Design of a PLL with improved locking range and its biomedical applications

This paper describes a phase locked loop employing a low voltage VCO using modified ECL inverter cells. The VCO circuit employed, features a positive feed back scheme to improve the operating frequency. The phase detector used in the PLL also uses a positive feedback scheme to improve the locked range and to reduce supply voltage of operation of the entire circuit. An improvement of locked range of around 35% was obtained from circuit simulation (using PSPICE) as well as from practical circuit, using discrete components. The minimum supply voltage required here is 2.5 volts. Some biomedical applications of this PLL are also proposed.     

V-band harmonic injection-locked frequency divider using cross-coupled FETs

A V-band 1/2 frequency divider is developed using harmonic injection-locked oscillator. The cross-coupled field effect transistors (FETs) and low quality-factor microstrip resonator are employed as a wide-band oscillator to extend the locking bandwidth. The second harmonic of free-running oscillation signal is injected to the gates of cross-coupled FETs for high-sensitivity superharmonic injection locking. The fabricated microwave monolithic integrated circuit frequency divider using 0.15-/spl mu/m GaAs pHEMT process showed a maximum locking range of 7.4 GHz (from 65.1 to 72.5 GHz) under a low power dissipation of 100 mW. The maximum single-ended output power was as high as -3 dBm.     

2.488 Gbit/s时钟数据恢复电路的设计

利用Cadence集成电路设计软件,基于SMIC 0.18 μm 1P6M CMOS工艺,设计了一款2.488 Gbit/s三阶电荷泵锁相环型时钟数据恢复(CDR)电路.该CDR电路采用双环路结构实现,为了增加整个环路的捕获范围及减少锁定时间,在锁相环(PLL)的基础上增加了一个带参考时钟的辅助锁频环,由锁定检测环路实时监控频率误差实现双环路的切换.整个电路由鉴相器、鉴频鉴相器、电荷泵、环路滤波器和压控振荡器组成.后仿真结果表明,系统电源电压为1.8V,在2.488 Gbit/s速率的非归零(NRZ)码输入数据下,恢复数据的抖动峰值为14.6 ps,锁定时间为1.5μs,功耗为60 mW,核心版图面积为566 μm×448μm.     

由RTD/MOSFET构成的压控振荡器的设计与实现

提出了一种基于负阻器件共振隧穿二极管(RTD)与MOSFET结合的新型压控振荡器(VCO),并利用了高级设计系统(ADS)软件对该振荡器的可行性进行了电路仿真,利用分立RTD、MOSFET器件实现了此种VCO,实际调频范围在20～26 MHz之间。RTD与三端器件的连接方式不同可呈现不同的调制I-V特性,这种调制特性对基于RTD的振荡电路的频率也会产生影响。通过深入研究这种调制对振荡电路频率产生的影响,得到多种不同于常规方法的电压控制频率方式,其中一些具有很好的线性度。因此该电路的研究对于RTD在高频、高速振荡电路中的进一步应用具有重要意义。     

利用光电振荡器实现10Gbit/s NRZ码时钟的直接提取和码型转换

本文所研究的光电振荡器（OEO）是一种高速光电混合环路，其振荡频率可以被锁定于外界信号的数据率，本文利用OEO首次实现10Gbit/s的非归零码（NRZ）时钟提取，获得了时间抖动小于0.4ps的时钟信号，测得OEO的注入锁定频率范围可达800kHz。实验中发现OEO中调制器的偏置电压对OEO的注入锁定范围有很大影响。合理控制OEO的工作条件，在进行时钟提取的同时，还可以实现NRZ码到RZ（归零）码的码型转化。将转换后的RZ码进行了160km传输，结果证明这种码型适合传输，该实验说明OEO可以用作不同码型光网络中间的码型转化节点。     

Low cost microwave oscillator using substrate integrated waveguide cavity

A topology is proposed for designing a low-cost microwave oscillator. This new feedback oscillator makes use of a substrate integrated waveguide (SIW) cavity that acts as a frequency selector as well as a feedback-coupling device. The oscillator is stabilized by using an injection-locking scheme. A 12.02-GHz oscillator prototype was designed. Experimental results for phase noise, locking range, and quality factor of the new circuit are presented. An external Q of 178 was measured.     

基于注入锁定技术的非接触式免校准脉搏检测传感器

为了实现手腕脉搏检测系统的免校准脉冲检测,提出了一种基于注入锁定原理的邻近耦合射频传感器。该传感器由两个主要部分组成,包括谐波振荡器和具有压控振荡器的锁相回路（PLL）合成器。谐波振荡器由具有两个端口的微带谐振器（叉指电极机构）制成的,该微带谐振器可将桡动脉的膨胀或收缩转换为阻抗变化。然后,PLL合成器通过锁相振荡器将频率变化转换为直流电压内的变化。测量结果表明,由于桡动脉的变化,谐振器的阻抗变化会导致谐波振荡器产生高达0.68 MHz的频率变化。在脉搏的一个周期内,测得的电压峰间值为10-15mV。证明了提出传感器可用于有效的非接触式手腕脉搏检测系统。     

约瑟夫森阵列振荡器的相位锁定分析

系统地研究了超导亚毫米波阵列振荡器的相位锁定问题。为使超导振荡器达到高工作频率、窄线宽和高稳定的性能，约瑟夫森结与结之间的相位必须相互锁定。相位锁定可以通过结与结之间的耦合电路得以实现。通过对振荡器的各种耦合电路的比较表明，蝴蝶领结天线结构是一个比较适合约瑟夫森振荡器相位锁定的耦合电路。本文提出了一种超导亚毫米波阵列振荡器模型并对其进行了模拟计算与分析，仿真得出了振荡器各项参数值，并给出了相位锁定的条件。     

An X‐Band Carbon‐Doped InGaP/GaAs Heterojunction Bipolar Transistor MMIC Oscillator

This paper addresses a fully‐integrated low phase noise X‐band oscillator fabricated using a carbon‐doped InGaP heterojunction bipolar transistor (HBT) GaAs process with a cutoff frequency of 53.2 GHz and maximum oscillation frequency of 70 GHz. The oscillator circuit consists of a negative resistance generating circuit with a base inductor, a resonating emitter circuit with a microstrip line, and a buffering resistive collector circuit with a tuning diode. The oscillator exhibits 4.33 dBm output power and achieves ?127.8 dBc/Hz phase noise at 100 kHz away from a 10.39 GHz oscillating frequency, which benchmarks the lowest reported phase noise achieved for a monolithic X‐band oscillator. The oscillator draws a 36 mA current from a 6.19 V supply with 47.1 MHz of frequency tuning range using a 4 V change. It occupies a 0.8 mm × 0.8 mm die area.     

GPS射频接收芯片中低功耗压控振荡器的设计

设计了一种应用于GPS射频接收芯片的低功耗环形压控振荡器.环路由5级差分结构的放大器构成.芯片采用TSMC 0.18 μm CMOS工艺,核心电路面积0.25 mm×0.05 mm.测试结果表明,采用1.75 V电源电压供电时,电路的功耗约为9.2 mW,振荡器中心工作频率为62 MHz,相位噪声为-89.39 dBc/Hz @ 1 MHz,该VCO可应用于锁相环和频率合成器中.     

A wide-locking range 6-phase divide-by-3 injection-locked frequency divider

A 6-phase divide-by-3 CMOS injection locked frequency dividers (ILFDs) have been proposed and implemented in a 0.35 μm CMOS process. The ILFD circuits are realised with a 3-stage double cross-coupled CMOS ring oscillator. The self-oscillating voltage controlled oscillator (VCO) is injection-locked by 3th-harmonic input to obtain the division factor of 3. Measurement results show that as the supply voltage varies from 1.2 to 3.5 V, the free-running frequency is from 0.136 to 0.7 GHz. At the incident power of ?5 dBm, the locking range in the divide-by-3 mode is from the incident frequency 0.38–2.31 GHz.     

Design of a three-stage ring-type voltage-controlled oscillator with a wide tuning range by controlling the current level in an embedded delay cell

This paper presents a new design for a three-stage voltage-controlled differential ring oscillator embedded with a delay cell for a wide tuning range from 59 MHz to 2.96 GHz by adjusting the current level in the delay cell. The ring oscillator consists of a voltage-to-current converter, coder circuit, three-stage ring with delay cells, and current monitoring circuit to extend the tuning range of the proposed voltage-controlled oscillator. Each functional block has been designed for a minimum power consumption using the TSMC 0.18 μm CMOS technology. We simulate the performances of the proposed voltage-controlled oscillator in terms of phase noise, power consumption, tuning range, and gain. Our simulation results show that the proposed oscillator has the linear frequency–voltage characteristics over a wide tuning range. At each tuning range (mode), the calculated phase noise of the proposed ring oscillator at each tuning range (mode) was −87, −85, −81, and −79 dBc/Hz at a 1 MHz offset from the center frequency. The DC power of the proposed voltage-controlled oscillator consumed 0.86–3 mW under a 1.8 V supply voltage.     

A dual-gate 2nd/3rd-order subharmonic injection-locked oscillator in GaAs PHEMT

A dual-gate subharmonic injection-locked oscillator (SILO) has been designed and fabricated in 0.5 μm GaAs PHEMT process for millimeter-wave communication applications. Specifically, this study proposes a dual-gate circuit topology to achieve a high-frequency oscillator with a large output signal power. The proposed dual-gate transistor also performs a wideband negative resistance characteristic by which the self-oscillation frequency can easily be determined with a proper resonator. The measured self-oscillation frequency of the proposed SILO is approximately 49 GHz, and the frequency tuning range is adjustable from 48.7 GHz to 49.7 GHz with an output power of 8 dBm. By injecting a 2nd-order (~24.5 GHz) subharmonic signal into the dual-gate SILO, the maximum locking range of 5.6 GHz can be approached at an input power of 11 dBm without any self-oscillation frequency tuning. With changing the input frequency to be a 3rd-order subharmonic injection (~16.3 GHz), an output locking range of 2.9 GHz also can be achieved. The measured phase noises of the output signals from 2nd- and 3rd-order subharmonic injections are −101 and −100 dBc/Hz, respectively, at 100-kHz offset frequency.     

Wide-locking range ÷3 series-tuned injection-locked frequency divider

A new wide locking range series-tuned (ST) divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process is presented. The ÷3 ILFD circuit is realized with a ST cross-coupled n-core MOS LC-tank oscillator. Two direct-injection MOSFETs in series are used as a frequency doubler and a dynamic linear mixer to widen the locking range. The power consumption of the ILFD core is 10.56 mW. The divider’s free-running frequency is tunable from 3.529 to 3.828 GHz by tuning the varactor’s control bias, and at the incident power of 0 dBm the maximum locking range is 2.3 GHz (21.6 %), from the incident frequency 9.5 to 11.8 GHz. The operation range is 2.5 GHz (23.7 %), from 9.3 to 11.8 GHz.     

一种UHF频段小数分频频率综合器设计与实现

基于130 nm CMOS工艺设计了一款特高频(UHF)频段的锁相环型小数分频频率综合器.电感电容式压控振荡器(LC VCO)片外调谐电感总值为2 nH时,其输出频率范围为1.06～1.24 GHz,调节调谐电感拓宽了频率输出范围,并利用开关电容阵列减小了压控振荡器的增益.使用电荷泵补偿电流优化了频率综合器的线性度与带内相位噪声.此外对电荷泵进行适当改进,确保了环路的稳定.测试结果表明,通过调节电荷泵补偿电流,频率综合器的带内相位噪声可优化3 dB以上,中心频率为1.12 GHz时,在1 kHz频偏处的带内相位噪声和1 MHz频偏处的带外相位噪声分别为-92.3和-120.9 dBc/Hz.最小频率分辨率为3 Hz,功耗为19.2 mW.     

一种L、S波段微机械压控振荡器

报道了一种中心频率为2GHz的电感电容(LC)压控振荡器,其谐振回路由微机械可变电容和键合线电感构成。微机械可变电容采用与集成电路兼容的表面微机械工艺制造,在2GHz时其Q值约为32.6,当调节电压从0V增大到12V时,电容量变化范围为25%。通过键合技术将微机械可变电容与有源电路集成在一起,制备了MEMSVCO器件,测试结果表明,载波频率为2.004GHz时,VCO的单边带相位噪声为-103.5dBc/Hz@100kHz,输出功率为12.51dBm。调频范围约为4.8%。     

基于基片集成波导的W波段基波注入锁定谐波振荡器

研制了一种基于基片集成波导的W波段平面注入锁定谐波振荡器.为了获得大的注入功率,注入锁定谐波振荡器采用基波端口强耦合结构,利用谐波提取技术的频率倍频作用,自由振荡输出频率在90.2 GHz附近.当基波注入信号在45.08 GHz附近时,锁定带宽大干120 MHz,输出功率大于6.5 dBm.将该平面集成的注入锁定谐波振荡器与低频参考信号同步,能够产生稳定的W波段低相噪信号.     

基于基片集成波导谐振器的压控振荡器设计

设计了一种基于基片集成波导谐振器的X波段压控振荡器。首先分析了串联反馈式振荡器以及基片集成波导谐振器的理论,然后在高频电磁仿真软件ADS中进行仿真和设计,并通过将变容管合理地引入谐振器,实现了电调谐的目的。最终设计完成了一个工作于X波段的基片集成波导压控振荡器。此压控振荡器与传统的介质压控振荡器(DRO)相比,具有稳定性高、平面化以及成本低的优点。由于采用了ADS中的联合仿真功能进行振荡器的设计,仿真结果的准确性得到了提高,减小了实物的调试工作量。测试结果为:工作频率为7 GHz,调谐范围为30 MHz,输出功率≥7 dBm,谐波抑制度≥22 dBc,相位噪声优于-106 dBc/Hz@100 kHz。     

一种用于开关电源中的双极型高频振荡器

文章提出了一种基于2μm双极型工艺设计、应用于DC/DC开关电源中的高频振荡电路.该模块产生时钟信号,该时钟信号的频率可以随着负载和电源电压的变化而变化.我们用Cadence Spectre仿真工具对电路的工作状态进行仿真,结果表明该电路在宽电源输入和高、低温范围内都具有良好的性能.本振荡电路不但功能良好,而且结构简单...     

单片CDCTA-C低功耗电控调谐双模式三阶正交振荡器的设计

针对振荡器功耗大和振荡频率低的问题,提出了一种基于电流差分级联跨导放大器的三阶正交振荡电路.该电路仅使用一个电流差分级联跨导放大器和三个接地无源电容,可以同时产生两组等幅正交电流信号和一组等幅正交电压信号.电路结构简单,功耗低至1.8mW,最大灵敏度绝对值仅0.5,振荡频率可达10MHz数量级,而且振荡条件和震荡频率可相互独立地电控调谐.计算机模拟和流片芯片测试结果验证了理论分析的正确性.