Efficient March Tests for a Reduced 3-Coupling and 4-Coupling Faults in Random-Access Memories

This paper presents two new march test algorithms, MT-R3CF and MT-R4CF, for detecting reduced 3-coupling and 4-coupling faults, respectively, in n × 1 random-access memories (RAMs). To reduce the length of the tests, only the coupling faults between physically adjacent memory cells have been considered. The tests assume that the storage cells are arranged in a rectangular grid and that the mapping from logical addresses to physical cell locations is known completely. The march tests need 30n and 41n operations, respectively. In this paper any memory fault is modelled by a set of primitive memory faults called simple faults. We prove, using an Eulerian graph model, the ability of the test algorithms to detect all simple coupling faults. This paper also includes a study regarding the ability of the test MT-R3CF to detect interacting linked 3-coupling faults. This work improves the results presented in [1] where a similar model of reduced 3-coupling faults has been considered and a march test with 38n operations has been proposed. To compare these new march tests with other published tests, simulation results are presented in this paper.     

CMOS存储器中地址译码器的开路故障及其测试

CMOS存储器中地址译码器的开路故障不能被常用的推进测试算法可靠地测试出。本文首先对CMOS存储器中地址译码器的开路故障进行了分析和分类,得出了其中有一类开路故障不能用常用的测试算法可靠的测试出,然后给出了测试该类开路故障的测试方法以及针对该类开路故障的容错性设计方案。     

多端口功率分配器S参数的计算机分析

本文给出复杂网络任意端口连接理论，从而可以方便地进行多端口功率分配器的Ｓ参数计算机分析，理论计算与实测结果作了比较，这一理论也适用于其它多端微波元件的分析。     

Near-optimal tests for classes of write-triggered coupling faults in RAMs

This article is concerned with the detection of write-triggered coupling faults and toggling faults (certain double coupling faults) in n × 1 random-access memories (RAMs), where n is the number of one-bit words in the memory. In an earlier article we showed that any functional test that detects all multiple coupling faults must have a length of at least 2n ² + 3n. Since such a test is prohibitively long, given modern RAM capacities, we study more manageable subclasses of the class of all coupling faults. We show that there exist two hierarchies of fault models corresponding to nested subclasses of toggling faults and coupling faults, respectively, of increasing maximum multiplicities. We then identify optimal or near-optimal tests for two classes of toggling faults and five classes of coupling faults; these tests are of order n or nlog₂ n.This work was supported by the Natural Sciences and Engineering Research Council of Canada under Grants OGP0105567 and OGP0000871, and by the Information Technology Research Centre of Ontario.     

内嵌RAM的液晶显示控制驱动器

讨论一种液晶控制驱动器的设计及使用方法。根据设计要求，阐述了每个分模块的设计思想与设计方法，并进行了数模混合仿真。     

Trade-offs in scan path and BIST implementations for RAMs

In this article we propose efficient scan path and BIST schemes for RAMs. Tools for automatic generation of these schemes have been implemented. They reduce the design effort and thus allow the designer to select the more appropriate scheme with respect to various constraints.     

广义耦合矩阵在多工器设计中的应用

介绍一种新型的适用于耦合谐振器网络的多端口耦合矩阵,它是对过去的双端口网络耦合矩阵的推广。应用多端口网络耦合矩阵可以方便地优化综合多工器,这样得到的多工器由于没有额外的消抗网络,相比过去的设计方案要小型而紧凑得多。通过仿真试验,验证了其有效性,及与理论的一致性。     

暗室用吸波材料大入射角吸波特性测试方法研究

本文介绍了根据对比原理测试吸波材料性能的一种方法,把通常采用的弓形法和RCS法进行了对比,指出弓形法在大入射角度情况下测试存在的困难,而在大的微波暗室内可以较好地解决大入射角测试的问题,最后给出了一组在RCS暗室内进行材料测试的结果,并对测试结果进行了分析。     

XCP-based transmission control mechanism for optical packet switched networks with very small optical RAM

According to a famous rule-of-thumb, buffer size of each output link of a router should be set to bandwidth-delay product of the network, in order to achieve high utilization with TCP flows. However, ultra high speed of optical networks makes it very hard to satisfy this rule-of-thumb, especially with limited choices of buffering in the optical domain, because optical RAM is under research and it is not expected to have a large capacity, soon. In this article, we evaluate the performance of our explicit congestion control protocol-based architecture designed for very small Optical RAM-buffered optical packet switched wavelength division multiplexing networks with pacing at edge nodes in order to decrease the required buffer size at core nodes. By using a mesh topology and applying TCP traffic, we evaluate the optical buffer size requirements of this architecture and compare with a common proposal in the literature.

基于双口RAM核监测数字示波器设计研究

在核监测中,常将各种传感器输出的信号通过A／D转换器转换为数字信号,然后利用数字信号处理技术对各种核信号进行数字处理。为了准确测量核信号数字波形的各种参数,对基于FPGA双口RAM的数字示波器进行了设计和测试分析。实验表明,该数字示波器能准确获取核信号的数字波形及各种参数的值,可对核信号的波形进行录制、回放和精确分析,为核监测及其仪器准确设计提供有力的保证。     

基于FPGA的双口RAM与PCI9052接口设计

为了解决PCI9052和双口RAM之间读写时序不匹配的问题,本设计采用可编程器件来实现它们之间的接口电路。此电路可以使系统更加紧凑。核心逻辑部分采用有限状态机实现,使控制逻辑直观简单,提高了设计效率。通过仿真工具ModelSim Se对该接口电路进行了验证,得出的仿真波形符合要求。     

FPGA中嵌入式块存储器的IP软核设计

以集成电路的快速发展与广泛应用为契机,针对FPGA开发过程中IP软核可复用的特点,提出一种提升FPGA嵌入式块存储器工作频率的IP软核设计方法。利用软件对不同读写类型和不同输入位宽的数据进行预处理,获取所需的硬件资源开销,并生成相应的硬件描述语言。IP软核设计时,在使用固定硬件资源的情况下,通过优化数据预处理方法,以及改变在综合阶段布局布线的处理结果,提高了工作频率。对设计的IP软核进行测试验证,结果表明,该设计方法生成的IP软核的功能和性能指标均符合设计要求,其工作频率最高可提升25.56%。     

相变存储器驱动电路的设计与实现

介绍了一种新型的相变存储器驱动电路的基本原理,设计了一种依靠电流驱动的驱动电路,整体电路由带隙基准电压源电路、偏置电流产生电路、电流镜电路及控制电路组成.该结构用于16Kb以及1 Mb容量的相变存储器芯片的设计,并采用中芯国际集成电路制造(上海)有限公司的0.18μm标准CMOS工艺实现.该驱动电路通过Hspice仿真,表明带隙基准电压、偏置电流均具有较高的精度,取得了良好的仿真结果,在16 Kb相变存储器芯片测试中,进一步验证了以上仿真结果.     

含存储器数字电路板的TPS开发研究

提出了含存储器数字电路板的两种测试矢量集(TPS)开发方案.对含少量存储器芯片的电路板采用结构化的测试方案,即将RAM等效成时序电路模型,利用时序电路ATPG软件进行测试生成.对以RAM为主的存储器板提出了一种功能测试方案,采取压缩地址空间的方法,对RAM阵列进行读写操作.实际应用证明,这两种方案较好地满足了实际应用中的需要.     

分布并行实时系统的互连技术研究

分布并行实时系统严格划分为硬实时和软实时两类系统。针对直升机工程模拟器和航空电子综合系统这两种实时性不同的系统的网络互连,分别给出了解决方案。特别是对硬实时系统,提出了基于多端口静态存储器和多端口收发器的并行内存实时网,最大优点是没有高层通信协议,且使所有的分系统能并行与中心节点交换数据,能最大限度地降低总传输延时。     

一种基于双端口RAM的高速数据采集系统设计

文章给出了一种基于双端口RAM技术的高速数据采集系统的设计。采用将高速双端口RAM映射为主机内存并构造成环状缓冲区的方法,实现了高速DC数据流实时采集与主机处理的并行操作。     

Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata

Quantum-dot cellular automata is one of the candidate technologies used in Nano scale computer design and a promising replacement for conventional CMOS circuits in the near future. Since memory is one of the significant components of any digital system, designing a high speed and well-optimized QCA random access memory (RAM) is a remarkable subject. In this paper, a new robust five-input majority gate is first presented, which is appropriate for implementation of simple and efficient QCA circuits in single layer. By employing this structure, a novel RAM cell architecture with set and reset ability is proposed. This architecture has a simple and robust structure that helps achieving minimal area, as well as reduction in hardware requirements and clocking zone numbers. Functional correctness of the presented structures is proved by using QCADesigner tool. Simulation results confirm efficiency and usefulness of the proposed architectures vis-à-vis state-of-the-art.     

高性能低功耗高速缓存的V-LRU RAM单周期清零技术

提出并实现了一种高速缓存的V-LRU RAM单周期清零技术。运行操作系统的CPU在不同任务之间切换时,需要对V-LRU RAM清零。使用传统的计数器依次清空V-LRU RAM的各行,CPU会白白浪费很多个时钟周期。在一个时钟周期对V-LRU RAM清空,可以大大提高CPU的性能。在四路组相联的高速缓存设计中,容量为16k、8k和4k字节时,使用该技术可以将以前的256、128和64个时钟周期降低到只有1个时钟周期。基于SMIC 0.13μm工艺,实现该技术的硬件电路面积为6 312.8μm2,且高速缓存的缺失率保持在非常低的水平。这种技术同样适用于对RAM需要单周期清空的场合。     

Test Generation for Mixed-Signal Devices Using Signal Flow Graphs

We describe a new reverse simulation approach to analog and mixed-signal circuit test generation that parallels digital test generation. We invert the analog circuit signal flow graph, reverse simulate it with good and bad machine outputs, and obtain test waveforms and component tolerances, given circuit output tolerances specified by the functional test needs of the designer. The inverted graph allows backtracing to justify analog outputs with analog input sinusoids. Mixed-signal circuits can be tested using this approach, and we present test generation results for two mixed-signal circuits and four analog circuits, one being a multiple-input, multiple-output circuit. This analog backtrace method can generate tests for second-order analog circuits and certain non-linear circuits. These cannot be handled by existing methods, which lack a fault model and a backtrace method. Our proposed method also defines the necessary tolerances on circuit structural components, in order to keep the output circuit signal within the envelope specified by the designer. This avoids the problem of overspecifying analog circuit component tolerances, and reduces cost. We prove that our parametric fault tests also detect all catastrophic faults. Unlike prior methods, ours is a structural, rather than functional, analog test generation method.