Moving-average output interface for digital stochastic computers

A new logic circuit suitable for use as an output interface for digital stochastic computers is presented. The logic element is based on the theory of moving averages, and is demonstrated to provide a significant improvement in transient-response characteristics, without loss in accuracy.     

Adaptively designed test logic for digital circuits

Adaptive n-tuple pattern-recognition techniques in their hardware embodiment may be used to design test circuits for logic systems which indicate the presence of a fault. The principles of this concept are explained and early results obtained with realistically scaled circuits are presented.     

Comment: Moving-average output interface for digital stochastic computers

An improvement to obtain a reduced step-response time without loss in accuracy in a moving-average output interface circuit, by a simple modification, is suggested.     

Optimum criteria for output interfaces in digital stochastic computers

Optimum criteria are discussed for the evaluation of output interface systems in digital stochastic computers. In particular, the ideal probability sensing, device is described, as well as a practical realisation of a variable-accuracy averager.     

Power rail logic: a low power logic style for digital GaAs circuits

This paper describes a new logic style called Power Rail Logic (PRL), which is compatible with direct-coupled FET logic (DCFL) circuits. Multiplexors, latches, flip-flops, and exclusive-OR gates can be built using this logic style. Compared to DCFL, PRL uses fewer transistors, has larger noise margins, and up to 40% lower power-delay products. A test chip containing 32-b barrel shifters designed in DCFL and in PRL was successfully fabricated and tested. Test results are given for both circuits     

Crosstalk noise reduction in synthesized digital logic circuits

As CMOS technology scales into the deep submicrometer regime, digital noise is becoming a metric of importance comparable to area, timing, and power, for analysis and design of CMOS VLSI systems. Noise has two detrimental effects in digital circuits: First, it can destroy logical information carried by a circuit net. Second, it causes delay uncertainty: Non critical paths might become critical because of noise. As a result, circuit speed becomes limited by noise, primarily because of capacitive coupling between wires. Most design approaches address the crosstalk noise problem at the layout generation stage, or via postlayout corrections. With continued scaling, too many circuit nets require corrections for noise, causing a design convergence problem. This work suggests to consider noise at the gate-level netlist generation stage. The paper presents a simplified analysis of on-chip crosstalk models, and demonstrates the significance of crosstalk between local wires within synthesized circuit blocks. A design flow is proposed for automatically synthesizing CMOS circuits that have improved robustness to noise effects, using standard tools, by limiting the range of gate strengths available in the cell library. The synthesized circuits incur a penalty in area/power, which can be partially recovered in a single postlayout corrective iteration. Results of design experiments indicate that delay uncertainty is the most important noise-related concern in synthesized static CMOS logic. Using a standard synthesis methodology, critical path delay differences up to 18% of the clock cycle time have been observed in functional blocks of microprocessor circuits. By using the proposed design flow, timing uncertainty was reduced to below 3%, with area and power penalties below 20%.     

Effect of logic family on radiated emissions from digital circuits

Radiated emissions were measured for simple digital circuits designed to operate with various logic families. Emissions in the near and far field were found to depend both on the circuit layout and the choice of logic family. However, the difference in peak emissions between any two logic families was found to be independent of the circuit layout. The greatest difference in peak emissions was between high-speed 74ACT logic and low-speed 4000 CMOS logic devices, with a mean value of approximately 20 dB. Emissions from a more complex circuit were compared with the measurements on simple loop circuits. Test circuits were used to measure the propagation delay, the rise and fall times, the maximum operating frequency and the transient switching currents between two successive logic gates for each logic family. Empirical formulas have been derived that relate relative peak emissions to these switching parameters. It is hoped that these will assist designers to assess the effect of choice of logic family on electromagnetic compatibility     

Reducing parasitic BJT effects in partially depleted SOI digital logic circuits

This paper presents four new circuit techniques that reduce the parasitic bipolar junction transistor (BJT) effect in digital dynamic logic circuits in partially depleted silicon-on-insulator (PD-SOI) technology. Simulation results have shown the proposed schemes to be effective at various operating voltages. Fully functional test circuits, incorporating some of the proposed techniques, have been designed, fabricated and tested in a 130 nm IBM PD-SOI technology. The measured silicon hardware data validate the simulation predictions and have demonstrated that the new techniques can be easily incorporated to improve the robustness of PD-SOI dynamic logic circuits.     

Most digital logic circuits in silicon films deposited on sapphire substrates

Details are given of the construction and performance of MOS transistors, logic elements and digital integrated circuits fabricated in silicon layers grown on sapphire substrates and processed on a p-channel enhancement MOST process. P-channel enhancement MOSTs with parameters similar to those of bulk silicon MOSTs, linear resistors with a high sheet resistivity and non-linear resistors are obtained. The use of non-linear resistors is shown to give static logic circuits with operating speeds 2–4 times faster than linear resistors. In addition node capacitance is reduced, the thick oxide MOST is eliminated and dielectric isolation between devices is obtained. Experimental and computer simulated results are given for the performance of a range of logic elements and circuits.     

Design of stochastic learning automata using adaptive digital logic elements

The hardware design of stochastic learning automata using adaptive digital logic elements is considered. Such techniques, based on digital stochastic computing, are shown to provide economical and fast learning-time computations. Experimental results are presented for a variety of linear learning algorithms.     

Self-timed logic circuits

Self-timed and asynchronous design techniques are currently proposed as a vehicle for pushing digital integrated circuits to higher levels of density and performance. The arguments for and against the adoption of these techniques are presented with illustrations from practical development projects. Some of the key principles behind self-timed operation are reviewed. Design tools to enable complex practical applications to be engineered are considered. For engineers who wish to find out more a selection of key references is provided     

Digital logic circuits

Recent progress in Josephson digital logic circuits is described. It is noted that changing the junction material from a lead alloy to niobium has dramatically improved process reliability, and that high-speed, low-power operations have been demonstrated at large-scale integrated-circuit levels. The first Josephson microprocessor, operated at 770 MHz, verified the potential of Josephson devices for future digital elements. The possibilities of the ultrafast Josephson computer, previously shelved because of a number of problems, are being actively reconsidered. The performance anticipated for Josephson digital circuits using high-temperature superconducting materials is also discussed     

Timing-driven logic restructuring for nano-hybrid circuits

As the feature size of the integrated circuits (ICs) scales down, the future of nano-hybrid circuit looks bright in extending Moore's Law. However, mapping a circuit to a nano-fabric structure is vexing due to connectivity constraints. A mainstream methodology is that a circuit is transformed into a nano-fabric preferred structure by buffer insertion to high fan-out gates. However, it may result in timing degradation. Logic replication is a traditional way to split high fan-out gates in logic synthesis but may not be suitable for high fan-out gates with high fan-ins. In this article, a timing-driven logic restructuring framework at the gate level is proposed. The proposed framework identifies the high fan-out gates from a given gate netlist according to the fan-out threshold, following by the restructuring of high fan-out gates through the application of logic replication and buffer insertion. To improve circuit timing from a global perspective, latent critical edges are identified to avoid entrapping critical paths during the restructuring. Experimental results on ISCAS benchmarks indicate that 8.51% timing improvement and 6.13% CPU time reduction can be obtained traded with 4.16% area increase on an average.     

Basic circuits for multi-valued sequential logic

Multi-valued logic circuits were presented as an alternative to well known binary logic. It has the potential of reducing the number of active elements and interconnection lines. More data may be transferred trough a single wire using logic signals having more than two levels. However, in spite of their potential advantages, developments in multi-valued systems are not satisfactory. In particular, it is very difficult to find circuits to implement the multilevel sequential circuits. The flip-flop is the basic building block of sequential circuits and may be used to design sequential circuits such as counter/dividers and other sequential circuits. In this regard, a new multilevel flip-flop, called the AB flip-flop, was developed and published by the authors recently (Sarica and Morgul, Electron Lett 47(5):297–298, 2011). In this paper we present a new latch and restoration circuit which improves the performance of the previously designed flip-flop circuit. It is also shown that any sequential circuit may be implemented by using this flip-flop.     

C-element multiplexing for fault-tolerant logic circuits

A novel approach to von Neumann multiplexing is considered, in which NAND gates are replaced by Muller C-elements. The new method is developed as an application of maximum a-posteriori (MAP) estimation, and is shown to be superior to NAND multiplexing in systems where transient upsets are the dominant fault species.     

Josephson nonlatching logic circuits

The authors describe nonlatching logic circuits that can be designed using Josephson junctions as the switching elements. The circuits require no current resetting and can be switched between their two logic states with a subnanosecond delay time. The switching behavior has been simulated numerically. The choice of parameters and junction types is analyzed. The distinctive features which make these circuits attractive are discussed.     

Dynamic logic CMOS circuits

A structure of dynamic CMOS logic based on the direct interconnection of p-channel logic and n-channel logic dynamic gates is reported. Prevention of glitches and other circuit problems are discussed. Application to a 16-bit parallel-adder design resulted in improved speed as well as important savings in layout area when compared to standard static design.     

Self-biasing Josephson logic circuits

A self-biasing network for Josephson logic circuits that permits wide variations in junction critical currents, resistors, and power supply voltage is presented. The self-biasing network automatically switches resistors in or out to make the gate currents track with the critical currents of the logic gates. Results of Monte Carlo statistical analyses of the tolerances of this scheme are presented as a function of amount of correlation between the critical currents of the logic device and the biasing network, amount of systematic variation on a chip, and number of junctions used in the biasing network. Results indicate that almost a factor of two larger variations in the critical currents of the Josephson junctions can be tolerated when the self-biasing network is used, without adverse impact on the gate delays and the power dissipation.     

All-refractory Josephson logic circuits

A process for the fabrication of Josephson integrated circuits is described which uses only refractory materials. The Josephson devices are Nb-Si-Nb tunnel junctions which are formed in the initial phase of the process. After depositing a Nb-Si-Nb `trilayer' over the entire substrate, the individual devices are isolated by the selective niobium anodization process (SNAP). Other materials used are molybdenum for the normal resistors and bias-sputtered SiO/SUB 2/ for additional insulator layers. The process uses only five photolithographic steps to produce circuits of the direct-coupled isolation type. This simplicity is achieved by using some layers for multiple purposes and by fabricating components with different functional purposes in a single step. For example, the lower electrode of the Josephson devices also functions as the ground plane and the contacts to the ground plane are actually large-area Josephson junctions formed simultaneously with the active devices. Low capacitance junctions (~0.025 pF//spl mu/m/SUP 2/) are produced with good uniformity.