结合垂直通孔分配的层次式三维混合布局算法

采用层次式方法,分而治之,减小了电路的设计规模,非常适用于大规模的混合模式布局,并且在布局阶段结合了垂直通孔的分配问题.布局阶段的通孔分配问题不仅使得三维布局问题得以简化,而且为布线做好了准备,减少了后面的调整,是布线阶段垂直通孔分配问题的良好指导.提出了2种垂直通孔分配算法:比较精确的匈牙利近似算法;比较快速的邻域搜索方法.将这2种算法与层次式三维混合模式布局流程紧密结合,有效地解决了三维混合模式布局问题.     

力驱动三维FPGA布局算法

三维FPGA布局问题的复杂度与二维情况相比成指数倍增长,布局算法需要花费大量时间,影响了FPGA物理设计效率.为了在保证布局质量的前提下缩短布局时间,提出以线长为优化目标基于力驱动的三维FPGA布局算法——3D-WFP.该算法由整体布局、坐标合法化和层划分、布局优化3个阶段组成,通过力驱动算法快速形成整体布局,为后续2个子过程提供更精确的逻辑单元位置和时延信息.提出三维空间填充曲线,根据位置和时延信息依次对逻辑单元按照三维空间填充曲线进行坐标合法化和层划分;修正了低温模拟退火进行布局优化的解空间,大大加快了低温模拟退火的收敛速度.与已有的三维FPGA布局算法比较,3D-WFP在保证运行时间和时延性能的前提下,有效地缩短了最终布局结果,缩短的总线长达7.38%.     

考虑通孔电阻和耦合电容的时延驱动的层分配算法

针对集成电路设计的多层布线问题,提出了以直接优化互连时延为目标、同时考虑通孔电阻与耦合电容的层分配算法.通过基于路径的时延分析寻找电路的关键路径,以通孔的时延模型和概率耦合电容模型作为层分配模型计算资源分配的代价,利用基于启发式的贪婪算法进行层分配.实验结果表明:该算法比只控制通孔和耦合电容数量的层分配策略具有更大的优势.     

一种基于通孔数最小化的多层通道布线算法

该文提出了一种基于通孔数量小化的多层通道布线算法，算法采用非预留层模，首先根据线网之间的位置关系利用模拟退火算法将各线网合理地分配到对应的布线层中去，然后利用遗传算法得到相关布线层中线网的最佳布线顺序向量，最的根据得到的顺序向量利用“沉积法”将各线网布于合理的通道上，该算法克服了传统通孔优化算法中原始布线对优化结果的不利影响，使通孔的优化达到很好的效果。     

圆柱形硅通孔的二维解析电容模型

精确提取三维芯片中硅通孔(Through Silicon Via,TSV)电容在三维芯片设计中至关重要.使用后钻孔工艺(Via-last technology)制造的TSV将贯穿导体层,使得TSV和互连线之间的耦合电容需要精确建模.文中提出的解析公式方法可以快速提取圆柱形TSV与互连线间的二维耦合电容.对于较短的互连线,文中采用基于最小二乘拟合得到的解析公式,而对于较长的互连线,使用基于电场模拟得到的解析公式.数值实验表明和商业软件Raphael相比,文中方法可以在结果误差不超过9.1%的情况下获得至少三千倍的加速.     

采用统一建模的拥挤度驱动三维芯片布局算法

三维芯片设计对于提高芯片性能以及减少线长显现了很好的优势,降低连线拥挤度是保证布线成功率和三维芯片实现的关键.为了解决三维芯片布局阶段的拥挤度问题,提出一种拥挤度驱动的三维芯片布局算法.该算法首先对拥挤度单元分布和线长等优化目标进行统一建模,利用二次规划求解单元位置,得到一个单元分布均匀、走线均匀以及线长优化的总体布局;然后利用拥挤度驱动的层分配算法将空间上均匀分布的单元分配到各个芯片层上;最后对各个芯片层进行详细布局,消除重叠,优化拥挤度和线长.实验结果表明,该算法能够改善走线拥挤度约15%,而线长仅有3%的增加.     

基于三维盒维数算法的城市分维计算

通过将传统的二维盒维数算法扩展到三维空间,提出了一个基于三维空间的盒维数计算方法。分别利用三维盒维数算法和二维盒维数算法计算城市的分维,通过对计算结果进行比较分析,观察到城市空间结构在第三维同样具有分形特征,证明传统城市分维计算中采用基于二维空间的分维算法或者简单地利用二维分维加1的方法表示三维分维都是不准确的,并进而给出正确的城市分维计算方法。     

面向标准单元三维布局的密度驱动划分方法

标准单元布局是超大规模集成电路自动化设计的一个关键阶段.针对三维布局问题,提出一种面向标准单元的密度驱动划分方法.该方法将三维布局区域划分成网格,并计算每个网格的单元密度,再根据网格单元密度将标准单元合理地划分到三维空间,可有效地减小标准单元与固定单元之间的重叠率,得到优化的划分结果.将文中方法嵌入到三维布局器中,对三维转换的benchmarks电路进行三维布局.实验结果表明,与原始三维布局器3D-Crust相比,该方法能够有效地减少HPWL 60.89%,减少运行时间20.54%.     

非默认规则线技术下基于多策略的时延驱动层分配算法

层分配作为超大规模集成电路物理设计中的关键环节,在决定布线方案的时延起到非常重要作用.为了优化集成电路的时延性能,现有的层分配工作通常注重优化互连时延和通孔数量,但要么未考虑到对线网中时序关键段的分配问题,要么对线网段的时序关键性的表示不够合理,最终使得算法的时延优化不够理想.为此,本文提出一种非默认规则线技术下基于多策略的时延驱动层分配算法,主要包含4种关键策略:(1)提出轨道数感知的层选择策略,增强层分配器为线网段选择合适布线层的能力;(2)提出多指标驱动的初始线网排序策略,综合考虑线长、信号接收器数和可布线轨道资源等多个指标为线网确定层分配优先级,从而获得高质量的初始层分配结果;(3)提出线网段调整策略,通过重绕线网,将时序关键段调整至上层布线层,优化线网时延;(4)提出线网段时延优化策略,对存在溢出线网进行拆线重绕,从而可同时优化时延和溢出数.实验结果表明,本文提出的算法相比于现有的层分配算法能够在时延和通孔数两个指标上均取得最佳,并且保证不产生溢出.     

基于蚁群算法的虚拟维修环境布局规划方法

虚拟维修拆装过程是虚拟维修的重要组成部分。现阶段拆装过程中产生的零部件一般都只是简单的以爆炸效果在虚拟三维空间环境中显示,然而当部件复杂,拆装后零部件较多时,这种显示效果容易产生视角上的重叠、混乱。为了解决虚拟维修拆装环境中的零部件在三维空间的布局问题,应用空间规划对零部件进行拆装顺序分类,将复杂三维布局转化为二维布局,同时使虚拟环境空间更具层次感。在运用定位法进行二维布局优化时,结合蚁群算法进行布局顺序寻优,提高了布局优化质量。最后通过对某航空发动机高压压气机虚拟拆装零部件布局进行仿真分析表明,提出的方法是可行的。     

Machine learning based effective linear regression model for TSV layer assignment in 3DIC

On the integration of 3D IC design, thermal management issues play a significant role. So, it is required to implement an effective approaches and solutions for integrating 3DIC. The TSV causes problems with the distinct coefficients of thermal expansion that induces mismatch strains and stresses. The major drawback of 3DIC is the thermal management issues which increases the power consumption through the current crowding, perhaps the temperature upraised by the slacked layers due to its heat generation. Several research has not been undergone in 3DIC utilizing machine learning approaches which is highly complicated. This paper firstly proposes an efficient ML model to achieve better reduction in wire length and temperature. An efficient linear regression model is preferred here in order to achieve significant performances in TSV layer assignment. The linear regression utilized gradient based approach where the error is predicted at every instance through tracing gradient cost function. An optimized TSV layer assignment is achieved with this flexible ELRM. The performance analysis of data shows that the proposed ELRM based TSV assignment achieved better wire length and temperature. The ISPD98 Circuit Benchmark Suite is utilized for result evaluation and it achieves improved TSV layer assignment through reducing wire length and temperature.     

Combining the ant system algorithm and simulated annealing for 3D/2D fixed-outline floorplanning

Three dimensional integrated circuits (3D ICs) can alleviate the problem of interconnection, a critical problem in the nanoscale era, and are also promising for heterogeneous integration. This paper proposes a two-phase method combining the ant system algorithm (AS) and simulated annealing (SA) to handle 3D IC floorplanning with fixed-outline constraints. In the first AS phase, the floorplans are constructed by sequentially packing the block one by one, and the AS is used to explore the appropriate packing order and device layer assignment for the blocks. When packing a block, a proper position including the coordinates and the appropriate layer in the partially constructed floorplan should be chosen from all possible positions. While packing the blocks, a probability layer assignment strategy is proposed to determine the device layer assignment of unpacked blocks. After the AS phase, the SA phase is used to perform further optimization. The proposed method can also be easily applied to 2D floorplanning problems. Compared with the state of the art 3D/2D fixed-outline floorplanner, the experimental results demonstrate the effectiveness of the proposed method.     

An augmented Lagrangian method for VLSI global placement

By ignoring some cell overlaps, global placement computes the best position for each cell to minimize the wirelength. It is an important stage in very large scale integration (VLSI) physical design, since circuit performance heavily depends on the placement results. In this paper, we propose an augmented Lagrangian method to solve the VLSI global placement problem. In the proposed method, a cautious dynamic density weight strategy is used to balance the wirelength objective and the density constraints, and an adaptive step size is used to obtain a trade-off between runtime and solution quality. The proposed method is tested on the IBM mixed-size benchmarks and the International Symposium on Physical Design 2006 placement contest benchmarks. Experimental results show that our global placement method outperforms the state-of-the-art placement approaches in terms of solution quality on most of the benchmarks.     

Deadlock-free generic routing algorithms for 3-dimensional Networks-on-Chip with reduced vertical link density topologies

3-Dimensional Networks-on-Chip (3D NoC) have emerged as the promising solution for scalability, power consumption and performance demands of next generation Systems-on-Chip (SoCs) interconnect. Due to the cost in terms of thermal, yield, chip area and design complexity, minimizing the number of Through-Silicon-Via (TSVs) in 3D ICs has become on the most important design issues. In this paper, we will present several stable, simple and deadlock-free generic routing algorithms for 3D NoCs with different reduced vertical link density topologies, which can maintain the 3D NoCs performance and save the system cost (TSV number, chip area, system power, etc.). The experimental results have been extracted from our cycle-accurate GSNOC simulator and have shown that our routing algorithms can maintain the system performance up to reducing 50% of TSVs number in comparison to the 100% TSVs number with ZXY routing algorithm configuration.     

3D System-on-Chip technologies for More than Moore systems

3D integration is a key solution to the predicted performance problems of future ICs as well as it offers extreme miniaturization and cost-effective fabrication of More than Moore products. Through silicon via (TSV) technologies enable high interconnect performance compared to 3D packaging. At present TSVs are associated with a relatively high fabrication cost, but research world wide strive to bring the cost down to an acceptable level. An example of a 3D System-on-Chip (3D-SOC) technology is to introduce a post backend-of-line TSV process as an optimized technology for heterogeneous system integration. The introduced ICV-SLID process, that combines both TSVs and bonding, enables 3D integration of fabricated devices. Reliability issues related to thermo-mechanical stress caused by the TSV formation and the bonding are considered. 3D-SOC technology choices made to realize a heterogeneous ultra-small IC stack for a wireless tire pressure monitoring system (TPMS) as an automotive application are described.     

低系统开销的多TSV子阵列联合数据传输方法

串扰抑制编码往往具有图形限制特性,在小规模硅通孔(through silicon via,TSV)阵列中应用时,可以在合理的编解码器面积开销下取得良好的串扰抑制效果.为了在大规模的TSV阵列中实现低系统开销的高质量数据传输,提出基于多TSV子阵列联合数据传输的方法.针对参与数据联合传输的子阵列最优数量问题,通过研究子阵...     

低功耗驱动的电路网表多级划分算法

在划分阶段因得不到实际线长值而无法精确计算功耗值.通过组合使用互连线的通路级数、通路级差和基本线长,提出一种新的独立线长预测方法.使用预测线长和开关活动性的乘积度量划分阶段的动态功耗,并将这一乘积作为权重赋给每条互连线;在聚类和细化处理阶段,尽量避免权重较大的互连线被分割,以实现低功耗驱动的多级划分.实验结果表明,该算法可有效地减小电路的功耗,并且对其他技术指标影响不大.     

考虑硅衬底效应的基于TSV的3D IC电源分配网络建模

基于硅通孔TSV的3D-IC在电源分配网络PDN中引入了新的结构--TSV，另外，3D堆叠使得硅衬底效应成为不可忽略的因素，因此为3D-IC建立PDN模型必须要考虑TSV以及硅衬底效应。为基于TSV的3D-IC建立了一个考虑硅衬底效应的3D PDN模型，该模型由P/G TSV对模型和片上PDN模型组成。P/G TSV对模型是在已有模型基础上，引入bump和接触孔的RLGC集总模型而建立的，该模型可以更好地体现P/G TSV对的电学特性；片上PDN模型则是基于Pak J S提出的模型，通过共形映射法将硅衬底效应引入单元模块模型而建立的，该模型可以有效地反映硅衬底对PDN电学特性的影响。经实验表明，建立的3D PDN模型可以有效、快速地估算3D-IC PDN阻抗。     

基于粒子群算法的移动边缘计算任务分配方法

为提高移动终端任务分配效率,降低计算能量损耗,提出基于粒子群算法的移动边缘计算任务分配方法。通过构建异构网络获取完整的需要分配的任务,明确任务分配时所需的特定条件,即分配消耗和时延等。将分配任务转化成寻找分配结果的最优解,构建最优解模型,利用粒子群算法对模型实施求解,经过不断迭代和更新,生成最优边缘计算任务的分配结果。实验结果表明,粒子群方法在分配任务数量为20~100之间时计算时间在1 s~3.3 s;当任务数量为100时,本文方法能耗仅为4107 J;粒子群方法在任务达到率达到100%时,其时延仅为12.5 ms;其任务分配计算时间短、能量消耗小和数据传输的时延短,能较好地满足实际应用需要。     

拥挤度驱动的总体布线层分配算法

针对多层布线问题，提出以拥挤度为驱动目标，完成布线资源的合理分配，同时达到布线层资源占用少和通孔数少等优化目标的层分配算法．首先采用启发式方法获得初始分配方案，然后通过模拟退火技术优化分配结果，最后采用试探策略优化层资源占用．工业实验数据表明，该算法能够实现线网层合理分配，获得满足拥挤度的优化解．