Clustered defect detection of high quality chips using self-supervised multilayer perceptron

During electrical testing, each die on a wafer must be tested to determine whether it functions as originally designed. When defects, including scratches, stains or localized failed patterns, are clustered on the wafer, the tester may not detect all of the defective dies in the flawed area. A testing factory must assign a few workers to check the wafers and hand-mark the defective dies in the flawed region or close to the flawed region, to ensure that no defective die is present in the final assembly. This work presents an automatic wafer-scale defect cluster identifier that uses a multilayer perceptron to detect the defect cluster and mark all of the defective dies. The proposed identifier is compared with an existing tool used in industry. The experimental results confirm that the proposed algorithm is more effective at identifying defects and outperforms the present approach.     

Image processing techniques for wafer defect cluster identification

Electrical testing determines whether each die on a wafer functions as originally designed. But these tests don't detect all the defective dies in clustered defects on the wafer, such as scratches, stains, or localized failed patterns. Although manual checking prevents many defective dies from continuing on to assembly, it does not detect localized failure patterns-caused by the fabrication process-because they are invisible to the naked eye. To solve these problems, we propose an automatic, wafer-scale, defect cluster identifier. This software tool uses a median filter and a clustering approach to detect the defect clusters and to mark all defective dies. Our experimental results verify that the proposed algorithm effectively detects defect clusters, although it introduces an additional 1% yield loss of electrically good dies. More importantly, it makes automated wafer testing feasible for application in the wafer-probing stage     

Optimization of Wafer Exposure Patterns Using a Two-Dimensional Cutting Algorithm

The semiconductor industry plays an integral role in Taiwan's manufacturing sector. Although defect reduction has received considerable attention to improve the yield rate, the problem of optimizing wafer exposure patterns has seldom been addressed. This study formulates the wafer exposure-patterning problem into a cutting and packing problem by adopting an innovative approach. We developed a two-dimensional cutting algorithm to maximize the number of dies that can be produced from a wafer to increase the gross die yield. The proposed algorithm is successfully implemented in a wafer fabrication factory. Experimental results validate the effectiveness of the proposed algorithm.     

An unsupervised neural network approach for automatic semiconductor wafer defect inspection

Semiconductor wafer defect inspection is an important process before die packaging. The defective regions are usually identified through visual judgment with the aid of a scanning electron microscope. Dozens of people visually check wafers and hand-mark their defective regions. Consequently, potential misjudgment may be introduced due to human fatigue. In addition, the process can incur significant personnel costs. Prior work has proposed automated visual wafer defect inspection that is based on supervised neural networks. Since it requires learned patterns specific to each application, its disadvantage is the lack of product flexibility. Self-organizing neural networks (SONNs) have been proven to have the capabilities of unsupervised auto-clustering. In this paper, an automatic wafer inspection system based on a self-organizing neural network is proposed. Based on real-world data, experimental results show, with good performance, that the proposed method successfully identifies the defective regions on wafers.     

Defect cluster recognition system for fabricated semiconductor wafers

The International Technology Roadmap for Semiconductors (ITRS) identifies production test data as an essential element in improving design and technology in the manufacturing process feedback loop. One of the observations made from the high-volume production test data is that dies that fail due to a systematic failure have a tendency to form certain unique patterns that manifest as defect clusters at the wafer level. Identifying and categorising such clusters is a crucial step towards manufacturing yield improvement and implementation of real-time statistical process control. Addressing the semiconductor industry’s needs, this research proposes an automatic defect cluster recognition system for semiconductor wafers that achieves up to 95% accuracy (depending on the product type).     

A novel defect detection and identification method in optical inspection

Optical inspection techniques have been widely used in industry as they are non-destructive. Since defect patterns are rooted from the manufacturing processes in semiconductor industry, efficient and effective defect detection and pattern recognition algorithms are in great demand to find out closely related causes. Modifying the manufacturing processes can eliminate defects, and thus to improve the yield. Defect patterns such as rings, semicircles, scratches, and clusters are the most common defects in the semiconductor industry. Conventional methods cannot identify two scale-variant or shift-variant or rotation-variant defect patterns, which in fact belong to the same failure causes. To address these problems, a new approach is proposed in this paper to detect these defect patterns in noisy images. First, a novel scheme is developed to simulate datasets of these 4 patterns for classifiers’ training and testing. Second, for real optical images, a series of image processing operations have been applied in the detection stage of our method. In the identification stage, defects are resized and then identified by the trained support vector machine. Adaptive resonance theory network 1 is also implemented for comparisons. Classification results of both simulated data and real noisy raw data show the effectiveness of our method.     

Wafer defect inspection by neural analysis of region features

Wafer defect inspection is an important process that is performed before die packaging. Conventional wafer inspections are usually performed using human visual judgment. A large number of people visually inspect wafers and hand-mark the defective regions. This requires considerable personnel resources and misjudgment may be introduced due to human fatigue. In order to overcome these shortcomings, this study develops an automatic inspection system that can recognize defective LED dies. An artificial neural network is adopted in the inspection. Actual data obtained from a semiconductor manufacturing company in Taiwan were used in the experiments. The results show that the proposed approach successfully identified the defective dies on LED wafers. Personnel costs and misjudgment due to human fatigue can be reduced using the proposed approach.     

基于局部与非局部线性判别分析和高斯混合模型动态集成的晶圆表面缺陷探测与识别

在复杂的半导体制造过程中,晶圆生产经过薄膜沉积、蚀刻、抛光等多项复杂的工序,制造过程中的异常波动都可能导致晶圆缺陷产生.晶圆表面的缺陷模式通常反映了半导体制造过程的各种异常问题,生产线上通过探测和识别晶圆表面缺陷,可及时判断制造过程故障源并进行在线调整,降低晶圆成品率损失.本文提出了基于一种流形学习算法与高斯混合模型动态集成的晶圆表面缺陷在线探测与识别模型.首先该模型开发了一种新型流形学习算法——局部与非局部线性判别分析法(Local and nonlocal linear discriminant analysis, LNLDA),通过融合数据局部/非局部信息以及局部/非局部惩罚信息,有效地提取高维晶圆特征数据的内在流形结构信息,以最大化数据不同簇样本的低维映射距离,保持特征数据中相同簇的低维几何结构.针对线上晶圆缺陷产生的随机性和复杂性,该模型对每种晶圆缺陷模式构建相应的高斯混合模型(Gaussian mixture model, GMM),提出了基于高斯混合模型动态集成的晶圆缺陷在线探测与识别方法.本文提出的模型成功地应用到实际半导体制造过程的晶圆表面缺陷在线探测与识别,在WM-811K晶圆数据库的实验结果验证了该模型的有效性与实用性.     

晶圆表面缺陷模式的在线探测与自适应识别研究

晶圆表面的缺陷通常反映了半导体制造过程存在的异常问题,通过探测与识别晶圆表面缺陷模式,可及时诊断故障源并进行在线调整。提出了一种晶圆表面缺陷模式的在线探测与自适应识别模型。首先该模型对晶圆表面的缺陷模式进行特征提取,基于特征集对每种晶圆模式构建相应的隐马尔科夫模型（Hidden Markov Model,HMM）,并提出基于HMM动态集成的晶圆缺陷在线探测与识别方法。提出的模型成功应用于WM-811K数据库的晶圆缺陷检测与识别中,实验结果充分证明了该模型的有效性与实用性。     

晶圆表面缺陷在线检测研究

针对准确与实时检测晶圆表面缺陷的需求,提出了一种基于主成分分析(Principal Component Analysis, PCA)和贝叶斯概率模型(Bayesian Probability Model, BPM)的在线检测算法。首先,改进双边滤波方法以消除晶圆表面图像中的噪声和突出晶圆表面的模式特征。然后,提取晶圆表面缺陷的Hu不变矩、方向梯度直方图(Histogram of Oriented Gradients, HOG)和尺度不变特征变换特征(Scale Invariant Feature Transform, SIFT)。接着,采用PCA方法对特征进行降维。最后,在离线建模阶段构建各种缺陷模式的BPMs;在在线检测阶段采用胜者全取(Winner-take-all, WTA)法判断缺陷的模式和构建新缺陷模式的BPMs。提出算法在WM-811K晶圆数据库中得到了87.2%的检测准确率。单副图像的平均检测时间为40.5ms。实验结果表明,提出算法具有较高的检测准确性与实时性,可以实际应用到集成电路制造产线的晶圆表面缺陷在线检测中。     

A sub-region one-to-one mapping (SOM) detection algorithm for glass passivation parts wafer surface low-contrast texture defects

Glass Passivation Parts (GPP) wafer texture defects are one of the most important factors affecting the accuracy of wafer defect detection. Template matching has local errors and low efficiency, and deep learning requires many training samples. In the early stage, defect training sample sets cannot be provided. This paper discusses the design of an effective GPP wafer grain region texture defect detection algorithm using a sub-region one-to-one mapping. A set of standard wafer datum is selected as the reference of grain region segmentation detection, and then the standard wafer images and test GPP wafer images are automatically calibrated and segmented, respectively. Then, a series of pre-processes were performed to equalize the sizes of the two grain-region images. Then the grain region was divided into an equal number of rectangular sub-regions of the same size according to the measurement precision requirement. The correlation degree of each test sub-region is judged by the designed three-channel RGB gray-scale similarity decision functions. Experiments show that the algorithm successfully achieved the necessary calibration and segmentation for the grain region. Compared with the template and histogram matching algorithms, the proposed method does not require a training set, the detection accuracy is significantly improved and the detection efficiency is up to 29.74 times better on average using the proposed algorithm.

     

A new intelligent SOFM-based sampling plan for advanced process control

Sample measurement inspecting for a process parameter is a necessity in semiconductor manufacturing because of the prohibitive amount of time involved in 100% inspection while maintaining sensitivity to all types of defects and abnormality. In current industrial practice, sample measurement locations are chosen approximately evenly across the wafer, in order to have all regions of the wafer equally well represented, but they are not adequate if process-related defective chips are distributed with spatial pattern within the wafer.In this paper, we propose the methodology for generating effective measurement sampling plan for process parameter by applying the Self-Organizing Feature Map (SOFM) network, unsupervised learning neural network, to wafer bin map data within a certain time period. The sampling plan specifies which chips within the wafer need to be inspected, and how many chips within the wafer need to be inspected for a good sensitivity of 100% wafer coverage and defect detection. We finally illustrate the effectiveness of our proposed sampling plan using actual semiconductor fab data.     

利用内容可寻址技术的存储器BISR方法

随着缺陷密度的增加,在存储器中设计冗余行或冗余列替换有缺陷的存储器单元已成为提高存储器成品率的常用方法.然而基于冗余行或冗余列的修复方法不仅对冗余资源的利用率较低、冗余分析算法较复杂,且受限于存储器生产厂商提供的冗余资源结构.针对此,提出了利用内容可寻址技术结合冗余行和冗余列来修复存储器的方法.该方法中,内容可寻址存储器不仅用于存储修复信息,还被用于当作冗余字替换故障字实现字修复,而冗余行和冗余列则分别用于修复行或列地址译码故障;并在译码逻辑输出端设计控制电路,避免对已修复的故障字进行访问.文中方法简单易行、面积开销小、利于扩展且修复效果好.实验结果表明,该方法在获得同样修复效率的情况下,冗余资源和内容可寻址存储器面积开销最小约为已有二维冗余修复方法的20%.     

基于改进Yolo v3的电连接器缺陷检测

针对电连接器缺陷检测目前存在自动化程度低、检测精度低、检测速度慢以及鲁棒性较差等问题,提出了一种改进的Yolo v3算法来检测电连接器的缺陷。首先采用K-means聚类算法对本文数据集进行聚类分析得到3种宽高比的候选框,针对本文缺陷对象提高检测精度;对主干网络第三个残差块输出的8倍降采样特征图进行4倍上采样,将得到的特征图与第二个残差块输出的2倍降采样特征图进行拼接得到融合特征检测层;将目标检测层之前经过的6个DBL单元改为2个DBL单元加上2个残差单元,以提高特征的复用与获取;另外本文选择单尺度特征图进行目标检测,而不是原网络的多尺度预测,既节省了计算量,又一定程度上避免误检。通过定性与定量的实验结果表明,本文改进后的Yolo v3算法对电连接器缺陷检测有着更好的性能以及速度,准确率为93.5%,相较于Faster R-CNN更加准确,原Yolo v3更加快速,基本上满足了工业现场对电连接器检测的要求。     

Defect-oriented testing and defective-part-level prediction

After an integrated circuit (IC) design is complete, but before first silicon arrives from the manufacturing facility, the design team prepares a set of test patterns to isolate defective parts. Applying this test pattern set to every manufactured part reduces the fraction of defective parts erroneously sold to customers as defect-free parts. This fraction is referred to as the defect level (DL). However, many IC manufacturers quote defective part level, which is obtained by multiplying the defect level by one million to give the number of defective parts per million. Ideally, we could accurately estimate the defective part level by analyzing the circuit structure, the applied test-pattern set, and the manufacturing yield. If the expected defective part level exceeded some specified value, then either the test pattern set or (in extreme cases) the design could be modified to achieve adequate quality. Although the IC industry widely accepts stuck-at fault detection as a key test-quality figure of merit, it is nevertheless necessary to detect other defect types seen in real manufacturing environments. A defective-part-level model combined with a method for choosing test patterns that use site observation can predict defect levels in submicron ICs more accurately than simple stuck-at fault analysis     

基于改进部分卷积的瑕疵布匹图像生成算法

针对工业生产中布匹瑕疵自动化检测模型训练时缺少带瑕疵位置信息的瑕疵布匹图像数据集的问题,本文提出了一种以改进的部分卷积网络作为基本框架的带瑕疵位置信息的瑕疵布匹图像生成模型EC-PConv.该模型引入小尺寸瑕疵特征提取网络,将提取出的瑕疵纹理特征与空白mask拼接起来形成带有位置信息和瑕疵纹理特征的mask,然后以修复方式生成带有瑕疵位置信息的瑕疵布匹图像,另外,本文提出一种结合MSE损失的混合损失函数以生成更加清晰的瑕疵纹理.实验结果表明,与最新的GAN生成模型相比,本文提出的生成模型的FID值降低了0.51;生成的瑕疵布匹图像在布匹瑕疵检测模型中查准率P和MAP值分别提高了0.118和0.106.实验结果表明,该方法在瑕疵布匹图像生成上比其他算法更稳定,能够生成更高质量的带瑕疵位置信息的瑕疵布匹图像,可较好地解决布匹瑕疵自动化检测模型缺少训练数据集的问题.     

Wafer defect pattern recognition by multi-class support vector machines by using a novel defect cluster index

Wafer yield is an important index of efficiency in integrated circuit (IC) production. The number and cluster intensity of wafer defects are two key determinants of wafer yield. As wafer sizes increase, the defect cluster phenomenon becomes more apparent. Cluster indices currently used to describe this phenomenon have major limitations. Causes of process variation can sometimes be identified by analyzing wafer defect patterns. However, human recognition of defect patterns can be time-consuming and inaccurate. This study presents a novel recognition system using multi-class support vector machines with a new defect cluster index to efficiently and accurately recognize wafer defect patterns. A simulated case demonstrates the effectiveness of the proposed model.     

Defective wafer detection using a denoising autoencoder for semiconductor manufacturing processes

Defective wafer detection is essential to avoid loss of yield due to process abnormalities in semiconductor manufacturing. For most complex processes in semiconductor manufacturing, various sensors are installed on equipment to capture process information and equipment conditions, including pressure, gas flow, temperature, and power. Because defective wafers are rare in current practice, supervised learning methods usually perform poorly as there are not enough defective wafers for fault detection (FD). The existing methods of anomaly detection often rely on linear excursion detection, such as principal component analysis (PCA), k-nearest neighbor (kNN) classifier, or manual inspection of equipment sensor data. However, conventional methods of observing equipment sensor readings directly often cannot identify the critical features or statistics for detection of defective wafers. To bridge the gap between research-based knowledge and semiconductor practice, this paper proposes an anomaly detection method that uses a denoise autoencoder (DAE) to learn a main representation of normal wafers from equipment sensor readings and serve as the one-class classification model. Typically, the maximum reconstruction error (MaxRE) is used as a threshold to differentiate between normal and defective wafers. However, the threshold by MaxRE usually yields a high false positive rate of normal wafers due to the outliers in an imbalanced data set. To resolve this difficulty, the Hampel identifier, a robust method of outlier detection, is adopted to determine a new threshold for detecting defective wafers, called MaxRE without outlier (MaxREwoo). The proposed method is illustrated using an empirical study based on the real data of a wafer fabrication. Based on the experimental results, the proposed DAE shows great promise as a viable solution for on-line FD in semiconductor manufacturing.     

A new scanning MEMS mirror

This paper introduces the development of a new MEMS-based optical mirror, which performs optical scanning function with discrete reflection angles in an out-of-plane configuration. The device was fabricated through Deep Reactive Ion Etching (DRIE) process on silicon-on-insulator (SOI) wafer, followed by assembly with two metalised glass dies. The optical mirrors can be tilted by electrostatic forces between the opposite electrodes on the SOI and glass dies. The most outstanding performance that can be expected from the device is the discrete and therefore, reliable tilting angle of the mirror, which is guaranteed by its unique mechanical structure and the electrostatically driven mechanism. In this paper, the working principle of the new MEMS mirror was presented, followed by the introduction of device design, mechanical simulation, microfabrication process, assembly solution, and some testing results. The potential application of this new MEMS mirror is for light beam scanning or optical sensing (detection).