Operation model of floating-Si-gate channel-corner-avalanche-transition (FCAT) nonvolatile memory devices

A write/erase model is described for FCAT nonvolatile memory devices which perform write/erase operations with 10–20 V pulses of less than 100-1 μs duration. The amplitude of the threshold voltage shift is analyzed as a function of the source and gate pulse amplitudes using a sample equivalent source circuit. The high level saturated threshold voltage, V_TH, obtained by electron injection into the floating gate and the low level saturated threshold voltage, V_TL, due to hole injection are shown to be linear functions of V_G and V_S, and the analysis agrees well with experimental results. The influence of series resistance, including substrate resistance, in the source circuit is also discussed.     

Characterization of scaled MANOS nonvolatile semiconductor memory (NVSM) devices

We have modeled and characterized scaled Metal–Al₂O₃–Nitride–Oxide–Silicon (MANOS) nonvolatile semiconductor memory (NVSM) devices. The MANOS NVSM transistors are fabricated with a high-K (K_A = 9) blocking insulator of ALD deposited Al₂O₃ (8 nm), a LPCVD silicon nitride film (8 nm) for charge-storage, and a thermally grown tunneling oxide (2.2 nm). A low voltage program (+8 V, 30 μs) and erase (?8 V, 100 ms) provides an initial memory window of 2.7 V and a 1.4 V window at 10 years for an extracted nitride trap density of 6 × 10¹⁸ traps/cm³ eV. The devices show excellent endurance with no memory window degradation to 10⁶ write/erase cycles. We have developed a pulse response model of write/erase operations for SONOS-type NVSMs. In this model, we consider the major charge transport mechanisms are band-to-band tunneling and/or trap-assisted tunneling. Electron injection from the inversion layer is treated as the dominant carrier injection for the write operation, while hole injection from the substrate and electron injection from the gate electrode are employed in the erase operation. Meanwhile, electron back tunneling is needed to explain the erase slope of the MANOS devices at low erase voltage operation. Using a numerical method, the pulse response of the threshold voltages is simulated in good agreement with experimental data. In addition, we apply this model to advanced commercial TANOS devices.     

Characterization of CoxNiyO hybrid metal oxide nanoparticles as charge trapping nodes in nonvolatile memory devices

The Co_xNi_yO hybrid metal oxide nanoparticles (HMONs) embedded in the HfO_xN_y high-k dielectric as charge trapping nodes of the nonvolatile memory devices have been formed via the chemical vapor deposition using the Co/Ni acetate calcined and reduced in the Ar/NH₃ ambient. A charge trap density of 8.96 × 10¹¹ cm^?2 and a flatband voltage shift of 500 mV were estimated by the appearance of the hysteresis in the capacitance–voltage (C–V) measurements during the ±5 V sweep. Scanning electron microscopy image displays that the Co_xNi_yO HMONs with a diameter of ～10–20 nm and a surface density of ～1 × 10¹⁰ cm^?2 were obtained. The mechanism related to the writing characteristics are mainly resulted from the holes trapping. Compared with those devices with the Co_xNi_yO HMONs formed by the dip-coated technique, memory devices with the Co_xNi_yO HMONs fabricated by the drop-coated technique show improved surface properties between the Co_xNi_yO HMONs and the HfON as well as electrical characteristics.     

Improvement of memory properties for MANOS-type nonvolatile memory devices with high-pressure wet vapor annealing

Effects of high-pressure wet vapor annealing (HPWA) on the memory properties of Metal/Alumina/Nitride/Oxide/Silicon (MANOS)-type flash memory devices are studied. The Oxide/Nitride/Alumina (ONA) stacks were annealed in a high-pressure wet vapor ambient (N₂:D₂O = 10 atm:2 atm) at 250 °C for 5 min. It is found that HPWA can effectively passivate the intrinsic defects of the Al₂O₃ film by oxygen species, leading to the improvement of blocking efficiency. The HPWA significantly improved the electrical and reliability characteristics of ONA stacks, such as leakage current density, saturation level of erase, charge loss rate through the blocking oxide, and memory window after the program and erase cycles. HPWA shows promise for future MANOS-type flash memory devices.     

A nonvolatile charge-addressed memory (NOVCAM) cell

A nonvolatile charge-addressed memory (NOVCAM) cell is described in a 64-bit shift register configuration. The charge address is performed by a charge-coupled device (CCD) shift register and the information is stored in metal-nitride-oxide-silicon (MNOS) nonvolatile sites located in parallel with the CCD shift register. The tunneling electric field strength across the thin-oxide MNOS structure is controlled by the magnitude of the charge transferred from the CCD register. The write, erase, and read modes of operation are discussed with typical /spl plusmn/20 V 10 /spl mu/s write/erase, and 2 V 2 /spl mu/s read conditions. Readout is accomplished by parallel stabilized charge injection from a diffused p/n junction to minimize access time to the first bit.     

Polyoxide thinning limitation and superior ONO interpoly dielectricfor nonvolatile memory devices

Results obtained from a study on thin interpoly dielectrics, especially for nonvolatile memories with stacked-gate structures, are presented. First, the key factors which dominate the leakage current in polyoxide are reviewed, and intrinsic limitations in thinner polyoxide for device applications are investigated considering defect densities and edge leakage current. Second, the ONO (oxide/nitride/oxide) structure which overcomes polyoxide-thinning limitations is described. This stacked film reveals superior electric-field strength due to the inherent electron-trapping-assisted process. UV erase characteristics for EPROM cells with ONO structure are discussed. The slower erasing speed for EPROM cells with ONO interpoly dielectric is due to the decrease in photocurrent flow from a floating gate to a control gate     

Thickness scaling limitation factors of ONO interpoly dielectricfor nonvolatile memory devices

This paper describes the scaling limitation factors of ONO interpoly dielectric thickness, mainly considering the charge retention capability and threshold voltage stability for nonvolatile memory cell transistors with a stacked-gate structure, based on experimental results. For good intrinsic charge retention capability, either the top- or bottom-oxide thickness should be greater than around 6 nm. On the other hand, a thicker top oxide structure is preferable to minimize degradation due to defects. It has been confirmed that a 3.2 nm bottom-oxide shows detectable threshold voltage instability, but 4 nm does not. Effective oxide thickness scaling down to around 13 nm should be possible for flash memory devices with a quarter-micron design rule     

Investigation of channel hot electron injection by localized charge-trapping nonvolatile memory devices

A novel measurement method to extract the spatial distribution of channel hot electron injection is described. The method is based on characterization of localized trapped-charge in the nitride read-only memory (NROM) device. The charge distribution is determined by iteratively fitting simulated subthreshold and gate induced drain leakage (GIDL) currents to measurements. It is shown that the subthreshold and the GIDL measurements are sensitive to charge trapped over the n+ junction edge. Their characteristics are determined by the trapped charge width, density and location and the associated fringing field. Extremely high sensitivity of the GIDL measurement to localized charge over the n+ junction is demonstrated. The extracted charge distribution width is shown to be /spl sim/40 nm, located over the junction edge.     

OLED with a controlled molecular weight of the PVK (poly(9-vinylcarbazole)) formed by a reactive ink-jet process

An ink-jet printing method was proposed to solve several conventional problems of ink jet process. PVK (poly(9-vinylcarbazole)) thin film was synthesized and simultaneousely patterned by the reactive ink-jet process (RIP). Gel permeation chromatography shows a linear relationship between the molecular weight of the PVK and the reaction time. The as-synthesized PVK with a controlled molecular weight was applied to an OLED device. Most of the OLED with the RIP–PVK film performed better compared to the reference OLEDs. The luminance graphs indicated the existence of a proper molecular weight leading to the optimum structural conformity which was matched well to the modified OLED structure, showing a linear relationship with the reaction time in the turn-on threshold. This result implies that one can control the proper molecular weight of a polymer and thus the electrical properties of an OLED device via the RIP method.     

Characterization of PI:PCBM organic nonvolatile resistive memory devices under thermal stress

In this study, we fabricated nonvolatile organic memory devices using a mixture of polyimide (PI) and 6-phenyl-C61 butyric acid methyl ester (PCBM) (denoted as PI:PCBM) as an active memory material with Al/PI:PCBM/Al structure. Upon increasing the temperature from room temperature to 470 K, we demonstrated the good nonvolatile memory properties of our devices in terms of the distribution of ON and OFF state currents, the threshold voltage from OFF state to ON state transition, the retention, and the endurance. Our organic memory devices exhibited an excellent ON/OFF ratio (I_ON/I_OFF > 10³) through more than 200 ON/OFF switching cycles and maintained ON/OFF states for longer than 10⁴ s without showing any serious degradation under measurement temperatures up to 470 K. We also confirmed the structural robustness under thermal stress through transmission electron microscopy cross-sectional images of the active layer after a retention test at 470 K for 10⁴ s. This study demonstrates that the operation of PI:PCBM organic memory devices could be controlled at high temperatures and that the structure of our memory devices was maintained during thermal stress. These results may enable the use of nonvolatile organic memory devices in high temperature environments.     

Platinum-induced hysteresis and nonvolatile memory properties in MOS systems (PLATMOS)

The effect of diffused platinum on MOS structures has been studied using high-frequency capacitance-voltage techniques. The materials used were and oriented p-type silicon substrates of 3-5-Ω.cm resistivity. All the platinum diffusions were performed at 1000°C in a dry nitrogen ambient for various times between 10 and 300 min. Experimental results are presented which show that platinum diffusion produces hysteresis effects in the MOS system which have not previously been observed. The hysteresis is found to be very strongly dependent on diffusion time and crystal orientation, being much more pronounced in wafers than . All the experimental observations point to this phenomenon being associated with some bias-dependent charge storage at the oxide-silicon interface or mobile platinum ions in the oxide. The precise nature of the charge-storage mechanism is not completely understood; however, the platinum-induced hysteresis raises the possibility of being used as a memory element due to its nonvolatile property.     

Nonvolatile memory and opto-electrical characteristics of organic memory devices with zinc oxide nanoparticles embedded in the tris(8-hydroxyquinolinato)aluminum light-emitting layer

The nonvolatile organic memory devices based on the tris(8-hydroxyquinolinato)aluminum (Alq₃) emitting layer embedded with zinc oxide nanoparticles (ZnO-NPs) are reported. The devices have a typical tri-layer structure consisting of the Alq₃/ZnO-NPs/Alq₃ layers interposed between indium tin oxide (ITO) and aluminum (Al) electrodes. An external bias is used to program the ON and OFF states of the device that are separated by a four-orders-of-magnitude difference in conductivity. No significant degradation of the device is observed in either the ON or OFF state after continuous stress (∼10⁵ s) and multicycle (∼10³ cycles) testings. These nanoparticles behave as the charge trapping units, which enable the nonvolatile electrical bistability when biased to a sufficiently high voltage. Impedance spectroscopy, capacitance–voltage (C–V) and current–voltage (I–V) analysis are used to verify the possible physical mechanism of the switching operation. Moreover, it is found that the location of the ZnO-NPs could affect the memory and opto-electrical characteristics of the devices, such as the ON/OFF ratio, threshold voltage and turn-on voltage, which can be attributed to the influence of the ZnO-NPs and diffused Al atoms in the bulk of the Alq₃ layer.     

Application of quantum dot gate nonvolatile memory (QDNVM) in image segmentation

This paper presents the application of quantum dot gate nonvolatile memory (QDNVM) in image processing application. The charge accumulation in the gate region varies the threshold voltage of QDNVM, which can be used as a reference voltage source in a comparator circuit. A simplified comparator circuit can be implemented using the QDNVM. In this work, the use of QDNVM-based comparators in image processing specially image segmentation is demonstrated, which can be efficient in future image processing application.     

Improvement of photoelectrochemical and optical characteristics of MEH-PPV using titanium dioxide nanoparticles

The use of bulk heterojunctions can increase the efficiency of exciton dissociation in polymer-based photovoltaics. We prepared and characterized bulk heterojunctions of poly[2-methoxy-5-(2′-ethylhexyloxy)-p-phenylenevinylene] (MEH-PPV) and titanium dioxide nanoparticles deposited by spin coating on indium tin oxide substrates. The surface morphology of the MEH-PPV+TiO₂ composite films revealed that addition of TiO₂ nanoparticles increased the film roughness. The effect of TiO₂ nanoparticles on the photoelectrochemical and optical characteristics of MEH-PPV polymer heterojunctions was studied. Addition of TiO₂ nanoparticles improved the absorbance of MEH-PPV composite films. Moreover, the photocurrent of the composite devices increased with the TiO₂ nanoparticle concentration. These observations provide an insight into new approaches to improve the light collection efficiency in photoconductive polymers.     

Using different work function nanocrystal materials to improve the retention characteristics of nonvolatile memory devices

Recently, nanocrystal nonvolatile memory (NVM) devices have attracted great research interest. Taking into account the effect of work function to account for the better retention characteristics for nanocrystals with larger work function, utilizing different work functions Au, W and Si as floating gates is proposed and comparatively studied in this paper. It was found that Au nanocrystals have better retention characteristic than W and Si. The good retention characteristic of the Au nanocrystal device is due to the larger work function and it is difficult for electrons captured by Au nanocrystal to escape from them. So, the retention characteristic of the device can be improved by using larger work function nanocrystal materials.     

New results on electron injection, hole injection, and trapping in MONOS nonvolatile memory devices

Charge injection and trapping in silicon nitride layers are studied with the three-terminal metal-oxide-nitride-oxide-semiconductor (MONOS) gated-diode structure. A new experimental technique based on the linear voltage ramp is developed which measures electron and hole currents separately in the semiconductor during the actual charge injection (nonsteady-state measurement as opposed to the steady-state method) across the tunneling oxide. In addition, the technique measures the flat-band voltage shift and minimizes the back tunneling of the injected charge (a problem with the pulse measurement). The blocking oxide between the gate electrode and the nitride layer prevents any injection from the gate electrode. The main conclusion from these studies is that the semiconductor injects electrons and holes into the nitride layer for positive and negative polarities of the gate bias, respectively. This result is in sharp contrast with the existing interpretations based on a single-carrier type. It is speculated that the recombination of electrons and holes takes place in the nitride layer via an "amphoteric" trap. At small levels of charge injection, centroids of the trapped charge (measured from the tunneling oxide-nitride interface) for both electron and hole injection conditions are found to be located at 75-80 Å at room temperature and 15-20 Å at 100 K.     

Impact of programming mechanisms on the performance and reliability of nonvolatile memory devices based on Si nanocrystals

A nonvolatile memory based on silicon nanocrystals (nc-Si) synthesized with very-low-energy Si/sup +/ implantation is fabricated, and the memory performance under the programming/erasing of either Fowler-Nordheim (FN)/FN or channel hot electron (CHE)/FN at both room temperature and 85/spl deg/C is investigated. The CHE programming has a larger memory window, a better endurance, and a longer retention time as compared to FN programming. In addition, the CHE programming yields less stress-induced leakage current than FN programming, suggesting that it produces less damage to the gate oxide and the oxide/Si interface. Detailed discussions on the impact of the programming mechanisms are presented.     

Characterization of TiOxNy nanoparticles embedded in HfOxNy as charge trapping nodes for nonvolatile memory device applications

Silicon-oxide–nitride-oxide–silicon devices with nanoparticles (NPs) as charge trapping nodes (CTNs) are important to provide enhanced performance for nonvolatile memory devices. To study these topics, the TiO_xN_y metal oxide NPs embedded in the HfO_xN_y high-k dielectric as CTNs of the nonvolatile memory devices were investigated via the thermal synthesis using Ti thin-film oxidized in the mixed O₂/N₂ ambient. Well-isolated TiO_xN_y NPs with a diameter of 5–20 nm, a surface density of ～3 × 10¹¹ cm^?2, and a charge trap density of around 2.33 × 10¹² cm^?2 were demonstrated. The writing characteristic measurements illustrate that the memory effect is mainly due to the hole trapping.     

Characterization of various alloying metal oxide nanoparticles embedded in HfOxNy as charge trapping nodes in nonvolatile memory devices

This work compares Co_xMo_yO, Co_xFe_yO and Fe_xMo_yO alloying metal oxide nanoparticles (AMONs) that were individually embedded in HfO_xN_y high-k dielectric as charge trapping nodes. They were formed by chemical vapor deposition using Co/Mo, Co/Fe and Fe/Mo acetate, respectively, calcined and reduced in Ar/NH₃ ambient. The effects of various pre-treatments on Co_xMo_yO, Co_xFe_yO and Fe_xMo_yO AMONs preparation were investigated. The results indicate that the larger charge trap density, larger memory window and better programming characteristics of Co_xMo_yO AMONs are attributable to their higher surface density and smaller diameter. The average collected charge in each Co_xMo_yO AMON is the smallest among three AMONs, revealing that a local leakage path is associated with the least charge loss. The main mechanism that governs the programming characteristics involves the trapping of holes.