Pentacene bottom-contact thin film transistors with solution-processed BZT gate dielectrics

The solution-processed high-k barium zirconate titanate (BZT) as gate dielectrics for bottom-gate pentacene-based organic thin film transistor (OTFT) applications is presented. To reduce the transistor threshold voltage, higher work function metals (Au) is used as the gate electrodes. The threshold voltage is efficiently decreased from −3.6 to −2.15 V as compared to that of Al. In addition, the UV/ozone was employed to treat the Au (source/drain) surface to improve the poor crystalline of pentacene grown on Au. Moreover, the surface morphologies and orientations of pentacene films were analyzed through atomic force microscopy (AFM) and X-ray diffraction. As the results, the stack of pentacene molecules from disorder state changed to vertical growth on the Au surface. Finally, the electrical properties of pentacene-based thin film transistors exhibit high field-effect mobility of 4.5 cm²/V·s, low subthreshold swing of 260 mV/decade, high on/off ratio of 1.4 × 10⁵ and low operation voltage of −5 V. These results are better than the reported data using bottom contact pentacene OTFTs.     

Polycrystalline silicon thin film transistors fabricated at reducedthermal budgets by utilizing fluorinated gate oxidation

Polycrystalline silicon thin film transistors have been fabricated at reduced gate oxidation thermal budgets by utilizing NF₃-enhanced dry oxidation. Good performance TFTs with effective electron mobility values as high as 38 cm²/V.sec, threshold voltage values near zero, ON/OFF current ratios of up to 5×10⁷ and subthreshold slopes of 0.3 V/dec have been fabricated at an oxidation temperature of 800°C. Stable devices at an electrical stressing field of 3 MV/cm were demonstrated. Thermal gate oxide TFTs have also been fabricated at a maximum temperature of 650°C. The effect of hydrogen plasma passivation was found to depend on process conditions and was correlated with the amount of fluorine in the area near the Si-SiO₂ interface. Passivation at low power was always beneficial. Passivation at high power was highly beneficial for a limited amount of interfacial fluorine, but less beneficial or even detrimental when a large fluorine amount in the near interface area was present     

Magnetron-sputtered high performance Y-doped ZnO thin film transistors fabricated at room temperature

In this report, sputtered-grown undoped ZnO and Y-doped ZnO (ZnO:Y) thin film transistors (TFTs) are presented. Both undoped ZnO and ZnO:Y thin films exhibited highly preferred c-axis oriented (002) diffraction peaks. The ZnO:Y thin film crystallinity was improved with an increase of (002) peak intensity and grain size. The electrical properties of ZnO:Y TFTs were significantly enhanced relative to undoped ZnO TFTs. ZnO:Y TFTs exhibited excellent performance with high mobility of 38.79 cm² V⁻¹ s⁻¹, small subthreshold swing of 0.15 V/decade, and high I_on/I_off current ratio of the order of 8.17 × 10⁷. The O_1s X-ray photoelectron spectra (XPS) showed oxygen vacancy-related defects present in the ZnO:Y TFTs, which contributed to enhancing the mobility of the TFTs.     

A self-alignment process for amorphous silicon thin film transistors

A new method of fabricating amorphous Si thin film transistors (a-Si TFT's) has been developed. This method uses the self-alignment process, which also includes the successive deposition of gate insulator and active amorphous Si layers in one-pumpdown time in an RF glow discharge apparatus. This method greatly simplifies the fabrication process and results in stable device performance. The practicability of this method was confirmed by experimentally fabricated devices.     

Zapping thin film transistors

It was expected that hydrogenated amorphous silicon thin film transistors (α-Si:H TFTs) behave similarly to crystalline silicon transistors under electrostatic discharge (ESD) stress. It will be disproved in this paper. This knowledge is necessary in the design of the transistors used in a ESD protection circuit. The goal of this paper was to identify and to model failure under ESD zap. The drain of grounded gate TFTs has been stressed applying repeated square voltage pulses of different duration (100 ns to 10 s). The evolution and the mechanisms of the pre-breakdown degradation will be presented and discussed. Finally, the temperature distribution across an α-Si:H TFT under applied stress will be simulated by means of coupled electro-thermal simulations.     

IGZO thin film transistors with Al2O3 gate insulators fabricated at different temperatures

Thin film transistors (TFTs) with bottom gate and staggered electrodes using atomic layer deposited Al₂O₃ as gate insulator and radio frequency sputtered In–Ga–Zn Oxide (IGZO) as channel layer are fabricated in this work. The performances of IGZO TFTs with different deposition temperature of Al₂O₃ are investigated and compared. The experiment results show that the Al₂O₃ deposition temperature play an important role in the field effect mobility, I_on/I_off ratio, sub-threshold swing and bias stability of the devices. The TFT with a 250 °C Al₂O₃ gate insulator shows the best performance; specifically, field effect mobility of 6.3 cm²/Vs, threshold voltage of 5.1 V, I_on/I_off ratio of 4×10⁷, and sub-threshold swing of 0.56 V/dec. The 250 °C Al₂O₃ insulator based device also shows a substantially smaller threshold voltage shift of 1.5 V after a 10 V gate voltage is stressed for 1 h, while the value for the 200, 300 and 350 °C Al₂O₃ insulator based devices are 2.3, 2.6, and 1.64 V, respectively.     

薄膜沉积法制作菲涅耳透镜

衍射光学元件在国防、生产及科研等领域起着为越重要的作用。衍射光学元件的制作技术主要包括激光或电子束直写、反应离子刻蚀、离子束铣及薄膜沉积。薄膜沉积法具有精确控制台阶高度及台阶表面较光滑的优点。使用薄膜沉积法制作１６阶菲涅耳透镜,用它代替常规的光学透镜可实现系统的轻量化、小型化、增加系统设计的自由度,屯菲涅耳透镜的衍射效率并分析产生误差的原因。     

Characteristics of thin film transistors fabricated in polysilicon films deposited by plasma enhanced chemical vapor deposition

Thin-film transistors (TFTs) fabricated in polysilicon films deposited by plasma enhanced chemical vapor deposition (PECVD) were characterized. The transistors were fabricated using a low temperature process (i.e., <- 700° C). The characteristics of the devices were found to improve as the deposition temperature of the polysilicon film increased. The best characteristics (μ _FE of 15 cm²/V _s andV _TH of 2.2V) were measured in the devices fabricated in the film deposited at 700° C. The devices fabricated in the PECVD polysilicon films were compared to those fabricated in polysilicon films deposited by thermal CVD in the same reactor in order to decouple the effect of the plasma. A coplanar electrode structure TFT with adequate characteristics (μ _FE of 8 cm²/V _s) was also demonstrated in the PECVD polysilicon films.     

一种廉价电极的并五苯场效应晶体管

采用底栅顶接触结构,研究制备了以并五苯为有源层、聚甲基丙烯酸甲酯(PMMA)为绝缘层的全有机场效应晶体管(OFET),其中绝缘层采用溶液旋涂法制备,电极采用MoO3/Al双层电极。与传统采用单一Au为电极的器件相比,采用双层电极的器件性能大幅提高,经测试,器件的迁移率达到了0.133cm2/Vs,开关电流比可以达到2.61×105。对采用MoO3修饰层提高性能的作用机理进行了详细论证。     

一種製作互補式金氧半複晶矽薄膜電晶體之製程簡化技術

一種製作互補式金氧半複晶矽薄膜電晶體之製程簡化技術被提出, 其藉由大角度離子佈植摻雜物穿透閘極間隙壁. 藉由此技術方法,可使用同一光罩而同時形成淡摻雜區域於閘極間隙壁氧化層下方且形成高摻雜區域,其可於互補式金氧半複晶矽薄膜電晶體製作時簡化製程步驟.更進一步地,藉由此技術,與傳統的單一高濃度摻雜源汲極技術相較,此方法可得到更好的N型及P型薄膜電晶體特性,且無需增加光罩製程.     

A process simplification scheme for fabricating CMOS polycrystalline-Si thin film transistors

A process simplification scheme for fabricating CMOS poly-Si thin-film transistors (TFTs) has been pro-posed, which employs large-angle-tilt-implantation of dopant through a gate sidewall spacer (LATITS). By this LATITS scheme, a lightly doped drain region under the oxide spacer is formed by low-dose tilt implantation of phosphorus (orboron) dopant through the spacer, and then the n+-source/drain (n+-S/D) (or p+-S/D) region is formed via using the same photo-mask layer during CMOS integration. For both n-TFT and p-TFT devices, as compared to the sample with conventional single n+-S/D (or p+-S/D) structure, the LATITS scheme can cause an obviously smaller leakage current, due to more gradual dopant distribution and thus smaller electric field. In addition, the resultant on-state currents only show slight degradation for the LATITS scheme, As a result, by the LATITS scheme, CMOS poly-Si TFT devices with an on/off current ratio well above 8 orders may be achieved without needing extra photo-mask layers during CMOS integration.     

Organic thin film transistors with double insulator layers

We have investigated a double-layer structured gate dielectric for the organic thin films transistor (OTFT) with the purpose of improving the performance of the SiO₂ gate insulator. A 50 nm PMMA layer was coated on top of the SiO₂ gate insulator as organic insulator layer. The results demonstrated that using inorganic/organic compound insulator as the gate dielectric layers is an effective method to fabricate OTFTs with improved electric characteristics and decreased leakage current. Electrical parameters such as carrier mobility and on/off ratio by field effect measurement have been calculated. OTFT based on highly doped Si substrate with a field-effect mobility of 0.004 cm²/V s and on/off ratio of 10⁴ have been obtained.     

Organic thin film transistors with PMMA modified insulator

A double insulation layer structure organic thin films transistor (OTFT) was investigated for improving the performance of the SiO2 gate insulator. A 50 nm PMMA layer was coated on top of the SiO2 gate insulator as the organic insulator layer. The results demonstrated that using inorganic/organic compound insulator as the gate dielectric layer is an effective method to fabricate OTFTs with improved electric characteristics and decreased leakage current. Electrical parameters of carrier mobility and on/off ratio were calculated. OTFT based on Si substrate with a field-effect mobility of 4.0 × 10-3cm2/Vs and on/off ratio of 104 was obtained.     

具有双绝缘层的有机薄膜晶体管

为了提高SiO2单绝缘层器件的性能,在SiO2绝缘层的表面用旋涂的方法制备一层大约50 nm厚度的PMMA.实验结果表明用无机/有机双绝缘层可以有效的提高器件的性能同时降低器件的漏电流.计算出了载流子迁移率和开关电流比,基于PMMA/SiO2双绝缘层器件的载流子迁移率和开关电流比分别是4.0×10-3cm2/Vs和104.     

Self-patterning of high-performance thin film transistors

We have developed a technique for the preparation of thin film transistors (TFTs) through the self-patterning of various organic and inorganic materials via solution processing using a wide range of solvents. To obtain selectively self-patterned layers, we treated the oxide dielectric with two-phase patterned self-assembled monolayers of hexamethyldisilazane (HMDS) and octyltrichlorosilane. The conducting polymer poly(3,4-ethylenedioxythiophene) doped with poly(styrene sulfonic acid) in water and the dielectric polymer poly(vinyl phenol) in propylene glycol methyl ether acetate were both selectively deposited and patterned on the HMDS regions with high-quality feature shapes. When source and drain electrodes were patterned on the bottom-gate oxide wafer, we also self-patterned organic and inorganic semiconductors around the channel (HMDS) regions. These TFT devices exhibited moderate to good electronic characteristics. This method has great potential for the economical full solution processing of large-area electronic devices. The selectivity in the patterning phenomena can be understood in terms of surface energy interactions.     

Gate-planarized organic polymer thin film transistors

We report in this paper the fabrication and characterization of a new gate-planarized organic polymer thin-film transistor (GP OP-TFT). We describe in detail the effects of the measurement procedure on the GP OP-TFT electrical characteristics and extracted parameters and show that it is extremely critical to carefully control the electrical measurement conditions to obtain accurate and meaningful results, before any material optimization is undertaken. We also describe the importance of normalization of electrical characteristics and extracted parameters for a proper comparison of different devices. Finally, we report and analyze the gate voltage and channel length dependence of the TFT field-effect mobility.     

Silicon permeable base transistors fabricated by selective epitaxial growth

A new type of silicon PBT uses lateral selective low-pressure vapour-phase epitaxy to grow ridges with mushroom-like cross-sections leading to self-aligned gate and drain electrodes. Advantages are the lack of any etching damage encountered with etched-groove PBTs and high-temperature process compatibility. First experimental devices with bar widths of 1 mu m exhibited transconductances of 7 mS/mm.<>     

Radiation-hardened silicon-on-insulator junction field-effect transistors fabricated by a self-aligned process

A self-aligned process has been developed for fabricating JFET's in zone-melting-recrystallized (ZMR) Si films on SiO2-coated Si substrates. This process has been used to fabricate n-JFET's exhibiting transconductance values up to 63 mS/mm. For 228 devices within an area of about 4 × 4 cm², the mean threshold voltage is 578 mV and the standard deviation is 22 mV. With a -15-V bias applied to the Si substrate during irradiation and device operation, the devices show low threshold voltage shift (< -75 mV) and small transconductance degradation (∼30 percent) for exposure to total-dose radiation of 10⁸rad(Si).