C波段频率合成器的设计

在分析常规数字锁相环路基础上,利用数字锁相混频环电路实现了C波段快速低相噪宽带频率合成器的设计,并进行了理论分析。给出的研制模块的指标测试结果,验证了理论分析的正确性。     

A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications

A CMOS phase-locked loop (PLL) which synthesizes frequencies between 6.336 and 8.976 GHz in steps of 528 MHz and settles in approximately 150 ns is presented. The proposed PLL can be employed as a building block for a frequency synthesizer which generates a seven-band hopping carrier for multiband orthogonal frequency division multiplexing (MB-OFDM) ultrawideband (UWB) radio. To achieve fast loop settling, integer-N architecture that operates with 528-MHz reference frequency is implemented and a wideband active-loop filter is integrated. An improved phase-frequency detector (PFD) is proposed for faster loop settling. To reduce reference sidebands, a feedback circuit using replica bias is implemented in the charge pump. I/Q carriers are generated by two cross-coupled LC VCOs. The output current of the charge pump is controlled to compensate for the VCO gain nonlinearity and a programmable frequency divider (12/spl les/N/spl les/17) that reliably operates at 9 GHz is designed. Fabricated in 0.18-/spl mu/m CMOS technology, the PLL consumes 32 mA from a 1.8-V supply and achieves phase noise of -109.6dBc/Hz at 1-MHz offset and spurs of -52 dBc.     

一种具有相位噪声跟踪补偿的全数字锁相环频率合成器

为了实现频率合成器中的相位噪声跟踪补偿和降低全数字锁相环的复杂性,本文提出了一种新的基于全数字锁相环的频率合成器。它采用了一种低复杂度的数字鉴频鉴相器和非线性相位/频率判决电路以及数控振荡器,从而显著降低了硬件复杂性。同时结构中采用的非线性相位和频率判决电路能够很好地实现噪声跟踪和快速的相位/频率捕获,数控振荡器能够获得高的频率分辨率(大约6kHz)和大的线性频率调谐范围。通过采用90nm CMOS工艺制造的ADPLL实验结果表明,本文所提出的基于全数字锁相环的频率合成器能够实现从100kHz到6MHz的可控环路带宽和相当好的带内相位噪声跟踪性能。     

基于自适应锁相环的高动态GPS信号载波跟踪算法

提出了一种基于四维卡尔曼滤波的自适应锁相环算法,并将该算法用于高动态GPS信号的载波跟踪.详细推导了卡尔曼滤波与数字锁相环之间的等效性,并给出了相应的环路更新步骤.仿真结果表明,该算法相对于采用固定增益数字锁相环的算法明显地降低了载波跟踪过程的均方根频率误差,提高了接收机的测速精度.     

太阳能直放站锁相环系统设计与应用

由于移动通信技术的发展,通信频率的变化范围越来越宽,为了解决太阳能直放站锁相环系统在满足输出频率和相位稳定的同时,兼顾直放站太阳能电源对整个系统实现低功耗供电的问题,文中研究了锁相环原理,分析了GSM太阳能直放站锁相环系统,采用高度集成的锁相环频率合成器和高转换效率的电源,并进行了其具体的电路设计与应用,同时进行了锁相环系统测试,满足直放站频率合成输出的性能要求。     

A fast switching PLL frequency synthesizer with an on-chip passive discrete-time loop filter in 0.25-/spl mu/m CMOS

A phase-locked loop (PLL) frequency synthesizer with an on-chip passive discrete-time loop filter is reported in this paper. The closed loop is robust stable, and a fast switching speed is achieved by creating a stabilization zero in the discrete-time domain. The circuit implementations and system-level analysis results of the proposed architecture are presented. Techniques and design considerations are presented to overcome several potential problems of the proposed architecture, such as finite lock-in range, translation of voltage-controlled oscillator noise into in-band phase noise, and spur degradation due to clock feedthrough of the sampling switch. A 2.4 GHz prototype frequency synthesizer for Bluetooth applications was developed in a 0.25-/spl mu/m CMOS process. The measured results agree with theoretical predictions and demonstrate its high performance.     

A 1.5-V 900-MHz monolithic CMOS fast-switching frequencysynthesizer for wireless applications

A new architecture for phase-locked loop frequency synthesizers which employs a switchable-capacitor array to tune the output frequency and a dual-path loop filter operating in the capacitance domain is proposed. It provides many advantages, including simplified analog circuitry, low supply voltage, low power consumption, small chip area, fast frequency switching, and high immunity of substrate noise. Implemented in a standard 0.5-μm CMOS process, a fully integrated fractional-N synthesizer prototype with a third-order sigma-delta modulator is designed for 1.5 V and consumes 30 mW. The total chip area is, 0.9 × 1.1 mm². The settling time is less than 100 μs and the phase noise is -118 dBc/Hz at 600-kHz offset     

基于小数分频的锁相环设计

锁相环电路广泛应用于现阶段集成电路芯片中,由于需要较高的输出频率解析度,小数分频的锁相环得到了越来越多的关注。但是小数分频调制器会引入较大的噪声,因此如何降低系统噪声、提供高性能相位噪声的锁相环成为现阶段研究的重要课题。文章给出了基于小数分频技术的锁相环设计与噪声分析,分析了各个主要模块的设计要求与优化方法。芯片在SMIC流片制造,采用了0.13μm逻辑工艺,从样片的测试结果来看,Sigma-Delta模块的噪声得到了较好的抑制,满足了预先的设计要求。     

光学锁相环的研究进展

光学锁相环（OPLL）根据其锁定的两束激光间是否存在频差可分为零差光学锁相环和外差光学锁相环。主要介绍了外差光学锁相环的研究进展,它是一种通过鉴频鉴相方式使激光间的频率差保持相对稳定的偏频锁定方法。相较于其他激光偏频锁定方法,光学锁相环具有结构简单、伺服频率带宽大、频率偏置范围宽、锁定准确度高等优势,在原子相干、冷原子系统、相干功率合成以及外差干涉测量等领域都得到了越来越广泛的应用。首先介绍了激光偏频锁定的主要方法及光学锁相环的特点;其次介绍了光学锁相环的基本模型,分析了光学锁相环的误差反馈过程,并按照光学锁相环实现方法的不同详细介绍了其采用的关键技术和研究进展,对近年来光学锁相环在不同领域的应用进展做了简要介绍;最后对该方法的发展路线进行了总结和展望。     

并联谐振型逆变器控制技术的研究

在分析了锁相环的控制原理以及目前使用的锁相定角控制方法的基础上,提出了一种新的锁相控制方法,并将之应用于感应加热电源装置中,实现定角控制。以MATLAB／Simulink为工具建立了以IGBT为开关器件的并联谐振型逆变器仿真模型,并对仿真结果进行了分析。仿真结果验证了这种锁相控制方法的正确性和有效性。     

锁相环在光伏发电系统中的应用

锁相环是光伏发电系统并网的重要环节。锁相环的主要作用是输入与输出信号的频率相等时,输入、输出电压保持固定的相位差值,即输出与输入电压的相位被锁定。文中从锁相环的概念入手,介绍了锁相环3部分的工作过程。在结合锁相芯片CD4046实现对采集电压信号频率及相位数据的锁定,并通过锁相和失锁的信号输入逆变器。当光伏发电系统中逆变器输出的电压相位、频率和幅值严重偏离正常并网值时,可报警输出开关量值,发出报警并通过隔离开关使电网分离。     

数字锁相环相位噪声影响因素分析

数字锁相环作为广泛应用的一种频率合成技术,相位噪声是其关键的技术指标。介绍数字锁相环的关键组成部分,从数字锁相环的相位噪声分析模型出发,阐述各组成部分对相位噪声产生的影响,并分析各部分关键指标的选型依据,然后利用仿真软件搭建仿真模型验证分析结果。为数字锁相环的设计,提高相位噪声性能提供了参考依据。     

Ring voltage controlled oscillator for high-speed PLL systems

A circuit of a ring voltage controlled oscillator (VCO), which is to be used in high-speed phase-locked loop (PLL) systems integrated into programmable logic integrated circuits, is proposed. The maximum operating frequency of a VCO in 180 nm CMOS is shown by simulation to be able to reach 2 GHz in all operating conditions with the phase noise being ?99 dB/Hz and detuning frequency being 1 MHz.     

A fully integrated CMOS DCS-1800 frequency synthesizer

A prototype frequency synthesizer for the DCS-1800 system has been integrated in a standard 0.4 μm CMOS process without any external components. A completely monolithic design has been made feasible by using an optimized hollow-coil inductor low-phase-noise voltage-controlled oscillator (VCO). The frequency divider is an eight-modulus phase-switching prescaler that achieves the same speed as asynchronous dividers. The die area was minimized by using a dual-path active loop filter. An indirect linearization technique was implemented for the VCO gain. The resulting architecture is a fourth-order, type-2 charge-pump phase-locked loop. The measured settling time is 300 μs, and the phase noise is up to -123 dBc/Hz at 600 kHz and -138 dBc/Hz at 3 MHz offset     

数字锁相技术的研究与实现

锁相技术在调制和解调、频率合成电路等很多领域应用极其广泛。文中提出一种高动态数字锁相环的设计方法,分析了锁相环的基本原理,采用EDA技术,结合FPGA芯片特点,运用硬件描述语言对数字锁相环进行了优化设计,并且对设计进行仿真,给出了相应的仿真结果。     

自适应锁相环的设计与仿真

在三相电压不平衡时,负序分量会在Park变换后产生一个2倍基频的波动,进而影响对基频分量相位的提取。针对一般的锁相环在电网三相不平衡时无法准确锁定电网的相位,本文提出一种基于陷波器的自适应锁相环,利用自适应陷波器(ANF)能够输出两个相互正交分量的特点,生成两个能抵消dq坐标系的负序分量,这样就实现了基波的正序负序分离。在Matlab/Simulink中建立仿真模型进行验证,结果表明了文中所提的方法在电网不平衡时可以准确地锁定电网的相位。     

一种改善频率合成器相位噪声的方法

在现代电子技术中,数字式频率合成器在通信、雷达等系统中得到了广泛的应用,其相位噪声直接影响到系统的整体性能。提出了利用变频锁相方法改善微波波段频率合成器的相位噪声,并进行了频域分析,给出了相应的环路滤波器的设计。最后的实验结果给出了变频锁相与直接锁相的频率合成器相位噪声比较,可以看出采用变频锁相方式的频率合成器的相位噪声有了很大的改善。     

一种超宽带超低相位噪声频率综合器

为了解决直接频率合成方法频带拓展困难和锁相频率合成方法相位噪声附加恶化严重的问题,设计了一种联合直接模拟频率合成和锁相频率合成的混频锁相频率综合器. 该频率综合器采用梳谱发生器激励超低相位噪声的偏移信号后,再将该信号插入锁相环进行环内混频,降低鉴相器的倍频次数进而优化输出信号的相位噪声,同时解决了超宽带混频锁相环的错锁问题. 该文设计的频率覆盖范围为12~24 GHz、步进为100 MHz的超宽带频率综合器实验测试表明:频率综合器在低频段12 GHz处相位噪声优于?116 dBc/Hz@1 kHz,在高频段24 GHz处相位噪声优于?109 dBc/Hz@1 kHz,相位噪声指标与直接模拟频率合成方法相当,均优于传统锁相方法20 dB以上. 本文混合频率合成方法具有超宽带和超低相位噪声的优点,可以用于高性能的电子设备和系统.     

80 Gbit/s optical clock recovery with automatic lock acquisition using electrical phase-locked loop

A novel electrical phase-locked loop architecture for optical clock recovery using an input mixer mixing down to the intermediate frequency is presented. Phase detectors of the phase-locked loop operate on an intermediate frequency. The architecture allows the use of the quadrature phase detection enabling automatic lock acquisition.     

CMOS毫米波低相噪级联双锁相环频率综合器设计北大核心

采用65 nm CMOS工艺，设计了一种低相噪级联双锁相环毫米波频率综合器。该频率综合器采用两级锁相环级联的结构，减轻了单级毫米波频率综合器带内和带外相位噪声受带宽的影响。时间数字转换器采用游标卡尺型结构，改善了PVT变化下时间数字转换器的量化线性度。数字环路滤波器采用自动环路增益控制技术来自适应调节环路带宽，以提高频率综合器的性能。振荡器采用噪声循环技术，减小了注入到谐振腔的噪声，进而改善了振荡器的相位噪声。后仿真结果表明，在1.2 V电源电压下，该频率综合器可输出的频率范围为22～26 GHz,在输出频率为24 GHz时，相位噪声为-104.8 dBc/Hz@1 MHz,功耗为46.8 mW。