Part I--Digital techniques for communication signal processing

Digital processing of communication signals is now a practical alternative to analog processing. This application of a well-understood theory as a viable alternative is largely due to the availability of low cost arithmetic and storage LSI circuits; the availability of low cost A/D and D/A circuits; the commonplace occurrence of digital signals due to the ever increasing use of digital transmission and routing; and the significant advantages offered by the flexibility of the digital approach. This paper is an attempt to present in an introductory manner the what, why, where, and how of digital signal processing.     

Multirate analog-digital systems for signal processing andconversion

Systems containing both analog and digital functions have been investigated with the purpose of realizing mixed-signal integrated circuits with higher levels of functionality and integration. In most cases, such mixed-signal systems are inherently multirate because of the different sampling rates employed at various stages of the system. The multirate concepts have been used for traditional applications, such as subband coding and narrowband filter design. Some unconventional applications of multirate signal processing are also emerging, both for converting between analog samples and digital words, and for realizing processing functions in an easier and more economical way than would be possible using purely digital or analog techniques. This paper reviews fundamental multirate concepts, discusses some developments in this area of integrated multirate analog-digital systems, and outlines some possible future directions for research and application     

Multirate signal processing on finite fields

The paper addresses the problem of multirate signal processing over arbitrary fields. Studies of multirate systems and filter banks have proceeded in parallel, and a wealth of results are available in literature. The authors concentrate their attention on cyclic systems. These structures are ideally suited to generalising the concepts to finite fields. The perfect reconstruction property for quadrature mirror filter banks is obtained. It is shown how the cyclic wavelet transform (CWT) can be derived from such systems; the relationships between cyclic filter banks and CWTs are explored in detail. The results obtained are potentially very well suited for speech and image encoding, as well as for fast algorithms in signal processing     

GaAs ICs for high-speed signal processing

A complete family of small-scale integration (SSI) and middle-scale integration (MSI) analog and digital GaAs ICs for real-time signal processing is reported. These circuits have been used on several microstrip PC board applications with clock frequencies ranging from 500 MHz to 1 GHz. Detailed circuit performances and future trends are presented and discussed     

GaAs switched-capacitor circuits for high-speed signal processing

Switched-capacitor building blocks are presented which are suitable for implementation in GaAs MESFET technology. They include gain stages, operational amplifiers, and transmission gates. Switched-capacitor design techniques are discussed that minimize filter sensitivity to GaAs op-amp limitations. Experimental results are presented on a variety of GaAs switched-capacitor circuits, including a gain stage, a second-order bandpass filter, and a third-order low-pass filter. The circuits demonstrate sampling rates exceeding 100 MHz without significant loss of accuracy.     

Carry-save architectures for high-speed digital signal processing

Carry-save arithmetic, well known from multiplier architectures, can be used for the efficient CMOS implementation of a much wider variety of algorithms for high-speed digital signal processing than, only multiplication. Existing architectural strategies and circuit concepts for the realization of inner-product based and recursive algorithms are recalled. The two's complement overflow behavior of carry-save arithmetic is analyzed and efficient overflow correction schemes are given. Efficient approaches are presented for the carry-save, implementation of a saturation control. The concepts are extended and refined for the high-throughput implementation of decisiondirected algorithms such as division, modulo multiplication and CORDIC which have yet been avoided because of a lack of efficient concepts for implementation.It is shown, that the carry-save technique can be extended to a comprehensive method to implement high-speed DSP algorithms. Successfully fabricated commercial VLSI circuits emphasize the potential of this method.     

Monolithic GaAs photoreceiver for high-speed signal processing applications

High-speed planar monolithically integrated GaAs photoreceivers have been fabricated by selective ion implantation into SI GaAs substrates. Their fabrication is fully compatible with existing GaAs LSI process schedules. A receiver upper cutoff frequency of 1.5 GHz and sensitivity of 112 V/W have been measured. The application of these devices in short-haul high-bit-rate data communication systems has been demonstrated in a 560 Mbit prototype optical data link, using packaged and fibre-coupled devices.     

Complex residue number arithmetic for high-speed signal processing

Complex residue number arithmetic is developed for high-speed processing of complex waveforms. An important feature of complex residue arithmetic is that complex multiplication can be implemented by a real index calculus, thereby providing a highly efficient complex multiplication technique for processing digital complex waveforms in communication and radar systems.     

Acquisition time minimisation techniques for high-speed analoguesignal processing

Acquisition time minimisation techniques using a two-stage amplifier for high-speed analogue signal processing in mixed-mode circuits are presented. The proposed techniques reduce overshoots and undershoots of the amplifier by adjusting its transconductance and achieve high-speed performance with little modification to the conventional amplifier architecture. The measured signal-to-noise-and-distortion ratio of the prototype 12 bit CMOS ADC based on the proposed techniques is improved by >5 dB at a 50 MHz sampling clock     

A high-speed power detector MMIC for E-band communication

An E-band high speed power detector MMIC using 0.1 μm pHEMT technology has been designed, manufactured and experimentally characterized. By employing a 4-way quadrature structure for phase cancellation, the first, second and third harmonics can be suppressed and the ripple at the output is minimized. Compared to conventional topology with a low pass filter, a short response time and high speed performance of demodulation can be reached. Simulated results indicate that the detector is capable of demodulating an on-off keying signal at a data rate up to 5 Gbps. The fabricated chip occupies 1×1.5 mm²and the on-wafer measurement shows a return loss of less than -15 dB, responsivity better than 700 mV/mW and dynamic range of more than 25 dB over 70 to 90 GHz.     

A protocol structure for high-speed communication over broadbandISDN

Various possibilities for improving the performance of communications protocols and interfaces so that the slow-software-fast-transmission bottleneck can be alleviated are investigated. An architecture that is an alternative to the existing layered architectures is proposed. The novel feature of the proposed architecture is the reduction in the vertical layering; services that correspond to the definitions of layers four to six in the Open Systems Interconnection Reference Model are combined into a single, horizontally structured layer. This approach lends itself more naturally to parallel implementation. Moreover, the delay of a set of processes implemented in parallel is determined by the delay of the longest process, not by the sum of all the process delays, as is the case in a sequential implementation. In the same way, the total throughput need not be limited by the lowest-capacity process, but can be increased by concurrently performing the function on several devices     

Parallel bit-level pipelined VLSI designs for high-speed signal processing

This paper explores the potential of bit-level pipelined VLSI for high-speed signal processing. We discuss issues involved in designing such fully pipelined architectures. These include clock skew, clock distribution networks, buffering, timing simulation, area overhead due to pipelining, and testing. A total of six bit-level pipelined designs, including a multiplier, an FIR filter block, and a multichannel multiply-accumulate/add chip, have now been fabricated in CMOS technology. These chips have been tested both for functionality and speed. The results of these tests and the applications of these chips are presented and discussed.     

A high-speed digital filter LSI for video signal processing

A ninth-order symmetrical filter has been developed for use in two-dimensional (2-D) processing in TV video systems, especially in high-definition TV receivers. A 2-D filter that is composed of only two types of LSIs (one-dimensional (1-D) digital filter LSI and delay-line) is discussed. The architecture of the digital filter LSI and circuit techniques are presented to obtain high-speed operation, to save chip area, and to decrease power consumption. The order and the transfer function of the filter can be altered by means of the external terminals. The chip, achieved through 2-/spl mu/m CMOS technology, contains about 52000 transistors and occupies an area of 50 mm/SUP 2/. It operates at a high clock frequency of over 33 MHz, and dissipates only 600 mW of power.     

System identification techniques for adaptive signal processing

Many problems in adaptive filtering can be approached from the point of view of system identification. The close interconnection between these two disciplines is explored in some detail. This approach makes it possible to apply recursive parameter estimation algorithms to adaptive signal processing. Several examples are discussed including: adaptive line enhancement, generalized adaptive noise cancelling, adaptive deconvolution and adaptive TDOA estimation. It is shown how the recursive maximum likelihood algorithm can be used for both FIR and IIR filtering, and some preliminary results are presented. Several alternative algorithms are briefly discussed.This work was supported by the Office of Naval Research, Contract No. N00014-79-C-0743.     

One-dimensional signal processing techniques for airborne laserbathymetry

The application of one-dimensional signal processing techniques for the preprocessing of waveforms obtained in airborne laser bathymetry is investigated. Specifically, a special type of smoothing digital filter is used to remove noise in the waveforms while preserving the information content up to a desired degree. An algorithm, which incorporates a lowpass digital differentiator is then used to detect the bottom reflection. The optimal cutoff frequency of the differentiator is determined on the basis of the spectral content of the bottom reflection. After preprocessing, a waveform-decomposition technique recently described by the authors is used to separate the surface and bottom reflections for sea-depth estimation. In order to evaluate the effectiveness of the techniques developed, sea-depth estimates obtained are compared to corresponding estimates obtained by a local surveying company, and a high degree of agreement is observed between the two sets of results. When the resolution between the surface and bottom returns is low, the proposed techniques together with waveform decomposition offer a significant improvement in the sea-depth estimates     

Two-dimensional signal processing techniques for airborne laserbathymetry

The application of two-dimensional (2D) signal processing to data collected in airborne laser bathymetry is investigated. Specifically, a type of 2D filter for the suppression of impulsive noise in irregularly-spaced data based on order-statistics filtering is developed. An algorithm which incorporates this type of filter along with a sophisticated 2D interpolation technique is constructed to automate the filtering process. An adaptive 2D filtering technique that can be applied to raw bathymetric profiles to remove wideband noise is then discussed. The results obtained show that each type of filtering enhances the accuracy of bathymetric measurement quite significantly     

ASIC techniques for high-performance digital signal processing

We describe a high-level ASIC (application specific integrated circuit) synthesis system aimed at rapid and efficient realisation of integer arithmetic “engines” for signal processing bottleneck computations. Novel software features include bit-level scheduling which allocates numerical resources for computation, and a parameter synthesis system which maximises the use of this resource. Underlying synthesis is a generic digit-serial integer arithmetic processing architecture, with module generation capability across a wide parameter space for a useful set of primitive arithmetic operations. We outline the principal components of the tool, and briefly describe some application examples.