A 900-MHz fully integrated SOI power amplifier for single-chipwireless transceiver applications

This paper presents a silicon-on-insulator (SOI) fully integrated RF power amplifier for single-chip wireless transceiver applications. The integrated power amplifier (IPA) operates at 900 MHz, and is designed and fabricated using a 1.5-μm SOI LDMOS/CMOS/BJT technology. This technology is suitable for the complete integration of the front-end circuits with the baseband circuits for low-cost low-power high-volume production of single-chip transceivers. The IPA is a two-stage Class E power amplifier. It is fabricated along with the on-chip input and output matching networks. Thus, no external components are needed. At 900 MHz and with a 5-V supply, the power amplifier delivers 23-dBm output power to a 50-Ω load with 16-dB gain and 49% power-added efficiency     

A three-terminal SOI gated varactor for RF applications

This paper presents a new CMOS compatible SOI gated varactor for use in RF ICs. With its additional third terminal, the device offers an exceptional large tuning range and a good quality factor. The result of the MEDICI simulation of the structure of the varactor has been confirmed with measured data. A VCO circuit that can potentially exploit the three-terminal property is also reported     

A fully integrated feedback AGC loop for ZigBee (IEEE 802.15.4) RF transceiver applications

This work presents an efficient solution for automatic gain control (AGC) loop in ZigBee transceiver compatible to IEEE 802.15.4 standard. The design is based on a RF (Radio Frequency) and linear IF (Intermediate Frequency) chain where the signal amplification is done in the RF front-end blocks and analog VGAs (variable gain amplifiers). The gains of the RF block and VGA are digitally controlled by the DAGC (Digital AGC) block to ensure that the ADC (Analog-to-Digital Converter) operates inside its dynamic range. Feedback loop architecture is employed for the advantage of high linearity due to its inherent characteristic. The whole AGC loop has been integrated in the ZigBee transceiver which was fabricated in a 0.18 μm CMOS technology. The AGC loop achieves a dynamic range of about 95 dB with the gain error of less than ±0.5 dB. The two-channel VGAs and peak detectors occupy an area of 1.5 mm×0.4 mm and dissipate 1.71 mW from a single 1.8 V power supply. The DAGC has been integrated in the digital baseband processor and occupies an area of about 0.4 mm×0.4 mm. The max gain lock time of the AGC loop is about 1.25 μs.     

Low-power fully integrated and tunable CMOS RF wireless receiver for ISM band consumer applications

A 0.25-/spl mu/m single-chip CMOS single-conversion tunable low intermediate frequency (IF) receiver operated in the 902-928-MHz industrial, scientific, and medical band is proposed. A new 10.7-MHz IF section that contains a limiting amplifier and a frequency modulated/frequency-shift-key demodulator is designed. The frequency to voltage conversion gain of the demodulator is 15 mV/kHz and the dynamic range of the limiting amplifier is around 80 dB. The sensitivity of the IF section including the demodulator and limiting amplifier is -72 dBm. With on-chip tunable components in the low-power low-noise amplifier (LNA) and LC-tank voltage-controlled oscillator circuit, the receiver measures an RF gain of 15 dB at 915 MHz, a sensitivity of -80 dBm at 0.1% bit-error rate, an input referred third-order intercept point of -9 dBm, and a noise figure of 5 dB with a current consumption of 33 mA and a 2450 /spl mu/m/spl times/ 2450 /spl mu/m chip area.     

Design method for fully integrated CMOS RF LNA

An efficient method for fully integrated RF CMOS LNA design is presented. A particular input matching topology enables inductor values to be selected in order to be integrated fully and to minimise the input losses. Moreover, an active device sizing method is used to achieve a 50 /spl Omega/ input impedance with a low noise factor. Simulations show a 3.0 dB noise figure at 2.45 GHz for a power consumption of 10 mW in a 0.28 /spl mu/m RF CMOS process.     

SOI technology for radio-frequency integrated-circuit applications

This paper presents a silicon-on-insulator (SOI) integration technology, including structures and processes of OFF-gate power nMOSFETs, conventional lightly doped drain (LDD) nMOSFETs, and spiral inductors for radio frequency integrated circuit (RFIC) applications. In order to improve the performance of these integrated devices, body contact under the source (to suppress floating-body effects) and salicide (to reduce series resistance) techniques were developed for transistors; additionally, locally thickened oxide (to suppress substrate coupling) and ultra-thick aluminum up to 6 /spl mu/m (to reduce spiral resistance) were also implemented for spiral inductors on high-resistivity SOI substrate. All these approaches are fully compatible with the conventional CMOS processes, demonstrating devices with excellent performance in this paper: 0.25-/spl mu/m gate-length offset-gate power nMOSFET with breakdown voltage (BV/sub DS/) /spl sim/ 22.0 V, cutoff frequency (f/sub T/)/spl sim/15.2 GHz, and maximal oscillation frequency (f/sub max/)/spl sim/8.7 GHz; 0.25-/spl mu/m gate-length LDD nMOSFET with saturation current (I/sub DS/)/spl sim/390 /spl mu/A//spl mu/m, saturation transconductance (g/sub m/)/spl sim/197 /spl mu/S//spl mu/m, cutoff frequency /spl sim/ 25.6 GHz, and maximal oscillation frequency /spl sim/ 31.4 GHz; 2/5/9/10-nH inductors with maximal quality factors (Q/sub max/) 16.3/13.1/8.95/8.59 and self-resonance frequencies (f/sub sr/) 17.2/17.7/6.5/5.8 GHz, respectively. These devices are potentially feasible for RFIC applications.     

发展中的RF MEMS开关技术

射频MEMS开关是用MEMS技术形成的新的电路元件,与传统的半导体开关器件相比具有插入损耗低、隔离度大、线性度好等优点,将对现有雷达和通信中RF结构产生重大的影响。介绍了射频MEMS开关的工作原理、优化设计,分析了可靠性问题,举例说明了射频MEMS开关的应用,指出了其发展所面临的问题。     

发展中的RF MEM5开关技术

射频MEMS开关是用MEMS技术形成的新的电路元件,与传统的半导体开关器件相比具有插入损耗低、隔离度大、线性度好等优点,将对现有雷达和通信中RF结构产生重大的影响.介绍了射频MEMS开关的工作原理、优化设计,分析了可靠性问题,举例说明了射频MEMS开关的应用,指出了其发展所面临的问题.     

A low loss RF MEMS Ku-band integrated switched filter bank

A switched Ku-band filter bank has been developed using two single-pole triple-throw (SP3T) microelectromechanical systems (MEMS) switching networks, and three fixed three-pole end-coupled bandpass filters. A tuning range of 17.7% from 14.9 to 17.8 GHz was achieved with a fractional bandwidth of 7.7 /spl plusmn/2.9%, and mid-band insertion loss ranging from 1.7 to 2.0 dB.     

Lateral high-speed bipolar transistors on SOI for RF SoC applications

This paper introduces a novel silicon-on-insulator (SOI) lateral radio-frequency (RF) bipolar transistor. The fabrication process relies on polysilicon side-wall-spacer (PSWS) to self-align the base contact to the intrinsic base. The self-aligned base and emitter regions greatly reduce the parasitic components. In this unique design, the critical dimensions are not limited by lithography resolution. With the control of the SOI film thickness or SWS width, the device can be optimized for higher speed, gain, breakdown, or current drive capability. Furthermore, with no additional mask, both common-emitter and common-collector layout configurations can be realized, providing more flexibility to the circuit design and more compact layout. The experimental f/sub T//f/sub max/ of the high-speed device are 17/28 GHz, the second fastest reported f/sub T/ for lateral bipolar junction transistors (LBJT) so far. As for the high-voltage device, the measured f/sub T//f/sub max/ of 12/30 GHz and BV/sub CEO/ of over 25 V produces a Johnsons product well above 300 GHz /spl middot/V. This figure is currently the closest reported data to the Johnsons limit for lateral BJTs. This technology can easily be integrated with CMOS on SOI. Therefore, it is feasible to build fully complimentary bipolar and MOS transistors on a single SOI substrate to form a true complementary-BiCMOS process. This silicon-based lateral SOI-BJT technology is a promising candidate for realizing future RF SoC applications.     

A fully integrated CMOS super-regenerative wake-up receiver for EEG applications

A fully integrated super-regenerative wake-up receiver for wireless body area network applications is presented. The super-regeneration receiver is designed to receive OOK-modulated data from the base station. A low power waveform generator is adopted both to provide a quench signal for VCO and to provide a clock signal for the digital module. The receiver is manufactured in 0.18 μm CMOS process and the active area is 0.67 mm². It achieves a sensitivity of -80 dBm for 10^-3 BER with a data rate of 200 kbps. The power consumption of the super-regenerative wake-up receiver is about 2.16 mW.     

MEMS technology for optical networking applications

The explosion of the Internet has brought about an acute need for broadband communications, which can only be filled with optical networking. This in turn has resulted in an unprecedented interest in optical micro-electromechanical systems. Since the early days of fiber optics, it has been recognized that micro-optics was a fertile ground for the applications of MEMS. MEMS-based products offer substantial cost and performance advantages for optical networking applications in the area of switching fabrics, variable attenuators, tunable lasers, and other devices. This article provides a review of various types of MEMS technologies for optical networking applications     

RF MEMS phase shifters based on PCB MEMS technology

An X-band main-line type loaded line RF MEMS phase shifter fabricated using printed circuit based MEMS technology is reported. The phase shifter provides a phase shift of 31.6/spl deg/ with a minimum insertion loss of 0.56 dB at 9 GHz for an applied DC bias voltage of 40 V. These phase shifters are suitable for monolithic integration with low-cost phased arrays on Teflon or Polyimide such as low dielectric constant substrates.     

Vertically integrated SOI circuits for low-power and high-performance applications

Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.     

A BioMEMS review: MEMS technology for physiologically integrated devices

MEMS devices are manufactured using similar microfabrication techniques as those used to create integrated circuits. They often, however, have moving components that allow physical or analytical functions to be performed by the device. Although MEMS can be aseptically fabricated and hermetically sealed, biocompatibility of the component materials is a key issue for MEMS used in vivo. Interest in MEMS for biological applications (BioMEMS) is growing rapidly, with opportunities in areas such as biosensors, pacemakers, immunoisolation capsules, and drug delivery. The key to many of these applications lies in the leveraging of features unique to MEMS (for example, analyte sensitivity, electrical responsiveness, temporal control, and feature sizes similar to cells and organelles) for maximum impact. In this paper, we focus on how the biological integration of MEMS and other implantable devices can be improved through the application of microfabrication technology and concepts. Innovative approaches for improved physical and chemical integration of systems with the body are reviewed. An untapped potential for MEMS may lie in the area of nervous and endocrine system actuation, whereby the ability of MEMS to deliver potent drugs or hormones, combined with their precise temporal control, may provide new treatments for disorders of these systems.     

A complete RF power technology assessment for military applications

During many years, the French MOD has supported technology developments and specific MMICs designs for power amplification from S-band to Ku-band, for radar and electronic warfare applications. Due to critical issues at system level, an independent assessment made in a governmental laboratory was required by program officers in order to check all the key parameters of a new technology. The objective of this paper is to present and analyse data obtained on a PPHEMT technology, simultaneously taking into account technology, microwave measurements and reliability issues. The originality of this work is to gather all these aspects, combined by a new RF life test bench with negative and positive temperatures environment.     

A fully integrated 4-channel GMR biochip for biomedical detection applications

This paper proposed a fully integrated 4-channel GMR biochip for biomedical detection assays, including the acquisition analog frontend for small signal extraction, 180° phase shifter, resistor ladder and control circuits for carrier cancellation, and amplifiers. Besides, the overall system was evaluated comprehensively by experiment, and the output noise is as low as \(321.7\mathrm {nV/\sqrt{Hz}},\) which is lower than the signal produced by one single 500nm magnetic particle during the detection.     

Degradation mechanism understanding of NLDEMOS SOI in RF applications

The distinct channel hot-carrier (CHC) degradation mechanisms have been observed in NLDEMOS processed from a SOI CMOS technology. The charge-pumping (CP) technique has evidenced the larger hot-hole efficiency in the damage mechanisms at maximum substrate current condition where a net hole trapping is observed in the overlap region which is further screened by the large increase of interface traps in this region. As a consequence, the device suffers from a mobility reduction due to the series-resistance increase mostly in linear mode which impacts the device speed response to AC signal. Off state stressing exhibits a very similar CHC degradation behavior due to the interface traps which may represents a limitative case for the pulses shape optimisation encountered in Class-E operation. A modified reaction-diffusion modelling is proposed based on the multi-vibrational hydrogen release mechanism which matches the time dependence and saturation effect. Finally, we show that the efficiency of E-Class power amplifier is weakly affected by the series-resistance degradation.     

An SOI LDMOS/CMOS/BJT technology for integrated power amplifiersused in wireless transceiver applications

This paper describes a SOI LDMOS/CMOS/BJT technology that can be used in portable wireless communication applications. This technology allows the complete integration of the front-end circuits with the baseband circuits for low-cost/low-power/high-volume single-chip transceiver implementation. The LDMOS transistors (0.35 μm channel length, 3.8 μm drift length, 4.5 GHz f_T and 21 V breakdown voltage), CMOS transistors (1.5 μm channel length, 0.8/-1.2 V threshold voltage), lateral NPN transistor (18 V BV_CBO and h _FE of 20), and high Q-factor (up to 6.1 at 900 MHz and 7.2 at 1.8 GHz) on-chip inductors are fabricated. A fully-functional high performance integrated power amplifier for 900 MHz wireless transceiver application is also demonstrated     

A fully complementary BiCMOS technology for 10 V mixed-signalcircuit applications

A 10 V fully complementary BiCMOS technology, HBC-10, has been developed for high speed, low noise and high precision mixed signal system integration applications. In this technology, two varieties of CMOS transistors have been implemented for 10 V analog and 5 V digital applications. A gate oxide thickness of 30 nm is utilized for the 10 V CMOS transistors with a lightly doped drain extension added to the NMOS structure to achieve device lifetime in excess of 10 years. A gate oxide thickness of 18 nm is used for 5 V CMOS logic circuits. These transistors are specially architected so that they may also serve as analog transistors in 5 V circuit applications. The 5 V NMOS transistor lifetime is guaranteed by use of a double diffused drain structure. The active devices are isolated by a fully recessed 1.5 μm oxide grown under high pressure conditions. Use of high pressure steam, plus combining diffusion operations where possible, results in a low overall thermal budget. This allows the up-diffusion of buried layers to be minimized so that a thin, 1.6 μm epitaxial silicon layer is sufficient to support 10 V bipolar transistors. The resultant vertical PNP and NPN transistors are characterized with cut-off frequencies of more than 1.3 GHz and 5 GHz, respectively. Likewise, the associated products of the current gain and Early voltage of PNP and NPN bipolar transistors are more than 1000 and 6000 V, respectively. A precision, buried Zener diode (for voltage reference applications), PtSi Schottky diode, polysilicon-oxide-polysilicon capacitor and trimmable thin film resistor are integrated into this process. This wide variety of passive and active components is essential for system integration and has been carefully designed for precision analog applications. The total number of masking operations is 23, which includes double layer metallization