Tapered windows in phosphorus-doped SiO2by ion implantation

Phosphorus-doped SiO2is frequently used as a dielectric coating in silicon integrated circuits. It is important that windows in this dielectric have sufficiently tapered walls so that the subsequent metallization has good step coverage. It is shown here that tapered windows can be made in both Nitrox-deposited ∼ 1-percent phosphorus-doped SiO2and Silox-deposited ∼ 7-percent phosphorus-doped SiO2as well as undoped SiO2by an ion implantation which produces a thin damaged layer at the top of the oxide. The damaged layer etches at a faster rate than the undamaged oxide. This fast-etching layer undercuts the photoresist which serves as the etching mask and results in window walls having slopes in the range of 30-40° with respect to the wafer surface. Tapering windows by ion implantation is a dependable process that gives reproducible results without having to rely on the art of photoresist liftoff methods.     

C-MOS/SIS—Using selective SF6etching of {1102} sapphire

A process for selectively etching holes in {1102} sapphire using SF6in H2is described. SiO2, Si3N4, and combinations thereof are studied as possible etchant masks. Refilling the holes with epitaxial silicon produces an SIS (silicon-in-sapphire) wafer wherein the silicon islands are imbedded into the sapphire substrate. The electrical characteristics of C-MOS/SIS transistors are similar to those of conventionally processed SOS devices.     

On the origin of leakage currents in silicon-on-sapphire MOS transistors

n-channel n-p-n metal-oxide-semiconductor transistors (MOST's), fabricated in thin films of silicon-on-sapphire, exhibit values of source-to-drain leakage currents (IL)which vary from wafer to wafer, typicaily from 10^-11to 10^-7A/mil of channel width. Conversely, p-channel (p-n-p) devices exhibit low leakage current values in the range of 10^-11∼ 10^-10A/mil of channel width, consistent from wafer to Wafer. A model of a high concentration of donorlike states in the silicon in the vicinity of the Al2O3-Si interface creating a back-surface Conductive channel is proposed to account for both the inconsistently high n-channel and consistently low p-channel leakage current values. Experimental measurements of IL, which support the general conclusions of the model, are presented. ILis shown to be a strong function of a) the annealing temperature of the sapphire substrate prior to film growth, b) the silicon-film growth rate, c) the impurity concentration profile in the channel region, and d) the device geometry. These measurements show that the dominant factor controlling the overall magnitude of ILis the state of the Al2O3-Si interface immediately prior to silicon-film growth. A set of silicon-film growth conditions and device processing steps is outlined which achieve consistent n- and p-channel leakage current values of less than 10^-9A/mil of gate width.     

Optical multiplication in solid-state imaging devices with an inherent MNOS Memory gate

A simple model is developed which is capable of predicting the product LΔ VFB, where L is the incoming irradiance, and Δ VFBis the flat-band voltage shift of the memory gate, which is proportional to the exposing light signal in the previous write cycle. Preliminary experimental results are presented which confirm the model. The optical multiplication feature leads to a real-time two-dimensional image processor through which spatial convolution or correlation can be obtained.     

用相干激光束曝光孔点阵列图形的几种方法

将涂有光致抗蚀剂的硅片或其它光敏材料置于由多束相干光以某种方式组合构成的干涉场中,可以在大视场和深曝光场内形成孔、点或锥阵周期图形,光学系统简单廉价,不需掩模和高精度大NA光刻物镜,采用现行抗蚀剂工艺。文中介绍的双光束双曝光法得到的阵列图形周期d的极限为dm i n=λ/2,四光束单曝光的周期略大,为前者的2倍,三光束单曝光得到2/3 d周期的图形,并且图形不受基片在曝光场中位置的影响,适合大面积尺寸器件中周期图形的制作,而三光束双曝光和五光束曝光的结果是周期为2d的阵列图形,并且沿光轴方向光场随空间位置也作周期变化,适合在大纵深尺寸范围内调制物体结构。     

Integrated silicon-PVF2acoustic transducer arrays

A new type of transducer array has been designed which employs a piezoelectric polymer, polyvinylidene fluoride (PVF2), as the sensing material. Acoustic properties possessed by this piezoelectric polymer provide a reasonable match to those of the human body making it very attractive for medical ultrasonic imaging systems. Using planar integrated-circuit (IC) technology, an array of MOSFET input amplifiers is fabricated on a silicon wafer. A single sheet of PVF2is bonded to the surface of the wafer. Spatially varying acoustic signals detected by the PVF2are converted to corresponding charge distributions on the underlying array of amplifiers. A linear 34-element receiving transducer array has been built and evaulated. Array transverse dimensions are 14.7 × 9 mm, so that the silicon die area is approximately 1.32 cm². Individual transducers are 0.42 × 9 mm corresponding to the requirements of a particular system. Associated with each of the 34 transducers is a DMOS-bipolar cascode amplifier. Experimentally measured transducer impulse response decays 20 dB in two cycles. Using silicon technology, arrays of almost arbitrary size and complexity appear feasible.     

激光直写系统制作掩模和器件的工艺

激光直写系统是国际上９０年代制作集成电路光刻掩模版的新型专用设备。微细加工光学技术国家重点实验室从加拿大引进了国内第一台激光直写系统。利用这台系统，通过高精度激光束在光致抗蚀剂上扫描曝光，将设计图形直接转移到掩模或硅片上。激光直写系统的应用，可以分成一次曝光制作光刻掩模和多次套刻曝光制作器件两个方面。介绍使用激光直写系统制作光刻掩模和套刻器件的具体工艺，并给出利用激光直写工艺做出的一些掩模和器件的实例     

Formation of low surface energy separators with undercut structures via a full-solution process and its application in inkjet printed matrix of polymer light-emitting diodes

In this paper, low surface energy separators with undercut structures were fabricated through a full-solution process. These low surface energy separators are more suitable for application in inkjet printed passive-matrix displays of polymer light-emitting diodes. A patterned PS film was formed on the P4VP/photoresist film by microtransfer printing firstly. Patterned Au-coated Ni film was formed on the uncovered P4VP/photoresist film by electroless deposition. This metal film was used as mask to pattern the photoresist layer and form undercut structures with the patterned photoresist layer. The surface energy of the metal film also decreased dramatically from 84.6 mJ/m² to 21.1 mJ/m² by modification of fluorinated mercaptan self-assemble monolayer on Au surface. The low surface energy separators were used to confine the flow of inkjet printed PFO solution and improve the patterning resolution of inkjet printing successfully. Separated PFO stripes, complement with the pattern of the separators, formed through inkjet printing. The separators also realized the patterning of cathodes. A passive-matrix display device was obtained through the assistant patterning of low surface energy separators.     

A double-discharge-initiated HF laser

A double-discharge hydrogen fluoride chemical laser using SF6+ C4H10and SF6+ H2is described. A maximum pulse energy of 102.5 mJ is reported, with a peak power of about 400 kW. The energy density is 300 mJ/l, and the electrical efficiency is 0.6 percent.     

Device fabrication in {100} silicon-on-oxide produced by a scanning CW-laser-induced lateral seeding technique

By using a CW-laser-beam-induced lateral seeding technique, which is a zone-melting crystal-growth process, single-crystal silicon-on-oxide with{100}orientation has been obtained. To adopt this process for silicon-on-insulator (SOI) MOS transistor fabrication, a masking level has been added to an exisiting n-MOSFET mask set so that a fully recessed oxide layer may be grown in selected regions of a silicon wafer; the exposed silicon region becomes the seed region. After depositing a 0.5-µm-thick layer of undoped low-pressure CVD polysilicon on the wafer, a laser process is performed to induce epitaxial growth in the polysilicon-on-silicon region, which in turn seeds the zone growth of the polysilicon-on-oxide region as the beam is traversed across the surface of the wafer. N-channel MOS transistors have been fabricated in the silicon-on-oxide material using projection printing lithography. Both complete-island-etch (CIE) and LOCOS techniques have been used for device-to-device and device-to-substrate isolation. Surface electron mobilities as high as 740 cm²/V . s, comparable to that obtainable in bulk-type devices, have been measured in 5-µm channel-length devices. It is shown that the back interface between the recrystallized silicon and the oxide layer is the dominant contributor to the subthreshold leakage current due to a combined effect of a high fixed oxide charge density and drain-induced barrier lowering. A high dose (sim 10^{12}cm^-2) deep boron implantation centered at the back interface and a back-gate bias have been shown to be effective in suppressing the leakage current to as low as 1-pA/µm channel width at VDS= 2 V, comparable to the best results obtained in silicon-on-sapphire (SOS).     

Optical lithography

This is the first in a series of papers describing a theoretical process model for positive photoresist. This model, based upon a set of measurable parameters, can be used to calculate the response of photoresist to exposure and development in terms of image surface profiles. The model and its parameters are useful in many ways, from measuring quantitative differences between different resist materials to establishment of process sensitivities and optimization of the resist process within a manufacturing system. In this paper, the concepts of photoresist modeling are introduced by following the exposure and development of a photoresist film on silicon exposed by a uniform monochromatic light flux. This very simple example provides insight into the complex nature of the photoresist process for reflective substrates. The accompanying paper, "Characterization of Positive Photoresists," gives detail about measurement of the new photoresist parameters. It is supported by "In-Situ Measurement of Dielectric Thickness During Etching or Developing Processes" which discusses automated experimental techniques needed to establish photoresist development rates. These resist parameters provide a complete quantitative specification of the exposure and development properties of the resist. They also allow quantitative comparisons: lot to lot, material to material, and processing condition to processing condition. The fourth paper, "Modeling Projection Printing of Positive Photoresists," applies the process model to one technique of photoresist exposure. This paper contains the detailed mathematics of the model. The model is then used to calculate line-edge profiles For developed resist images.     

Plasma Etching for Sub-45-nm TaN Metal Gates on High-k Dielectrics

Etching of TaN gates on high-k dielectrics (HfO₂ or HfAlO) is investigated using HBr/Cl₂ chemistry in a decoupled plasma source (DPS). The patterning sequence includes 248-nm lithography, plasma photoresist trimming, etching of a SiN-SiO₂ hard mask, and photoresist stripping, followed by TaN etching. TaN etching is studied by design of experiment (DOE) with four variables using a linear model with interactions. It is found that at a fixed substrate temperature and wafer chuck power, etch critical dimensions (CD) gain decreases with decreasing HBr/Cl₂ flow rate ratio and pressure and with increasing source power and total gas flow rate. Based on these DOE findings, subsequent optimization is performed and a three-step etching process is developed; a main feature of the process is progressively increasing HBr/Cl₂ flow rate ratio. The optimized process provides etch CD gain within 2 nm and gate profile close to vertical and reliable etch-stop on high-k dielectric. This process is successfully applied to the fabrication of the 40-nm HfAlO/TaN gate stack p-MOSFETs with good electrical parameters     

A review of recent experiments pertaining to hole transport in Si3N4

In spite of the recent accumulation of experimental evidence for hole conduction in Si3N4it has been largely ignored in modeling of MNOS devices, especially, when hole injection from the metal electrode should have been considered. A review of recent experiments related to hole conduction in Si3N4films deposited on silicon is given. The experiments include: photo-induced and darkI-V; C-Vand flat-band tracking; charge-centroid; and shallow junction "carrier-type" experiments. The case for hole conduction is established firmly for both polarities of applied voltage; however, while agreement exists that holes dominate the conduction for negative polarity (injection of holes from the silicon substrate), differences of opinion remain about the role of electron conduction under positive polarity. A comparison of the qualitative features of the valence band structure of Si3N4and SiO2is included to show that the same reason for low hole conduction in SiO2is not expected in Si3N4.     

The area of safe operation of transistors for switching operation

A thermal feedback model is presented for the analytical definition of the ASO (Area of Safe Operation) for transistors in switching operations. This area is narrowed by the "second breakdown in p-n junction," and the approximate representation of the breakdown threshold is presented. This model consists of a forward and feedback energy flow with gains A and B, respectively.A = V_{CE} times M, B = K times theta times alpha_{R} times I_{e}. Therefore, the condition of the breakdown can be introduced as1 - AB = 0, whereMis the current multiplication factor, θ is transient thermal resistance,Kis a newly introduced current concentration factor, and αRis the temperature coefficient of Ie. Experimental results are also reported for a germanium alloy type transistor.     

A high resolution negative electron resist by image reversal

The use of AZ 1350 family photoresists as negative electron resists is described. Conventional photolithographic technology is used to coat and process the resist, with the exception of an e-beam exposure for patterning. A flood UV exposure is used for image reversal. Using 1.5 µm initial thickness, the exposure threshold for 6 s development in 1 : 1 AZ : H2O developer is 7 µC/cm². The resist contrast under these conditions is 1.3; and the sensitivity is about 25 µC/cm²(70% thickness remaining). Useful resolution on SiO2/Si and Al/SiO2/Si substrates is demonstrated to be at least 0.5 µm, and the resist is shown to mask the plasma etching of Al.     

Diffusion and recombination 1/f noise in long n+-p Hg1—xCdxTe diodes

1/f noise in long n⁺-p Hg1-xCdxTe diodes with x = 0.30 is studied at 193 K. The 1/f noise is considered to be generated by diffusion and recombination fluctuations. A distinction is made between cases a (all minority carriers contribute to the 1/f noise) and b (only the excess minority carriers contribute to the 1/f noise). Measurements on long nonplanar diodes show that case a is valid, indicating that all minority carriers contribute equally to the 1/f noise; this should be valid for any long-junction device in which the current flow is by diffusion and recombination of minority carriers. The lifetime τnof the electrons in the p-region is measured by the input impedance method, and the Hooge parameter αHof the device is evaluated. τnis of the order of 10^-6to 10^-7s and depends somewhat on bias. Near zero bias αHis of the order of 5 × 10^-3in close agreement with Handel's coherent state 1/f noise theory, which yields αH= 4.6 × 10^-3. Due to the nonplanar geometry of the studied diodes, the measurement of τnis not always equally reliable. Larger values of τnare accompanied by larger values of αH, because the noise measurements give αH/τn, and its value practically independent of bias. We also evaluated τnby putting αH= 4.6 × 10^-3; the τnvalues are then much closer and agree rather well with Honeywell lifetime tables. Preliminary measurements at 113 K also indicate coherent state 1/f noise, whereas data at 273 K give αH= 5 × 10⁵, in agreement with the Umklapp 1/f noise theory.     

OMR-85光刻胶的研究与应用

在半导体制造中，光刻胶是重要的原材料之一，本文从转速与膜厚，感光灵敏度，图形变化差等方面对ORM-85光刻胶进行了研究，得出了用于大生产的一套工艺，解决了接触式曝光方式粘版的问题及提高了产能。     

Improved sidewall morphology on dry-etched SiO2 masked GaN features

A number of different methods have been investigated for minimizing sidewall roughness on dry etched GaN features formed using high density plasmas. In many instances, striations on dry etched mesas are a result of roughness in the initial photoresist mask employed, and this roughness is transferred sequentially to the dielectric mask and then to the GaN. Flood exposure of the photoresist, optimization of the bake temperature, choice of plasma chemistry, and ion flux/energy for patterning the dielectric mask all influence the final GaN sidewall morphology.     

Plasma etching of polysilicon and Si3N4in SF6with some impact on MOS device characteristics

Accurate delineation of the circuit materials polycrystalline silicon ("poly"), and silicon nitride are important requirements of most SFC process sequences. We have investigated the use of SF6as an active species in the parallel-plate plasma etching of these materials. For the etching of poly there is good selectivity (better the 50:1) with respect to the etch rates of SiO2and positive photoresist. This process has been used in the fabrication of MOS transistor with 3-µm poly-gate lengths and threshold voltages vary by less than 0.05 V both across a wafer and from wafer to wafer. Etching of nitride is less selective and less isotropic than that of poly.     

On the shifting and broadening of impurity bands and their contribution to the effective electrical bandgap narrowing in moderately doped semiconductors

The role of shifting and broadening of the impurity band in determining the effective bandgap narrowing in moderately doped semiconductors, as obtained from the electrical transport experiments, has been discussed. A model complementary to Lee and Fossum's model (which is based on band tails and many body effects and would hold true at comparatively higher dopant concentrations at which the impurity ionization energy has completely disappeared)has been proposed here. It is shown that Mahan's variational calculations when seen in the right perspective explain the movement of impurity states toward the conduction band. Morgan's formulation has been used for the calculation of the density of states in the impurity band. The model quite satisfactorily explains the electrical bandgap narrowing data for dopant concentrations N < N2. For phosphorous-doped silicon, N2is found to be 3×10¹⁹cm^-3.