Designing asynchronous standby circuits for a low-power pager

We have designed asynchronous standby circuits for a pager decoder which dissipate four times less power and are 40% larger in size than synchronous designs. For the total pager unit this means a 37% reduction in power dissipation for nearly no additional area. The decoded chip, which apart from the standby circuits is completely synchronous, has been fabricated and was first-time-right. Two problems had to be solved to incorporate asynchronous subcircuits in a synchronous environment: synchronization and testing. A synchronization scheme is described that allows a free intermixing of asynchronous and synchronous modules and a test strategy is proposed in which the scan test facilities in the synchronous environment are used to test the asynchronous modules. One function is prevalent in the standby circuits, namely counting. In an appendix we present the asynchronous design of a so-called loadable counter whose power consumption does not depend on its size     

Designing low-power digital CMOS

The increasing levels of circuit integration are leading to the implementation of highly sophisticated algorithms. Many of the commercial application areas have a requirement for portability, which leads to the need for low-power design. This paper considers the issues and design solutions for complex low-power digital CMOS IC design     

树电运行低功耗电路

美国华盛顿大学的一组研究人员成功地演示了树木产生的电力足以独立地维持定制电路的运转.这个研究小组并不指望使用树电替代太阳能,但这套系统可以为那些可能被用于检测环境条件或森林火灾的树木传感器提供一种低成本的洗择.     

Novel low-voltage low-power full-swing BiCMOS circuits

A novel BiCMOS full-swing circuit technique with superior performance over CMOS down to 1.5 V is proposed. A conventional noncomplementary BiCMOS process is used. The proposed pull-up configuration is based on a capacitively coupled feedback circuit. Several pull-down options were examined and compared, and the results are reported. Several cells were implemented using the novel circuit technique; simple buffers, logic gates, and master-slave latches. Their performance, regarding speed, area, and power, was compared to that of CMOS for different technologies and supply voltages. Both device and circuit simulations were used. A design procedure for the feedback circuit and the effects of scaling on that procedure were studied and reported     

Low-voltage, low-power BiCMOS digital circuits

A new BiCMOS buffer circuit, for low-voltage, low-power environment, is presented. The circuit is based on the deep submicron technology and utilizes the parasitic bipolar transistors associated with the CMOS structure. The analysis, simulations and SPICE results confirm the functionality of the circuit and its speed and voltage swing superiority, compared with conventional BiCMOS circuits at low supply voltages     

VLSI circuits for low-power high-speed asynchronous addition

This paper presents a new low-power high-speed fully static CMOS variable-time adder. The VLSI implementation proposed here is based on the statistical carry look-ahead addition technique. The new circuit takes advantage of an innovative way of using a composition of propagate signals and of appropriately designed overlapped execution modules to reduce average addition time, layout area, and power dissipation. A 56-bit adder designed as described here and realized using AMS 0.35-/spl mu/m CMOS standard cells at 3.3V supply voltage shows an average addition time of about 4.3 ns and a maximum power dissipation of only 50 mW at 200-MHz repetitive frequency using a silicon area of less than 0.23 mm/sup 2/.     

Technology for the design of low-power circuits

Operation of integrated circuits at micropower levels requires transistors with adequate current gain at collector currents of 1 /spl mu/A and less and resistors of the order of 1 M/spl Omega/ within reasonable areas. Factors affecting current gain at low currents are discussed and design criteria presented that optimize gain at low collector current. A benefit of micropower operation is low-current noise. Factors tending to optimize noise performance are discussed. In order to obtain voltage gain at low collector current, high values of load resistance are required. Both passive and active loads suitable for incorporation in micropower integrated circuits are discussed.     

Designing of low-power data oriented adders

The paper presents an idea of designing of low-power adders addressed to specific data processing. Mainly, the idea consists in proper choosing of 1-bit full adder cells for given probability of summed data, to obtain reduction in consumed power. Additionally different structures of the cells can be used, in one design, if it leads to reduction of power dissipation. To proper choice of structures of 1-bit full adders theirs energy characteristic versus summed data is needed. So, at the beginning we present results of assessment of a few 1-bit adder cells selected from literature and designed in UMC180 CMOS technology. The extended model of power consumption, taking into consideration input vector changes, was used, giving more accurate values than traditional model based on switching activity only. Thanks to the use of this model, obtained results allow detailed analysis of 1-bit adders on account of the using them in designing of low-power multi-bit adders summing specific data. Based on the results of analyses and given characteristic of summed data, appropriate full adder cells can be chosen to the final design of low-power data oriented adder. In specific case, cells which are made in different techniques can be used in multi-bit adder. A few examples are shown at the end of the paper.     

Minimizing detection-to-boosting latency toward low-power error-resilient circuits

Dynamic voltage scaling (DVS) has become one of the most effective approaches to achieve ultra-low-power SoC. To eliminate timing errors arising from DVS, several error-resilient circuit design techniques were proposed to detect and/or correct timing violations. The most recently proposed time-borrowing-and-local-boosting (TBLB) technique has the advantage of lower power consumption and less performance degradation due to the needlessness of pipeline stalls. On the other hand, to make the best use of the TBLB technique, the latency from error detection to voltage boosting for TBLB latches must be carefully considered, especially during physical design. To address this issue, this paper first introduces the behavior of TBLB circuits, and then presents two major design styles of TBLB latches, including TBLB macros and multi-bit TBLB latches, for reducing detection-to-boosting latency. The corresponding physical synthesis methodologies for both design styles are further proposed. Experimental results based on the IWLS benchmarks show that the proposed physical synthesis approach for resilient circuits with multi-bit TBLB latches is very effective in reducing the delay of both combinational and error-detection circuits, which indicates better circuit reliability. To our best knowledge, this is the first work in the literature which introduces the physical synthesis methodologies for TBLB resilient circuits.     

Dual-threshold voltage techniques for low-power digital circuits

Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation. This paper presents several dual-threshold voltage techniques for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks. MTCMOS sleep transistor sizing issues are addressed, and a hierarchical sizing methodology based on mutual exclusive discharge patterns is presented. A dual-V_t domino logic style that provides the performance equivalent of a purely low-V _t design with the standby leakage characteristic of a purely high-V_t implementation is also proposed     

High-speed, low-power, implanted-buried-oxide CMOS circuits

CMOS ring oscillators with channels less than 1/2 µm long were fabricated in implanted-buried-oxide, silicon-on-insulator films using direct-write electron-beam lithography. Transistors with polysilicon gate lengths as short as 0.4 µm and effective channel lengths as short as 0.21 µm operate satisfactorily. Ring oscillators have delays per gate of 52 and 83 ps and power-delay products of 55 and 5 femtojoules for supply voltages of 5 and 3.3 V, respectively.     

Phase assignment for synthesis of low-power domino circuits

High performance circuit techniques such as domino logic have migrated from the microprocessor world into more mainstream ASIC designs but domino logic comes at a heavy cost in terms of total power dissipation. A set of results related to automated phase assignment for the synthesis of low-power domino circuits is presented: (1) it is demonstrated that the choice of phase assignment at the primary outputs of a circuit can significantly impact lower dissipation in the domino block, and (2) a method to determine a phase assignment that minimises power consumption in the final circuit implementation is proposed. Preliminary experimental results on a mixture of public domain benchmarks and real industry circuits show potential power savings as high as 34% over the minimum area realisation of the logic. Furthermore, the low-power synthesised circuits still meet timing constraints     

Design principles for low-voltage low-power analog integrated circuits

In this paper it is argued that there are good reasons to choose current as the information-carrying quantity in the case of low-voltage low-power design constraints. This paper focuses on the influence of the transfer quality on that choice. To obtain power-efficient transfer quality, indirect feedback is shown to be a good alternative to traditional feedback techniques.     

Low-voltage low-power improved linearity CMOS active resistor circuits

A tutorial of CMOS active resistor circuits will be presented in this paper. The main advantages of the proposed implementations are the improved linearity, the small area consumption and the improved frequency response. In order to improve their linearity, improved performances linearization techniques will be proposed, with additional care for compensating the errors introduced by second-order effects. Design techniques for minimizing the silicon area consumption will be further presented and FGMOS (Floating Gate MOS) transistors will be used for this purpose. The frequency response of the circuits is very good as a result of biasing all MOS transistors in the saturation region and of a current-mode operation of an important part of their blocks. Additionally, small changing in each design allows to obtain negative controllable equivalent resistance circuits. The circuits are implemented in CMOS technology, SPICE simulations confirming the theoretical estimated results, showing small values of the linearity error (under 0.15% for the best design) for an extended input range and for a supply voltage equal with ±3 V. The proposed circuits respond to low-voltage low-power requirements, their design being adapted to the continuous degradation of the model quality associated with the evolution toward latest nanotechnologies.     

Vertically integrated SOI circuits for low-power and high-performance applications

Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.     

Designing digital monolithic integrated circuits

In order to properly design or specify integrated circuits, the circuits engineer today must not only train himself in semiconductor component theory and design principles, but he must also become thoroughly familiar with the technology limitations that govern the manufacture of integrated circuits. So far, there is no set of design rules that apply generally to the great variety of circuits that may be required. The design approach to digital circuits, for example, can be entirely different from that of linear circuits from the standpoint of both technical and economic considerations. Yet an excellent insight into integrated circuit design can be obtained by following the theory and design procedure for translating a typical digital circuit design into a final monolithic device.In the following discussion, the highlights of integrated circuit theory, design relationships, processes and parameters will be developed to cover most of today's applications of monolithic circuits in digital computers. The vehicle for this is a high-speed DTL NAND gate, Fig. 1, currently being manufactured in quantity by Motorola.     

Mixed Full Adder topologies for high-performance low-power arithmetic circuits

This paper deals with the implementation of Full Adder chains by mixing different CMOS Full Adder topologies. The approach is based on cascading fast Transmission-Gate Full Adders interrupted by static gates having driving capability, such as inverters or Mirror Full Adders, thus exploiting the intrinsic low power consumption of such topologies. The obtained mixed-topology circuits are optimized in terms of delay by resorting to simple analytical models.Delay, power consumption and the Power-Delay Product (PDP) in both mixed-topology and traditional Full Adder chains were evaluated through post-layout Spectre simulations with a 0.35 μm, 0.18 μm and 90 nm CMOS technology considering different design targets, i.e., minimum power consumption, PDP, Energy-Delay Product (EDP) and delay. The results obtained show that the mixed-topology approach based on Mirror adders are capable of a very low power consumption (comparable to that of the low-power Transmission-Gate Full Adder) and a very high speed (comparable with or even greater than that of the very fast Dual-Rail Domino Full Adder). This also enables a high degree of design freedom, given that the same (mixed) topology can be used for a wide range of applications. This greater flexibility also affords a significant reduction in the design effort.     

High-speed low-power circuits fabricated using a submicron NMOS technology

We present results on very high-speed low-power devices and circuits fabricated using a NMOS technology scaled to submicron dimensions. These results illustrate the electrical behavior of single minimum-size devices, and present the performance of several submicron circuits, such as ring oscillators, a 3-GHz divide-by-two counter and a 90- MHz 16 × 16 multiplier.     

GaAs low-power integrated circuits for a high-speed digital signalprocessor

A high-speed 4-bit ALU, 4×4-bit multiplier, and 8×8-bit multiplier/accumulator have been implemented in low-power GaAs enhanced/depletion E/D direct-coupled FET logic (DCFL). Circuits are fabricated with a high-yield titanium tungsten nitride self-aligned gate MESFET process. The 4-bit ALU performs at up to 1.2 GHz with only 131-mW power dissipation. The multiplication time for the 4×4-bit array multiplier is 940 ps, which is the fastest multiplication time reported for any semiconductor technology. The 8×8-bit two's complement multiplier/accumulator uses 4278 FETs (1317 logic gates) and exhibits a multiplication time of 3.17 ns. the fastest yet reported for a multiplier of this type. Yield on the best wafer for the 4×4-bit and 8×8-bit circuits is 94 and 43%, respectively. A digital arithmetic subsystem has been demonstrated, consisting of the 8×8-bit multiplier/accumulator, two of the 4-bit ALUs, three logical multiplexers, and a logical demultiplexer. The subsystem performs arithmetic and logic functions required in signal processing at clock rates as high as 325 MHz     

A new systematic design approach for low-power analog integrated circuits

In this paper, a new design approach for systematic design and optimization of low-power analog integrated circuits is presented based on the proper combination of a simulation-equation based optimization algorithm using geometric programming as an optimization approach and HSPICE as a simulation and verification tool by a knowledge-based transistor sizing tool which uses physical-based gm/I_D characteristic in all regions of transistor operation to increase the accuracy in a reasonable simulation time. The proposed design methodology is successfully used for automated design and optimization of an operational amplifier with hybrid-cascode compensation using 0.18 μm CMOS technology parameters with the main purpose of minimizing the power consumption of the circuit.