A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology

A 33.6–33.8 Gb/s burst-mode clock/data recovery circuit (BMCDR) is presented in this paper. To reduce the data jitter and generate the high-frequency output clock, the LC gated voltage-controlled oscillator is presented. To receive and transmit the broadband data, a wideband input matching circuit and a wideband data buffer are presented, respectively. The phase selector is proposed to overcome the false phase lock due to the full-rate operation. This proposed BMCDR has been fabricated in a 90 nm CMOS process. The measured peak-to-peak and rms jitters for the recovered data are 7.56 ps and 1.15 ps, respectively, for a 33.72 Gb/s, 2 $^{11} -$1 PRBS. The measured bit error rate is less than $10^{-8}$ for a 33.72 Gb/s, 2$^{7} -$1 PRBS. It consumes 73 mW without buffers from a 1.2 V supply.      

5?Gb/s 2:1 fully-integrated full-rate multiplexer with on-chip clock generation circuit in 0.18-μm CMOS

A 5?Gb/s 2:1 full-rate multiplexer (MUX) has been designed and fabricated in SMIC 0.18-??m CMOS process. A clock generation circuit (CGC) is also integrated to provide the MUX with both 2.5 and 5-GHz clock signals. The CGC is realized by a clock and data recovery (CDR) loop with a divide-by-2 frequency divider embedded in, where the two required clocks are obtained after and before the divider, respectively. In addition, the phase relation between data and clock is assured automatically by CDR feedback loop and the precise layout. The whole chip area is 812?×?675???m, including pads. At a single supply voltage of 1.8?V, the total power consumption is 162?mW with an input sensitivity of <25?mV and a single-ended output swing of above 300?mV. And due to the full-rate architecture, the pulse width distortion (PWD) with multiplexed data is removed. The measured results also show that the circuit can work reliably at any input data rate between 2.46 and 2.9?Gb/s without need for external components, reference clock, or manual phase alignment between data and clock.     

Low supply voltage operation of over-40-Gb/s digital ICs based on parallel-current-switching latch circuitry

We implemented a low-voltage latch circuit topology in a full-rate 4:1 multiplexer (MUX) using InP-HBT technology. The proposed latch circuitry incorporates parallel current switching together with inductive peaking a combination that makes it suitable for over-40-Gb/s operation at supply voltages ranging from 1.5 to 1.8 V. The full-rate 4:1 MUX provided 40-Gb/s error-free operation with a power dissipation of only 1 W at a supply voltage of 1.8 V. The D-flip/flop (D-F/F) based on this latch circuitry provided 50-Gb/s D-F/F operation at a supply voltage as low as 1.5 V. Demultiplexing operation was also confirmed for the D-F/F with this circuit technology at a data rate of up to 110Gb/s with a 1.8-V supply voltage. The latch circuitry should help enable development of a low-voltage 40-Gb/s full-rate module which can be seamlessly connected with high-speed CMOS I/O circuits.     

A 140-Mb/s to 1.82-Gb/s Continuous-Rate Embedded Clock Receiver for Flat-Panel Displays

A wide-range fast-locking embedded clock receiver, which can provide a continuous data rate of 140 Mb/s to 1.82 Gb/s in a 0.25-mum CMOS process, is presented. A fast lock time of 7.5 mus and a small root-mean-square jitter of 15 ps are achieved by using the proposed frequency-band selection and frequency acquisition schemes, as well as a simple linear-phase detector. The implemented embedded clock receiver occupies 2.00 mm² and consumes currents of 44 and 137 mA at 140 Mb/s and 1.82 Gb/s, respectively, including input/output currents.     

A 2.5-Gb/s fully-integrated, low-power clock and recovery circuit in 0.18-μm CMOS

Based on the devised system-level design methodology, a 2.5-Gb/s monolithic bang-bang phase-locked clock and data recovery (CDR) circuit has been designed and fabricated in SMIC's 0.18-μm CMOS technology. The Pottbacker phase frequency detector and a differential 4-stage inductorless ring VCO are adopted, where an additional current source is added to the VCO cell to improve the linearity of the VCO characteristic. The CDR has an active area of 340 × 440μm2, and consumes a power of only about 60 mW from a 1.8 V supply voltage, with an input sensitivity of less than 25 mV, and an output single-ended swing of more than 300 mV. It has a pull-in range of 800 MHz, and a phase noise of-111.54 dBc/Hz at 10 kHz offset. The CDR works reliably at any input data rate between 1.8 Gb/s and 2.6 Gb/s without any need for reference clock, off-chip tuning, or external components.     

A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver

A CMOS low-power mixed-signal clock and data recovery circuit is presented in this paper. It is designed for OIF CEI-6G+ LR backplane transceiver, and consists of a phase detector, loop filter, phase control logic, and phase interpolator. A unique subsampled architecture makes it possible for a low-power mixed-signal clock recovery loop running at a rate of 6 Gb/s. The proposed architecture has data pattern independent loop bandwidth. Fabricated in a 0.13-/spl mu/m CMOS technology in an area of 280/spl times/100 /spl mu/m/sup 2/, the clock and data recovery loop exhibits a frequency tracking range up to 2000 ppm. The bit error rate is less than 10/sup -12/ with a pseudorandom bit sequence of length 2/sup 31/-1. The power dissipation is 24 mW for clock and data recovery circuits from a single 1.2-V supply.     

10Gb/s CMOS时钟和数据恢复电路的设计

介绍了利用0.18μmCMOS工艺实现了应用于光纤传输系统SDHSTM-64级别的时钟和数据恢复电路。采用了电荷泵锁相环(CPPLL)结构,CPPLL中的鉴相器能够鉴测相位产生超前滞后逻辑,采样数据具有1∶2分接的功能。振荡器采用全集成LC压控振荡器,鉴相器采用半速率的结构。对应于10Gb/s的PRBS数据(231-1),恢复出的5GHz时钟的相位噪声为-112dBc/Hz@1MHz,同时10Gb/s的PRBS数据分接出两路5Gb/s数据。芯片面积仅为1.00mm×0.8mm,电源电压1.8V时功耗为158mW。     

SiGe-HBT-based 54-gb/s 4:1 multiplexer IC with full-rate clock for serial communication systems

A 4:1 multiplexer (MUX) IC for 40 Gb/s and above operations in optical fiber link systems has been developed. The ICs are based on 122-GHz-f/sub T/ 0.2-/spl mu/m self-aligned selective-epitaxial-growth SiGe HBT technology. To reduce output jitter caused by clock duty distortion, a master-slave delayed flip-flop (MS-DFF) with full-rate clock for data retiming is used at the final stage of the MUX IC. In the timing design of the critical circuit for full-rate clocking, robust timing design that has a wide timing margin between data and clock at the MS-DFF was achieved. Measurements using on-wafer probes showed that the MUX attained 54-Gb/s operation with an output voltage-swing of 400 mVpp. The output rms jitter generated by the MUX was 0.91 ps and tr/tf (10%-90%) was 11.4/11.3 ps at a data rate of 50 Gb/s. Power consumption of the IC was 2.95 W at a power supply of -4.8 V. Error-free operation (<10/sup -12/) in back-to-back configuration of the MUX and a 1:4 DEMUX IC module at a data rate of 45 Gb/s was confirmed. We therefore concluded that the MUX IC can be applied for transmitter functions in optical-fiber-link systems at a data rate of 40 Gb/s and higher for forward error correction.     

2.5Gb/s 0.18μm CMOS时钟数据恢复电路

采用TSMC公司标准的0.18μm CMOS工艺,设计并实现了一个全集成的2.5Gb/s时钟数据恢复电路.时钟恢复由一个锁相环实现.通过使用一个动态的鉴频鉴相器,优化了相位噪声性能.恢复出2.5GHz时钟信号的均方抖动为2.4ps,单边带相位噪声在10kHz频偏处为-111dBc/Hz.恢复出2.5Gb/s数据的均方抖动为3.3ps.芯片的功耗仅为120mW.     

A semi-digital delay-locked loop using an analog-based finite state machine

This brief describes a low-power full-rate semi-digital delay-locked loop (DLL) architecture using an analog-based finite state machine (AFSM) and a polyphase filter. The AFSM architecture uses low-power analog blocks to map high-frequency loop feedback information to low frequency, thus reducing the total power required for digital signal processing and for the macro as a whole. The polyphase filter generates full-rate multiphase outputs for a phase rotator, hence a reference clock of the semi-digital DLL can be generated by any reference source including a phase-locked loop with an LC voltage-controlled oscillator. The prototype semi-digital DLL in 0.12-/spl mu/m CMOS exhibits less than 10/sup -12/ bit error rate at 3.2 Gb/s consuming 60 mW.     

A 2.5-10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization

This paper describes a technique for stabilizing the binary phase detector (PD) gain under various jitter conditions. A dead zone in the phase detector estimates the magnitude of high-frequency data jitter, and the resulting jitter information is used to control the charge-pump current. An alternating edge-sampling (AES) PD reduces hardware overhead by removing possible redundancies in previous dead-zone implementations. A series sense amplifier driven by a single-phase clock helps high-speed data sampling with increased data evaluation time. A dual path voltage-controlled oscillator incorporating dual-loop architecture enables wide-range operation of clock/data recovery circuits with low jitter. Fabricated in a 0.18-/spl mu/m CMOS process, a test transceiver operates from 2.5 to 11.5 Gb/s with a bit-error rate of less than 10/sup -12/ while consuming 540 mW from a 1.8-V supply.     

A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector

A jitter-tolerance-enhanced 10 Gb/s clock and data recovery (CDR) circuit is presented. The proposed architecture cascades 2 half-rate CDRs with different loop bandwidth to relax the design bottleneck and the predicted jitter tolerance can be enhanced without sacrificing the jitter transfer. By using a gated digital-controlled oscillator (GDCO), the proposed GDCO-based phase detector may reduce the cost of this architecture and achieve a wide linear range. This CDR circuit has been fabricated in a 0.13 mum CMOS technology and consumes 60 mW from a 1.5 V supply. It occupies an active area of 0.36 mm². The measured rms jitter is 0.96 ps and the peak-to-peak jitter is 7.11 ps for a 10 Gb/s 2⁷-1 PRBS. The measured bit error rate for a 10 Gb/s 2⁷-1PRBS is less than 10^-12.     

A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a triple-inductive transimpedance amplifier (TIA), direct current (DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers (VGA), and a reference-less clock and data recovery (CDR) circuit with built-in equalization technique. The TIA/VGA front-end measurement results demonstrate 72-dBΩ transimpedance gain, 20.4-GHz −3-dB bandwidth, and 12-dB DC gain tuning range. The measurements of the VGA’s resistive networks also demonstrate its efficient capability of overcoming the voltage and temperature variations. The CDR adopts a full-rate topology with 12-dB imbedded equalization tuning range. Optical measurements of this chipset achieve a 10⁻¹² BER at 26 Gb/s for a 2¹⁵−1 PRBS input with a −7.3-dBm input sensitivity. The measurement results with a 10-dB @ 13 GHz attenuator also demonstrate the effectiveness of the gain tuning capability and the built-in equalization. The entire system consumes 140 mW from a 1/1.2-V supply.     

A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector

This paper presents a 10-Gb/s clock and data recovery (CDR) and demultiplexer IC in a 0.13-mum CMOS process. The CDR uses a new quarter-rate linear phase detector, a new data recovery circuit, and a four-phase 2.5-GHz LC quadrature voltage-controlled oscillator for both wide phase error pulses and low power consumption. The chip consumes 100 mA from a 1.2-V core supply and 205 mA from a 2.5-V I/O supply including 18 preamplifiers and low voltage differential signal (LVDS) drivers. When 9.95328-Gb/s 2³¹-1 pseudorandom binary sequence is used, the measured bit-error rate is better than 10^-15 and the jitter tolerance is 0.5UIpp, which exceeds the SONET OC-192 standard. The jitter of the recovered clock is 2.1 psrms at a 155.52MHz monitoring clock pin. Multiple bit rates are supported from 9.4 Gb/s to 11.3 Gb/s     

10 GHz full-rate clock and data recovery circuit in 0.18 /spl mu/m CMOS without external reference clock

The design of a fully monolithic integrated 10 GHz full-rate clock and data recovery (CDR) circuit in 0.18 /spl mu/m digital CMOS technology, which employs an injection phase-locked loop (PLL) technique is presented. The CDR operating without the external reference exhibits a capture range of 200 MHz while consuming 205 mA current from 1.8 V supply including the output buffer. The recovered clock signal with 250 mV/sub pp/ pseudorandom bit Sequence input data of length 2/sup 31/-1 exhibits 7.9 ps of peak-to-peak (p-p) and 1.1 ps of root-mean-square (RMS) jitter. The measured clock phase noise at 1 MHz offset is approximately -109 dBc/Hz.     

Clock and data recovery circuit with two exclusive-OR phasefrequency detector

A clock and data recovery circuit with a two exclusive-OR phase-frequency detector is proposed. The PFD generates the control signal for the voltage-controlled oscillator (VCO) in the phase-locked loop by comparing different phase clocks and input data. Simulations show that this circuit operates an input at data rate of 800 Mbit/s to 1.2 Gbit/s under 2.5 V using 0.25 μm CMOS technology     

Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection

A fully integrated clock and data recovery circuit (CDR) using a multiplying shifted-averaging delay locked loop and a rate-detection circuit is presented. It can achieve wide range and low jitter operation. A duty-cycle-insensitive phase detector is also proposed to mitigate the dependency on clock duty cycle variations. The experimental prototype has been fabricated in a 0.25-/spl mu/m 1P5M CMOS technology and occupies an active area of 2.89 mm/sup 2/. The measured CDR could operate from 125 Mb/s to 2.0 Gb/s with a bit error rate better than 10/sup -12/ from a 2.5-V supply. Over the entire operating frequency range, the maximum rms jitter of the recovered clock is less than 4 ps.     

A 40 Gb/s CMOS Serial-Link Receiver With Adaptive Equalization and Clock/Data Recovery

This paper presents a 40 Gb/s serial-link receiver including an adaptive equalizer and a CDR circuit. A parallel-path equalizing filter is used to compensate the high-frequency loss in copper cables. The adaptation is performed by only varying the gain in the high-pass path, which allows a single loop for proper control and completely removes the RC filters used for separately extracting the high- and low-frequency contents of the signal. A full-rate bang-bang phase detector with only five latches is proposed in the following CDR circuit. Minimizing the number of latches saves the power consumption and the area occupied by inductors. The performance is also improved by avoiding complicated routing of high-frequency signals. The receiver is able to recover 40 Gb/s data passing through a 4 m cable with 10 dB loss at 20 GHz. For an input PRBS of 2 $^{7}-$1, the recovered clock jitter is 0.3 ps$_{rm rms}$ and 4.3 ps$_{rm pp}$. The retimed data exhibits 500 mV $_{rm pp}$ output swing and 9.6 ps$_{rm pp}$ jitter with ${hbox{BER}}≪ 10^{-12}$ . Fabricated in 90 nm CMOS technology, the receiver consumes 115 mW , of which 58 mW is dissipated in the equalizer and 57 mW in the CDR.      

2.5 Gb／s 16：1 MUX IC Design with CMOS

A low--power and high--speed 16.-1 MUX IC designed for optical fiber communication based on TSMC 0.25μm CMOS technology is presented. A tree—type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak—to—peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8mm^2.     

2.5Gb/s 16:1MUX IC Design with CMOS

A low-power and high-speed 16:1 MUX IC designed for optical fiber communication based on TSMC 0.25 μm CMOS technology is presented. A tree-type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak-to-peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8 mm2.