汽车CAE技术的新进展--虚拟试验场(VPG)技术

一、概述 现代汽车对结构设计提出了越来越高的要求,汽车结构分析已不满足于结构线性弹性分析.实际上汽车结构系统中大量存在非线性结构,例如发动机、驾驶室橡胶支承、悬挂大变形、零部件间连接的能量缓冲等.在产品要求精益设计的条件下,只应用线性分析普遍感到不足.产品开发要求CAE更多地考虑非线性影响.其次,汽车零部件结构分析的一个难点是分析载荷的不定因素,大量零部件结构实际所受到的载荷到底是多大,往往很难明确给出.     

MSC Nastran优化功能在结构强度设计中的应用

对某型飞机机翼主梁,以MSC Patran、 MSC Nastran为基本工具,对其结构进行优化设计. 优化后的结构重量、梁缘条面积、梁腹板厚度满足工程实际要求;通过有限元分析,翼尖扰度也满足变形要求.     

催泪剂焚烧炉气体燃烧室仿真

焚烧炉焚烧法是根据催泪弹的结构特点和药剂的理化特性确定的一种处废方法.焚烧炉分为固体焚烧室和气体焚烧室两大主体部分,其结构和参数是关系到药剂焚烧结果能否达到要求的关键.为验证设计的焚烧炉气体焚烧室的结构参数能否达到预定目标,为焚烧炉的实际生产运行提供参考.在根据要求设计出气体焚烧室结构参数的基础上,运用流体计算软件FLUENT对其中的气体燃烧室进行仿真.仿真结果与实际要求基本符合,说明气体燃烧室的设计能满足催泪剂销毁的要求.     

汽车CAE技术的新进展--虚拟试验场(VPG)技术

一、概述 现代汽车对结构设计提出了越来越高的要求,汽车结构分析已不满足于结构线性弹性分析,实际上汽车结构系统中大量存在非线性结构,例如发动机、驾驶室橡胶支承、悬挂大变形、零部件间连接的能量缓冲等.在产品要求精益设计的条件下,应用线性分析普遍感到不足,产品开发要求CAE更多地考虑非线性影响.其次,汽车零部件结构分析的一个难点是分析载荷的不定因素,大量零部件结构实际所受到的载荷到底是多大?往往很难明确给出.     

基于MSC Nastran的优化技术

减轻结构质量对现代飞机具有极其重要的意义,进行结构优化设计可以更加合理地确定材料分布,提高材料的利用率,从而满足这一目标要求.目前,结构优化技术已广泛应用于飞机结构设计中,通过确定优化设计变量、优化区域以及响应约束,采用MSC Nastran对机翼进行优化设计,在满足强度刚度设计要求的前提下,实现结构质量最轻的设计目标.     

基于PLC和IPC的富氧陶瓷窑炉监控系统设计

针对富氧陶瓷窑炉的控制要求,开发了一套基于PLC和IPC结构的富氧陶瓷窑炉监控系统.首先阐述了窑炉的结构及控制要求,并给出了监控系统的硬件结构;其次,对PLC中的核心程序和上位机监控软件设计的关键问题进行了详细说明;最后,对监控系统的特点进行了总结.     

列车车辆设备安装的过渡件结构优化和应用

对某型号列车车辆下部设备安装的过渡件进行结构分析,发现结构强度冗余较大.为提高材料使用率,减小列车整车整备质量,开展结构轻量化设计研究并提出改进措施.对常用底架设备安装方式进行有限元分析,利用OptiStruct对过渡件进行拓扑优化.根据材料工艺成型特点和结构安全要求对结构进行重新设计,并对新结构进行形状优化,获得最佳优化效果的结构设计方案.     

CMOS电路ESD保护结构设计

静电放电是CMOS电路中最为严重的失效机理之一,严重的会造成电路自我烧毁.论述了CMOS集成电路ESD保护的必要性,研究了在CMOS电路中ESD保护结构的设计原理,分析了该结构对版图的相关要求,重点讨论了在I/O电路中ESD保护结构的设计要求.     

基于实时数据仓库的OLAP研究

传统数据仓库及OLAP应用侧重对历史数据的分析.为了满足实时分析的要求,本文提出了一种实时数据仓库的分区结构.在分析了传统OLAP设计在实时性方面的缺陷后,我们提出了基于分区结构的实时OLAP的设计,使OLAP分析能够达到实时或准实时的要求.     

海水淡化集成系统的模拟与优化

海水淡化系统的集成与优化是提高能源利用效率,降低淡化成本的有效途径.本文提出了多级闪蒸(MSF)与反渗透(RO)的2种集成工艺,以年度总费用最小为目标函数,采用改进的遗传算法进行求解,探讨了不同进料浓度、不同淡水水质要求对2种工艺结构的影响,给出了不同条件下的最优流程结构:当海水浓度大于40000mg·L-1时,宜采用RO-MSF结构.低于40000 mg·L-1时,采用MSF-RO结构;当出水水质要求高时采用RO-MSF集成结构优于MSF-RO集成结构;而当出口淡水水质要求低时,宜采用RO-MSF集成系统.     

Scalable high-throughput variable block size motion estimation architecture

Variable block size (VBS) motion compensated prediction (MCP) provides substantial rate-distortion performance gain over conventional fixed-block-size MCP and is a key feature of the H.264/AVC video coding standard. VBS–MCP requires the encoder to perform VBS motion estimation (VBSME), a computationally complex operation. In this paper, we propose a high motion vector throughput full-search VBSME architecture. High performance is achieved by performing parallel computations for multiple pixels within a macroblock, as well as computing several candidate motion vector (MV) positions in parallel. Two implementations of the architecture are examined, a four pixel-parallel implementation, and a higher performance 16 pixel-parallel implementation. A high degree of scalability is achieved by allowing for a variable length processing element array, where more processing elements yields a higher degree of candidate MV parallelism. The proposed architecture achieves a throughput exceeding current full-search VBSME architectures.     

一种动态存储管理机制

动态存储管理是计算机必不可少的资源管理手段之一。现有的动态存储分配算法存在着效率不高、空间和时间开销较高等缺点。文中提出了一个用多级位示图目录来实现存储资源动态分配的算法，给出了多级位示图目录的结构和相应的算法，并分析了算法的效率，多级位示图目录算法具有结构简单，空间和时间开销小等优点。     

基于Bi-LSTM的财金文本情感分类研究

针对现有文本情感分析方法准确率不高、实时性不强以及特征提取不充分的问题,构建了双向长短时记忆神经网络(Bi-LSTM)模型。利用双向循环长短时记忆神经网络(Bi-LSTM)提取文本的上下文信息;然后,对已提取的上下文特征利用LSTM进行局部语义特征提取;最后,采用语法规则,构建情感分类器。通过与RNN、Bi-LSTM等单一模型对比。实验结果表明,多层LSTM结构相比传统RNN(循环神经网络)的ROUGE(语义恢复度)值更高,具有较好的学习能力。     

一种可变块运动估计结构的优化设计

为支持主流视频编码标准对可变块运动估计（VBSME）的要求,提出一种基于二维脉动阵列的可变块运动估计结构,该结构具有数据重传次数少,存储器带宽要求低,性能高的特性。针对该结构中的大量延迟寄存器开销问题,使用了基于数据流的AON网络模型和动态规划算法,对结构进行了分析,得到了优化的结果。     

Short-term Maharashtra state electrical power load prediction with special emphasis on seasonal changes using a novel focused time lagged recurrent neural network based on time delay neural network model

In this paper, the parameter-wise optimization training process is implemented to achieve an optimal configuration of focused time lagged recurrent neural network (FTLRNN) models by embedding the gamma, laguarre, and multi-channel tapped delay line memory structure. The aim is to examine the prediction ability of the proposed models in order to predict one-day-ahead electric power load simultaneously as usual to oppose 1–24 h forecast in sequel with a special emphasis on seasonal changes over a year. An improved delta-bar-delta algorithm is used to accelerate the training of neural networks and to improve the stability of the convergence.Experimental results indicate that the FTLRNN with time delay neural network (TDNN) clearly outperformed the gamma and laguarre based short-term memory structure in various performance metrics such as mean square error (MSE), normalized MSE, correlation coefficient (r) and mean absolute percentage error (MAPE) during evaluation process. Empirical results show that the proposed dynamic NN model consistently performs well on daily, weekly, and monthly average basis in terms of prediction accuracy. It is noticed from the literature review that an optimally configured FTLRNN with multi-channel tapped delay line memory structure is not currently available to solve short-term electrical power load prediction. The proposed method gives acceptable errors in all seasons, months and on daily basis. The average prediction error on three weeks is obtained as low as 1.67%.     

A comparison of broad versus deep auditory menu structures

OBJECTIVE: The primary purpose of this experiment was to gain a greater understanding of the utilization of working memory when interacting with a speech-enabled interactive voice response (IVR) system. BACKGROUND: A widely promoted guideline advises limiting IVR menus to five or fewer items because of constraints of the human memory system, commonly citing Miller's (1956) paper. The authors argue that Miller's paper does not, in fact, support this guideline. Furthermore, applying modern theories of working memory leads to the opposite conclusion--that reducing menu length by creating a deeper structure is actually more demanding of users' working memories and leads to poorer performance and satisfaction. METHOD: Participants took a working memory capacity test and then attempted to complete a series of e-mail tasks using one of two IVR designs (functionally equivalent, but one with a broad menu structure and the other with a deep structure). RESULTS: Users of the broad-structure IVR performed better and were more satisfied than users of the deep-structure IVR. Furthermore, this effect was more pronounced for those with low working memory capacity. CONCLUSION: Results indicate that creating a deeper structure is more demanding of working memory resource than the alternative of longer, shallower menus. APPLICATION: This experiment has important practical implications for all systems with auditory menus (particularly IVRs) because it provides empirical evidence refuting a widely promoted design practice.     

The use of intermediate memories for low-latency memory access in supercomputer scalar units

One of the prime considerations for high scalar performance in supercomputers is a low memory latency. With the increasing disparity between main memory and CPU clock speeds, the use of an intermediate memory in the hierarchy becomes necessary. In this paper, we present an intermediate memory structure called a programmable cache. A programmable cache exploits structural locality to decrease the average memory access time. We evaluate the concept of a programmable cache by using the vector registers in the CRAY X-MP and Y-MP supercomputers as a programmable cache. Our results indicate that a programmable cache can be used profitably to reduce the memory latency if the pattern of references to a data structure can be determined at compile time.The work of the first author was supported in part by NSF Grant CCR-8706722.     

面向大数据应用的众核处理器缓存结构设计

大规模数据排序、搜索引擎、流媒体等大数据应用在面向延迟的多核/众核处理器上运行时资源利用率低下,一级缓存命中率高,二级/三级缓存命中率低,LLC容量的增加对IPC的提升并不明显。针对缓存资源利用率低的问题,分析了大数据应用的访存行为特点,提出了针对大数据应用的两种众核处理器缓存结构设计方案,两种结构均只有一级缓存,Share结构为完全共享缓存,Partition结构为部分共享缓存。评估结果表明,两种方案在访存延迟增加不多的前提下能大幅节省芯片面积,其中缓存容量较低时,Partition结构优于Share结构,缓存容量较高时,Share结构要逐渐优于Partition结构。由于众核处理器中分配到每个处理器核的容量有限,因此Partition结构有一定的优势。     

RRAM的阻变特性研究

阻变存储器（RRAM）是一种基于阻值变化来记录存储数据信息的非易失性存储器（NVM）,RRAM具有存储单元结构简单、工作速度快、功耗低等诸多优点,因而受到广泛关注。主要从三方面论述 RRAM的阻变特性。     

A workload-aware flash translation layer enhancing performance and lifespan of TLC/SLC dual-mode flash memory in embedded systems

Similar to traditional NAND flash memory, triple-level cell (TLC) flash memory is used as secondary storage to meet the fast growing demands on storage capacity. TLC flash memory exhibits attractive features such as shock resistance, high density, low cost, non-volatility and low access latency natures. However, TLC flash memory also has some extra limitations, such as write disturbance, low performances and very limited cycles compared to single-level cell (SLC) flash memory.In this paper, we propose a workload-aware flash translation layer, named Balloon-FTL, for the TLC/SLC dual-mode flash memory, to improve performance and lifespan of the system. We first build a workload identifier module with genetic algorithm to dynamically allocate TLC/SLC capacity based on different workloads, and produce the suitable data allocation to achieve a balanced write distribution in flash memory with low memory access cost. The basic idea is to classify metadata/userdata according to their access pattern, and allocate low-latency SLC and high-density TLC mode blocks for write-intensive metadata and a large quantities userdata, respectively. We then propose a special hybrid mapping strategy for the TLC/SLC dual-mode flash memory to improve the performance. Experimental results show that Balloon-FTL can effectively improve the performance and lifespan of the TLC/SLC dual-mode flash memory in embedded systems.