Design of PLL-based clock generation circuits

The design of clock generation circuitry being used as a part of a high-performance microprocessor chip set is described. A self-calibrating tapped delay line is used to generate four nonoverlapping clock phases of a system clock. A charge-pump phase-locked loop (PLL) calibrates the delay per stage of the delay line. Using this technique, it is possible to obtain an accurate phase relationship between the off-chip reference clock and the internal clock signals. Experimental results show that required timing relations can be obtained with less than 2-ns clock skew for frequencies from 1 to 18 MHz.     

Post-fabrication clock-timing adjustment using genetic algorithms

To solve the problem of fluctuations in clock timing (also known as "clock skew" problems), we propose an approach for the implementation of post-fabrication clock-timing adjustment utilizing genetic algorithms (GAs). This approach is realized by the combination of dedicated adjustable circuitry and adjustment software, with the values for multiple programmable delay circuits inserted into the clock lines being determined by the adjustment software after fabrication. The proposed approach has three advantages: 1) enhancement in clock frequencies leading to improved operational yields; 2) lower power supply voltages, while maintaining operational yield; and 3) reductions in design times. Two different LSIs have been developed: the first is a programmable delay circuit, developed as an element of the clock-timing adjustment, while the second is a medium-scale circuit, developed to evaluate these advantages in a real chip. Experiments with these two LSIs, as well as a design experiment, have demonstrated these advantages with an enhancement in clock frequency of 25% (max), a reduction in the power-supply voltage of 33%, and a 21% shorter design time.     

A switched-ca pari tor delay line with self-equalizing sample-and-hold

A simple SC delay line using a three-phase clock is described. The new circuit uses a reduced number of operational amplifiers and includes a circuit for correcting the amplitude deviation arising from the sample-and-hold effect Unlike previous circuits this circuit does not affect the group-delay of the delay line. An example for a 10μS delay line in the frequency range 0-250 kHz is given.     

A 270-MHz to 1.5-GHz CMOS PLL clock generator with reconfigurable multi-functions for FPGA

A PLL clock generator with reconfigurable multi-functions for FPGA design applications is presented. This clock generator has two configurable operation modes to achieve clock multiplication and phase alignment functions,respectively.The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable.In order to further improve the accuracy of phase alignment and phase shift,a VCO design based on a novel quick start-up technique is proposed.A new delay partition method is also adopted to improve the speed of the post-scale counter,which is used to realize the programmable phase shift and duty cycle.A prototype chip implemented in a 0.13-μm CMOS process achieves a wide tuning range from 270 MHz to 1.5 GHz.The power consumption and the measured RMS jitter at 1 GHz are less than 18 mW and 9 ps,respectively.The settling time is approximately 2μs.     

Clock buffer chip with multiple target automatic skew compensation

This paper describes the application of a digital delay locked loop that compensates for variable delays on the clock chip, printed circuit board clock traces, and the clock systems on multiple ASICs. For a computer system consisting of nine PC boards (“modules”) plugged into a back plane with two clock chips per board and six ASICs per clock chip, a locking range of 25-150 MHz was achieved with a maximum skew in the system of less than 1 ns     

非时钟同步的单向排队时延测量估计方法

提出了一种测量和估计网络端到端单向排队时延的新方法。与消除时钟偏差和时钟频差的现有方法相比,新方法完全不需要测量端之间的时钟同步。探测分组之间的发送和到达时间间隔在两端分别测量,然后利用傅立叶域-时间域的迭代重构算法估计端到端单向排队时延的分布特性。仿真和分析结果表明新方法具有很好的实时性、准确性和顽健性。     

Virtual fine delay line using one-stage inverter delay

A virtual fine delay line (VFDL) using only two ring oscillators and counters can cover a wide frequency operation range clock without adding any additional delay line stage. The proposed ring oscillator can easily make a unit delay as a one-stage inverter. The VFDL achieves fine resolution of less than 60 ps and small circuit area with two clock cycles lock-in time.     

All Digital Spread Spectrum Clock Generator for EMI Reduction

An effective solution to control electromagnetic interference in computing appliances such as DVD players or home theater systems is to apply modulation on the system clock. The presence of modulation on the clock reduces the radiated power per unit bandwidth. We present the implementation of a spread spectrum clock generator (SSCG) using strictly digital components. A digital delay line (DDLi) controlled by a small digital circuit is used to increase or decrease the delay on a clock and hence create a modulated output. The DDLi total electrical length is no longer than one period of the 27-MHz reference clock as the digital circuit can adjust to the limited length of the line. The circuit can produce up or down spread by modulating the frequency of the reference with a triangular waveform. The measured peak power reduction is greater than 13 dB for a deviation of about 3% and a frequency modulation of 100 kHz. A real-time digital calibration circuit enables a process and temperature independent operation. The circuit occupies 0.06 mm² in a 0.15-mum CMOS process and consumes 7.1 mW     

Simple clock extraction circuit using a self sustaining monostable multivibrator output signal

A novel and simple clock extraction circuit is described. It is based on feedback around a monostable multivibrator resulting in a self sustaining clock signal. The method is suitable for application in systems which do not require the clock perfectly synchronised to the data. The circuit comprises three standard IC gates plus two delay units.     

A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time

A portable clock generator, which solves the duty ratio and jitter problems of the input clock, has been developed. In the proposed clock generator, the complementary delay line generates a series of multiphase clocks. The 0-to-1 transition detector finds the 2 pi phase delayed position among the multiphase clocks produced by the complementary delay line, and then, the select signal generator chooses the proper path to generate the delayed output clock. As a result, the proposed open-loop and full-digital architecture achieves a fast lock time of two clock cycles. Also, it is a simple, robust and portable IP and consumes only 17 mW at an input clock frequency of 1.6 GHz. In addition, a complementary delay line is implemented to achieve high phase resolution over a wide frequency range. The proposed clock generator is implemented in a 0.18-mum CMOS process and, occupies an active area of 170 mum times 120 mum. Also, it operates at various input frequencies ranging from 800 MHz to 1.6 GHz.     

Synchronous mirror delay for multiphase locking

A clock generation circuit having the function of multiphase locking was designed using the synchronous mirror delay (SMD) scheme. The internal clock can be synchronized to the external clock with intended phase difference. The synchronizing error of the clock generation circuit is reduced below the delay time of unit delay stage by compensation characteristics of detecting circuit in SMD. A 32-M double data rate (DDR) SRAM including the clock generation circuit is fabricated using 0.13-/spl mu/m CMOS technology. To measure the synchronizing error of the clock generation circuit, the test elements group (TEG) system is designed and fabricated with the main system. The synchronizing error of the clock generation circuit is far smaller than the delay time of unit delay stage at zero phase locking and similar to the delay time of unit delay stage at multiphase locking.     

A CMOS 1/spl times/-16/spl times/ speed DVD write channel IC

Optical recording demands a meticulous write strategy to control the laser beam power and regulate the phase change layer temperature tightly. The width, height, and delay of a string of short pulses applied to the laser diode need to be adjusted in fine steps, and the writing speed varies widely per applications. A multi-phase phase-locked loop (PLL) tracks a wide range of clock frequencies, and provides a low-jitter time base for write pulses. With two enabling circuit concepts, PLL loop filter voltage folding/unfolding and switch-in of parallel MOS resistors in delay cells, it is possible to operate a PLL to cover a frequency range spanning over three octaves with one VCO. A 10-stage differential VCO is phase-locked to the input channel clock ranging from 26 to 420 MHz (1/spl times/-16/spl times/ DVD speed), and its 20-phase outputs are used to generate write pulses. The pulsewidth and delay are programmed with 120 /spl plusmn/ 40 ps time resolution. The prototype chip fabricated in 0.35 /spl mu/m CMOS occupies 3.5/spl times/3.3 mm/sup 2/, and consumes 294 mW at 3.3 V.     

An open-loop clock deskewing circuit for high-speed synchronous DRAM

An open-loop clock deskewing circuit (CDC) for high-speed synchronous DRAM is described. Unlike the conventional circuits, the CDC does not require an additional measure delay line, thus power consumption is reduced. The delay is measured directly from the main delay line and both the input and output ports of the delay line are movable. The CDC provides a deskewed clock within two clock cycles.     

面向电荷泵的占空比可调四相时钟发生电路北大核心

针对传统四相时钟发生电路产生的时钟波形信号易发生交叠、驱动电荷泵易发生漏电等问题，提出了一种占空比可调四相时钟发生电路。电路在每两相可能出现交叠的时钟信号之间都增加了延时单元模块，通过控制延时时间对输出时钟信号的占空比进行调节，避免了时钟相位的交叠。对延时单元进行了改进，在外接偏置电压条件下，实现了延时可控。基于55 nm CMOS工艺的仿真结果表明，在10～50 MHz时钟输入频率范围内，该四相时钟发生电路可以稳定输出四相不交叠时钟信号，并能在1.2 V电压下驱动十级电荷泵高效泵入11.2 V。流片测试结果表明，该四相时钟发生电路能够产生不相交叠的四相时钟波形，时钟输出相位满足电荷泵驱动需求。     

Sixth-order programmable bandwidth bandpass sigma-delta modulator implemented with transmission lines

An implementation of a sixth-order bandpass continuous time sigma-delta modulator using transmission lines is presented. A single tuning coefficient allows the exchange of resolution and bandwidth in this modulator, owing to the use of a two path transformation that exploits the similarity between transmission line modulators and discrete time modulators. The modulator tolerates two clock cycles of excess loop delay and a high clock jitter.     

Dual-loop DLL-based clock synchroniser

A clock synchronisation scheme based on a newly proposed dual-loop delay locked loop (DLL) is presented. The proposed scheme incorporates analogue and digital DLLs to align phases of two different frequency clocks. Simulation results show that the internal clock can be synchronised to the reference clock by tracking the dual feedback loop. The whole circuit design was implemented using 0.35 μm CMOS technology. Power dissipation is ~42 mW with a single 3.3 V supply     

A direct-skew-detect synchronous mirror delay forapplication-specific integrated circuits

A nonfeedback CMOS digital-clock-generator, direct-skew-detect synchronous-mirror-delay (direct SMD) circuit has been developed that achieves clock-skew suppression in only two clock cycles for application-specific integrated circuits having unfixed and various clock paths. The direct SMD circuit detects both clock skew and clock cycle by using a direct-skew detector and clock-suspension circuitry. The skew-detection scheme removes the phase errors caused by delay in the clock-driver circuit. Measurements demonstrated that the direct SMD circuit eliminates various amounts of clock skew (2.0-3.0 ns) at 200 MHz in two clock cycles     

A high-resolution synchronous mirror delay using successive approximation register

A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the internal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the conventional SMD . Fine locking is achieved by the successive approximation register for the sake of fast locking . Measured results show that the maximum clock skew of the proposed SMD is 140 ps in the frequency range from 170 to 230 MHz and that the consumption power is 14.85 mW at 230 MHz in a 0.35-/spl mu/m 1-poly 4-metal CMOS technology. The total locking time is 10 clock cycles.     

A CMOS high-speed data recovery circuit using the matched delaysampling technique

This paper presents a scheme and circuitry for demultiplexing and synchronizing high-speed serial data using the matched delay sampling technique. By simultaneously propagating data and clock signals through two different delay taps, the sampler achieves a very fine sampling resolution which is determined by the difference between the data and clock delays. This high resolution sampling capability of the matched delay sampler can be used in the oversampling data recovery circuit. A data recovery circuit using the matched delay sampling technique has been designed and fabricated in 1.2-μm CMOS technology. The chip has been tested at 417 Mb/s [2.4 ns nonreturn to zero (NRZ)] input data and demultiplexes serial input data into four 104 Mb/s (9.6 ns NRZ) output streams with 800 mW power consumption at 4 V power supply. While recovering data, the sampling clock running at 1/4 of the data frequency is phase-tracking with the input data based on information extracted from a digital phase control circuit     

A new feedback control method to stabilize fiber-optical parametric oscillators for clock extraction

A new feedback control technique with the capability of dynamic compensation for the cavity length of fiber-optical parametric oscillators (FOPOs) is proposed by analyzing the time delay dependence of the idler optical power. Our experiments show that the idler optical power is approximately proportional to the FOPO cavity length variation or the resulting time delay, and then an electronically tunable optical delay line can be used to significantly improve the stability of the FOPO. By feeding back the idler power, a stable 10 Gb/s clock recovery based on the FOPO is obtained and the normalized time jitter of output clock signal remains at about 1.1%.