电吸收调制器和DFB激光器集成器件的测量

提出了一种测量电吸收调制器和激光器集成器件芯片散射参数的新方法.根据电吸收调制器和封装寄生参数的等效电路模型,对测量的反射系数进行拟合,得到封装寄生参数和电吸收调制器的等效电路元件的参数值.通过分析发现测试封装寄生参数对电吸收调制器的测试结果有很大影响.去除了封装寄生参数的影响后,得到了调制器的反射和传输参数的真实频响特性     

Influence of impact-ionization-induced base current reversal onbipolar transistor parameters

In this paper we describe a set of measurements representing a complete characterization of impact-ionization effects in bipolar transistors. We demonstrate that impact-ionization significantly influences the dependence of base resistance on current and voltages applied to the device. A dc method for the simultaneous extraction of all parasitic resistances in bipolar transistors is presented. The method can separate the influence of current-crowding on the base resistance from that of base width and conductivity modulation; the collector parasitic resistance is measured in the active region. Starting from the parameters extracted by means of these techniques, a complete and accurate circuit-model of impact-ionization effects can be defined     

RF-CMOS建模:MOST在片测试结构寄生分析

提出了一种新的RF-CMOS晶体管在片测试结构寄生模型,模型综合考虑了射频/微波条件下RF-MOST器件在片测试结构中的各种寄生效应.模型考虑了PAD-互连金属、互连金属-DUT(device under test)之间的非连续性,对互连金属和基底之间的寄生效应单独进行了考虑.通过引入一个新的元件,对PAD结构基底感性损耗进行表征.模型最终应用到采用CSM(Chartered Semiconductor Manufacture Ltd)0.25 μm RF-CMOS工艺制造的测试结构寄生效应等效电路建模中,高达40GHz测试和仿真数据验证了模型的良好精度.     

An accurate on-wafer deembedding technique with application to HBTdevices characterization

An accurate deembedding technique for on-wafer measurements of an active device's S-parameter is presented in this paper. This deembedding technique accounts in a systematic way for effect of all parasitic elements surrounding the device. These parasitic elements are modeled as a four-port network. Closed-form equations are derived for deembedding purposes of this four-port network. The proposed deembedding technique was used to extract small-signal model parameters of a 2×25 μm emitter GaInP/GaAs heterojunction bipolar transistor device, and excellent agreement between measured and model-simulated S-parameter was obtained up to 30 GHz     

Active IMPATT Diode Parameters Obtained by Computer Reduction of Experimental Data

This paper describes a method of determining the junction parameters of an IMPATT device from basic microwave measurements through the use of a computer program. The technique, which evaluates the parasitic without the use of substituted impedances, and the computer program are described. Typical small and large signal results obtained on Ge and Si IMPATT devices are presented.     

Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETs

This paper analyzes the geometry-dependent parasitic components in multifin double-gate fin field-effect transistors (FinFETs). Parasitic fringing capacitance and overlap capacitance are physically modeled as functions of gate geometry parameters using a conformal mapping method. Also, a physical gate resistance model is presented, combined with parasitic capacitive couplings between source/drain fins and gates. The effects of geometrical parameters on FinFET design under different device configurations are thoroughly studied     

基于小信号等效电路模型的SiGe HBT 高频特性模拟分析

给出了fr为15 GHz的SiGe HBT器件的高频小信号等效电路模型;运用微波网络理论,在Matlab软件平台上模拟出器件的S参数和H21参数曲线,模拟结果与实测结果相吻合;根据电路的拓扑结构,分析了管壳封装带来的寄生参数对器件高频性能的影响;根据稳定性判据,计算了器件的稳定性与工作频率之间的关系.为器件的设计和应用提供了理论依据.     

Determination and assessment of the floating-body voltage of SOICMOS devices

A self-consistent method to extract the off-state floating-body (FB) voltage of SOI CMOS devices is presented. The technique is simple and is based on CV and S-parameter measurements of a single standard SOI MOSFET device; no special test structure design is needed. The bias dependent S-parameter measurements of the FB SOI device and its equivalent circuit, along with the CV measurements between the drain and source of the same device, are used to determine the FB voltage. The technique provides reasonable insight on device off-state and leakage performances that are important for digital applications. Additionally, it proposes a method for the extraction of the parasitic source, drain, and gate resistances. Using the technique, FB voltage in excess of 0.4 V is measured in a partially depleted (PD) NMOS device at drain voltage of 2.5 V and zero gate voltage, demonstrating the importance of understanding FB effects on device off-state and junction leakage performances     

Modeling, analysis, and design of RF LDMOS devices usingharmonic-balance device simulation

This paper describes how device simulation may be used for the modeling, analysis, and design of radio-frequency (RF) laterally diffused metal-oxide-semiconductor (LDMOS) transistors. Improvements to device analysis needed to meet the requirements of RF devices are discussed. Key modeling regions of the LDMOS device are explored and important physical effects are characterized. The LDMOS model is compared to dc and small-signal ac measurements for calibration purposes. Using the calibrated model, large-signal accuracy is verified using harmonic distortion simulation, and intermodulation analysis. Predictive analysis and a study of the structure's parasitic components are also presented. Load-pull simulation is used to analyze matching network effects to determine the best choices for device impedance matching     

Study of CDM specific effects for a smart power input protection structure

A Charged Device Model (CDM) specific ESD failure mechanism is discussed for an input protection structure in a smart power technology. The input structure shows unexpected dependency of the CDM robustness on design variations of the input resistor. This paper demonstrates that circuit simulation reproduced the complex failure mechanism accurately after elements like package parameters, substrate resistance, parasitic pn-junctions and the resistance of parasitic physical layers were considered. The importance of accurately modeling these factors for achieving meaningful conclusions for CDM failure mechanisms and CDM robustness from circuit simulation is presented. For validation of the proposed simulation setup, results from circuit simulation are compared to measurements and device simulation.     

Origin and modeling of the frequency dependent output conductancein microwave GaAs MESFET's with buried p layer

This paper presents the results of measurements and modeling of the frequency dependent output admittance of GaAs microwave MESFET's with and without the buried p layer constructions. The output conductance of devices without the buried p layer shows a transition from a low to a higher value typically within the frequency range of 10 Hz-100 Hz at 300 K, and 10 KHz-100 KHz at 367 K. The shape of this transition is determined by the presence of multiple deep levels at the channel-substrate interface, while the magnitude of the higher value of the output conductance is determined by the transconductance of the substrate-controlled parasitic FET. The addition of a buried p layer beneath the channel region results in a parasitic n-p-n bipolar transistor without completely eliminating the parasitic FET action. Results of our study show that the combined effects of these two parasitic transistors on the output conductance of the buried p layer device becomes relatively independent of frequency above 10 Hz at 300 K. However, at higher temperatures the frequency dispersion of the output conductance becomes significant at frequencies above 10 Hz. At low frequencies the parasitic FET causes a very high output capacitance, whereas the parasitic BJT action causes a high negative output capacitance. For the purpose of modeling of the output admittance, this paper indicates how the parameters of the parasitic FET and BJT can be determined by direct measurements on the MESFET's. The paper also suggests how the parameters of these parasitic transistors can be tailored by possible device structural changes, in order to achieve MESFET's with negligible dispersion of output conductance     

A SPICE modeling technique for GaAs MESFET IC's

A vertically integrated device modeling technique for GaAs IC's is presented for use in circuit simulation. Most of the SPICE2 capability can be utilized for modeling the gate transit time and parasitic effects. A computer program has also been developed to extract model parameters from the measured device data.     

On Common–Base Avalanche Instabilities in SiGe HBTs

This paper presents a detailed investigation of the key device-level factors that contribute to the bias-dependent features observed in common-base (CB) dc instability characteristics of advanced SiGe HBTs. Parameters that are relevant to CB avalanche instabilities are identified, extracted from measured data, and carefully analyzed to yield improved physical insight, a straightforward estimation methodology, and a practical approach to quantify and compare CB avalanche instabilities. The results presented support our simple theory and show that CB-instability characteristics are strongly correlated with the parasitic base and emitter resistances. The influence of weak quasi-pinch-in effects are shown to contribute additional complexity to the bias dependence of the CB-instability threshold. Measured data from several technology nodes, including next-generation (300-GHz) SiGe HBTs, are presented and compared. Experimental analysis comparing different device geometries and layouts shows that while device size plays an important role in CB avalanche instabilities across bias, these parameters are not sensitive to standard transistor layout variations. However, novel measurements on emitter-ring tetrode transistor structures demonstrate the influence of perimeter-to-area ratio on CB stability and highlight opportunities for novel transistor layouts to increase .     

The effects of parasitic capacitance on the noise figure of MESFETs

The parasitic capacitance due to the gate pad and the gate feed area of a MESFET plays an important role in the low-noise performance of the device. Its effects on the noise figure have been measured and analyzed for π-FET device geometries. It is shown that there is an optimum unit gate width for the minimum noise figure. This optimum unit gate width depends on the device structure and the processing parameters. When the effects of parasitic capacitances are included, H. Fukui's (1979) equation predicts noise figures that are in good agreement with the experimental data     

AlGaN/GaN 高电子迁移率晶体管解析模型

基于电荷控制理论,考虑到极化效应和寄生漏源电阻的影响,建立了能精确模拟AlGaN/GaN高电子迁移率晶体管直流I-V特性和小信号参数的解析模型.计算表明,自发极化和压电极化的综合作用对器件特性影响尤为显著,2V栅压下,栅长为1μm的Al_0.2Ga_0.8N/GaN HEMT获得的最大漏电流为1370mA/mm;降低寄生源漏电阻可以获得更高的饱和电流、跨导和截至频率.模拟结果同已有的测试结果较为吻合,该模型具有物理概念明确且算法简单的优点,适于微波器件结构和电路设计.     

Edge effects in narrow-width MOSFET's

New results on edge effects in narrow-width MOSFETs as a function of the gate bias are presented. It was found that the value of the effective channel width, the current through the edge region, and the absolute value of the parasitic parallel conductance all increased with gate bias. These parameters were extracted from the experimental measurements by new techniques, which are described     

Smart 3-D Finite-Element Modeling for the Design of Ultra-Low On-Resistance MOSFET

A 3-D electrical finite-element model (FEM) for the design of an ultra-low on-state resistance power MOSFET device is presented. Model building and layer conductivity are discussed to take into account microscopic, technological, and electrical effects, such as metal step coverage and MOS behavior of each elementary cell of the transistor. Model simplifications are also presented to ensure time-efficient simulations. FEM gauging is then achieved, by comparing simulation results to electrical measurements, on devices subjected to top metallization debiasing effects. Simulations show a good agreement with measurements for result errors at less than 2%. The aim of this paper is to provide an accurate estimation of the contribution of parasitic elements such as the shape and number of power bonding wires or top metallization thickness to power device on-state resistance (R_ON). The 3-D electrical FEM is a mandatory first step towards an accurate electrothermal FEM for the design of efficient power products.     

A Theoretical Study of the High-Frequency Performance of a Schottky-Barrier Field-Effect Transistor Fabricated on a High-Resistivity Substrate

The short-circuit admittance parameters for a silicon Schottky-barrier field-effect transistor (SBFET) fabricated on a high-resistivity substrate are calculated from first principles ignoring the effects of minority carriers. The calculations show the maximum frequency of oscillation for a device with a 1-/spl mu/m gate to be 17.9 GHz, neglecting the parasitic associated with the contact metallizations, and 14.7 GHz when the parasitic are included. In order to describe the dynamic behavior of the device, the static properties must first be obtained. The simultaneous solution of Poisson's equation and the continuity equation, both in two dimensions, gives the static charge and potential distribution in the device. The effects of a field-dependent mobility are included in the continuity equation. Using the results of static two-dimensional solutions, a one-dimensional device model is developed that permits the dynamic device behavior to be described by a one-dimensional linear ordinary differential equation. By solving this equation under appropriate boundary conditions, the device y parameters are found as functions of frequency. Calculated results are shown to be in good agreement with published experimental data.     

An analytic method to determine GaAs FET parasitic inductances anddrain resistance under active bias conditions

An analytic technique to determine the parasitic inductances, source resistance, and drain resistance of the FET equivalent circuit is presented in this paper. The method exploits the frequency dependence of the extracted circuit parameters to determine the parasitic inductances and drain resistance from S-parameters measured over frequency for one active bias condition. Given a value for the parasitic gate resistance R _g, all of the other equivalent-circuit parameters are uniquely extracted. The method is fast and robust, making it suitable for in-line statistical process tracking, as well as device modeling. A process tracking example for a 12-wafer 1864-device sample and FET modeling results up to 40 GHz are also presented     

Analysis of width edge effects in advanced isolation schemes fordeep submicron CMOS technologies

The evolution of the active area/isolation transition has resulted in modification of the isolation induced parasitic effects on the device. Based on experimental and simulation results, this paper presents an analysis of the corner parasitic effects induced by an abrupt transition. The substrate bias, transistor length and width dependence of the corner effect Is studied. It is shown that the corner parasitic transistor is less sensitive to short channel and substrate bias effects. The parasitic effect behavior as a function of certain technological parameters is studied by simulating the isolation process. It is demonstrated that certain technological parameters linked to the isolation process must be perfectly controlled for a good integration of future isolation technologies, especially for shallow trench isolation (STI)