Thin film transistors by solution-based indium gallium zinc oxide/carbon nanotubes blend

Solution-based indium gallium zinc oxide (IGZO)/single-walled carbon nanotubes (SWNTs) blend have been used to fabricate the channel of thin film transistors (TFTs). The electrical characteristics of the fabricated devices were examined. We found a low leakage current and a higher on/off currents ratio for TFT with SWNTs compared to solution-based TFTs made without SWNTs. The saturation field effect mobility (μ_sat) of about 0.22 cm²/Vs, the current on/off ratio is ~ 10⁵, the subthreshod swing is ~ 2.58 V/decade and the threshold voltage (V_th) is less than − 2.3 V. We demonstrated that the solution-based blend active layer provides the possibility of producing higher performance TFTs for low-cost large area electronic and flexible devices.     

Amorphous structure and electrical performance of low-temperature annealed amorphous indium zinc oxide transparent thin film transistors

The effect of low-temperature (200 °C) annealing on the threshold voltage, carrier density, and interface defect density of amorphous indium zinc oxide (a-IZO) thin film transistors (TFTs) is reported. Transmission electron microscopy and x-ray diffraction analysis show that the amorphous structure is retained after 1 h at 200 °C. The TFTs fabricated from as-deposited IZO operate in the depletion mode with on-off ratio of > 10⁶, sub-threshold slope (S) of ~ 1.5 V/decade, field effect mobility (μ_FE) of 18 ± 1.6 cm²/Vs, and threshold voltage (V_Th) of − 3 ± 0.7 V. Low-temperature annealing at 200 °C in air improves the on-current, decreases the sub-threshold slope (1.56 vs. 1.18 V/decade), and increases the field effect mobility (μ_FE) from 18.2 to 23.3 cm²/Vs but also results in a V_Th shift of − 15 ± 1.1 V. The carrier density in the channel of the as-deposited (4.3 × 10¹⁶ /cm³) and annealed at 200 °C (8.1 × 10¹⁷ /cm³) devices were estimated from test-TFT structures using the transmission line measurement methods to find channel resistivity at zero gate voltage and the TFT structures to estimate carrier mobility.     

Investigation on indium concentration dependence of solution processed indium tin oxide thin film transistors

The effect of the indium content in indium tin oxide (ITO) films fabricated using a solution-based process and ITO channel thin film transistors (TFTs) was examined as a function of the indium mole ratio. The carrier concentration and resistivity of the ITO films could be controlled by the appropriate treatments. The TFTs showed an increase in the off-current due to the enhanced conductivity of the ITO channel layer with increasing indium mole ratios, producing an increase in the field effect mobility. The characteristics of the a-ITO channel TFT showed the best performance (μ_FE of 3.0 cm² V^− 1 s^− 1, V_th of 2.0 V, and S value of 0.4 V/decade) at In:Sn = 5:1.     

The effect of annealing on amorphous indium gallium zinc oxide thin film transistors

This paper presents the post-annealing effects, caused by rapid thermal annealing (RTA), on amorphous indium gallium zinc oxide (a-IGZO) thin film transistor's (TFT) electrical characteristics, and its contact resistance (R_C) with thermally grown SiO₂ gate dielectric on silicon wafer substrates. The electrical characteristics of two types of TFTs, one post-annealed and the other not, are compared, and a simple model of the source and drain contacts is applied to estimate the R_C by a transmission line method (TLM). Consequently, it has been found that the post-annealing does improve the TFT performances; in other words, the saturation mobility (μ_sat), the on/off current ratio (I_ON/OFF), and the drain current (I_D) all increase, and the R_C and the threshold voltage (V_T) both decrease. As-fabricated TFTs have the following electrical characteristics; a saturation mobility (μ_sat) as large as 0.027 cm²/V s, I_ON/OFF of 10³, sub-threshold swing (SS) of 0.49 V/decade, V_T of 32.51 V, and R_C of 969 MΩ, and the annealed TFTs have improved electrical characteristics as follows; a μ_sat of 3.51 cm²/V s, I_ON/OFF of 10⁵, SS of 0.57 V/decade, V_T of 27.2 V, and R_C of 847 kΩ.     

The effect of metallization contact resistance on the measurement of the field effect mobility of long-channel unannealed amorphous In-Zn-O thin film transistors

The effect of contact resistance on the measurement of the field effect mobility of compositionally homogeneous channel indium zinc oxide (IZO)/IZO metallization thin film transistors (TFTs) is reported. The TFTs studied in this work operate in depletion mode as n-channel field effect devices with a field effect mobility calculated in the linear regime (μ_FE) of 20 ± 1.9 cm²/Vs and similar of 18 ± 1.3 cm²/Vs when calculated in the saturation regime (μ_FE^sat). These values, however, significantly underestimate the channel mobility since a large part of the applied drain voltage is dropped across the source/drain contact interface. The transmission line method was employed to characterize the contact resistance and it was found that the conducting-IZO/semiconducting-IZO channel contact is highly resistive (specific contact resistance, ρ_C > 100 Ωcm²) and, further, this contact resistance is modulated with applied gate voltage. Accounting for the contact resistance (which is large and modulated by gate voltage), the corrected μ_FE is shown to be 39 ± 2.6 cm²/Vs which is consistent with Hall mobility measurements of high carrier density IZO.     

Localization effect of a current-path in amorphous In-Ga-Zn-O thin film transistors with a highly doped buried-layer

The highly-doped buried layer (carrier concentration of ~ 10¹⁹ cm^− 3) in an amorphous indium-gallium-zinc oxide (a-IGZO) channel layer of thin film transistor (TFT) led to dramatic improvements in the performance and prolonged bias-stability without any high temperature treatment. These improvements are associated with the enhancement in density-of-states and carrier transport. The channel layer is composed of Ga-doped ZnO (GZO) and a-IGZO layers. Measurements performed on GZO-buried a-IGZO (GB-IGZO) TFTs indicate enhanced n-channel active layer characteristics, such as V_th, μ_FE, I_off, I_on/off ratio and S.S, which were enhanced to 1.2 V, 10.04 cm²/V·s, ~ 10⁻¹³A, ~ 10⁷ and 0.93 V/decade, respectively. From the result of simulation, a current path was well defined through the surface of oxide active layer especially in GB-IGZO TFT case because the highly-doped buried layer plays the critical role of supplying sufficient negative charge density to compensate the amount of positive charge induced by the increasing gate voltage. The mechanism underlying the high performance and good stability is found to be the localization effect of a current path due to a highly-doped buried layer, which also effectively screens the oxide bulk and/or back interface trap-induced bias temperature instability.     

Copper phthalocyanine thin-film field-effect transistor with SiO2/Ta2O5/SiO2 multilayer insulator

Top-contact Copper phthalocyanine (CuPc) thin-film field-effect transistor (TFT) with SiO₂/Ta₂O₅/SiO₂ (STS) multilayer as the dielectric was fabricated and investigated. With the multi-layer dielectric, drive voltage was remarkably reduced. A relatively large on-current of 1.1 × 10⁻⁷ A at a V_GS of −15 V was obtained due to the strong coupling capability provided by the STS multilayer gate insulator. The device shows a moderate performance: saturation mobility of μ_sat = 6.12 × 10⁻⁴ cm²/V s, on-current to off-current ratio of I_on/I_off = 1.1 × 10³, threshold voltage of V_TH = −3.2 V and sub-threshold swing SS = 1.6 V/dec. Atomic force microscope images show that the STS multilayer has a relative smooth surface. Experiment results indicate that STS multilayer is a promising insulator for the low drive voltage CuPc-based TFTs.     

High-performance amorphous indium-gallium-zinc oxide thin-film transistors with polymer gate dielectric

The fabrication of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with a spin-coated polymer gate dielectric on a glass substrate is reported. The interface state density at the poly(4-vinylphenol)/a-IGZO interface is only around 4.05 × 10¹¹ cm^− 2. The TFTs' threshold voltage, subthreshold swing, on-off current ratio, and carrier mobility are 2.6 V, 1.3 V/decade, 1 × 10⁵, and 21.8 cm²/V s, respectively. These characteristics indicate that the TFTs are suitable for use as nonvolatile memory devices and in flexible electronic applications.     

Transparent amorphous In-Ga-Zn-O thin film as function of various gas flows for TFT applications

The electrical and optical properties of amorphous indium gallium zinc oxide (a-IGZO) films, which can be used as a channel layer, deposited by radio frequency (rf) magnetron sputtering system at room temperature (RT), were investigated as function of various gas flows. The optical transmittance of films deposited under Ar, O₂ / Ar + O₂ and O₂ / Ar-4% H₂ + O₂ atmospheres in the visible wavelength was consistently above 90% at a wavelength of 550 nm at all gas flows, although the film deposited under Ar-4% H₂ atmosphere exhibited a transmittance of below 50%. The carrier concentration and mobility of the a-IGZO films fabricated under Ar and Ar-4% H₂ were observed slight decrease as a function of the flow, respectively. The thin film transistors (TFTs) with an a-IGZO channel deposited under Ar and Ar-4% H₂ atmosphere exhibited the following good characteristics: V_th of 0.34 V, µ_FE of 3.6 cm² V^− 1 s^− 1, on/off ratio of 10⁶, and S value of 0.04 V decade^− 1.     

Optimization of thermoelectric properties on Bi2Te3 thin films deposited by thermal co-evaporation

The optimization of the thermal co-evaporation deposition process for n-type bismuth telluride (Bi₂Te₃) thin films deposited onto polyimide substrates and intended for thermoelectric applications is reported. The influence of deposition parameters (evaporation rate and substrate temperature) on film composition and thermoelectric properties was studied for optimal thermoelectric performance. Energy-dispersive X-ray spectroscopy, X-ray diffraction, X-ray photoelectron spectroscopy and Raman spectroscopy confirmed the formation of Bi₂Te₃ thin films. Seebeck coefficient (up to 250 μV K^− 1), in-plane electrical resistivity (≈10 μΩ m), carrier concentration (3×10¹⁹-20×10¹⁹ cm^− 3) and Hall mobility (80-170 cm² V⁻¹ s^− 1) were measured at room temperature for selected Bi₂Te₃ samples.     

Effect of gallium content on bias stress stability of solution-deposited Ga-Sn-Zn-O semiconductor transistors

We generated solution-processed thin film transistor (TFTs) using gallium tin zinc oxide (GTZO, Ga-Sn-Zn-O) layers as the channel that exhibit improved bias-stress stability during device operation under ambient conditions. The cause of the bias-stress stability was investigated through comparisons with zinc tin oxide (ZTO, Zn-Sn-O)-based TFTs, which suffer red from bias stress instability. Based on in-depth analysis of the electrical characteristics and chemical structure of both GTZO and ZTO layers, it was discovered that the GTZO layers had a significantly lower oxygen vacancy concentration than did the ZTO layer, which influenced the electrical performance of the GTZO transistors as well as their bias-stress stability. When 5 mol% gallium was added, a bias stress-stable transistor was obtained, exhibiting typical semiconductor behavior with a field-effect mobility of 1.2 cm² V^− 1 s^− 1, on/off ratio of 10⁶, off-current of 1 × 10^− 10 A, and threshold voltage of 19.6 V. Further doping of Ga deteriorated the device performance, which was found to be associated with decreased carrier concentration and segregation of an insulating secondary phase.     

Device characteristics improvement of a-In-Ga-Zn-O TFTs by low-temperature annealing

A low-temperature process to improve performances of a-In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) fabricated at room temperature was examined. Two deposition methods, pulsed laser deposition (PLD) and RF magnetron sputtering were employed to deposit the a-IGZO channels. For the PLD case, the TFT characteristics were improved significantly by wet annealing at dew point (d.p.) of 50 °C at the annealing temperature of 200 °C. For the sputtered TFTs, a wider range of annealing temperature from 100 to 200 °C was examined. It was found that annealing at ≥ 150 °C improved the TFT characteristics when dry annealing was employed. On the other hand, wet annealing also improved μ_sat and S values, but very large negative threshold voltage (V_th) shift was observed. These results indicate that the annealing at 150 °C is enough to obtain mobility (μ_sat) as large as 8 cm² Vs^− 1, but annealing temperature as high as 200 °C provides larger μ_sat comparable to those obtained by 400 °C annealing. It is speculated that the large negative V_th shift originates from compensated donors in as-deposited sputtered films.     

Influence of process steps on the performance of microcrystalline silicon thin film transistors

Bottom gate microcrystalline silicon thin film transistors (μc-Si TFT) have been realized with two types of films: μc-Si(1) and μc-Si(2) with crystalline fraction of 80% and close to 100% respectively. On these TFTs we applied two types of passivation (SiN_x and resist). μc-Si TFTs with resist as a passivation layer present a low leakage current of about 2.10^− 12 A for V_G = − 10 and V_D = 0.1V an ON to OFF current ratio of 10⁶, a threshold voltage of 7 V, a linear mobility of 0.1 cm²/V s, and a sub-threshold voltage of 0.9 V/dec. Microcrystalline silicon TFTs with SiN_x as a passivation present a new phenomenon: a parasitic current for negative gate voltage (− 15 V) causes a bump and changes the shape of the sub-threshold region. This excess current can be explained by and oxygen contamination at the back interface.     

High performance self-aligned top-gate ZnO thin film transistors using sputtered Al2O3 gate dielectric

High performance self-aligned top-gate zinc oxide (ZnO) thin film transistors (TFTs) utilizing high-k Al₂O₃ thin film as gate dielectric are developed in this paper. Good quality Al₂O₃ thin film was deposited by reactive DC magnetron sputtering technique using aluminum target in a mixed argon and oxygen ambient at room temperature. The resulting transistor exhibits a field effect mobility of 27 cm²/V s, a threshold voltage of − 0.5 V, a subthreshold swing of 0.12 V/decade and an on/off current ratio of 9 × 10⁶. The proposed top-gate ZnO TFTs in this paper can act as driving devices in the next generation flat panel displays.     

The influence of fabrication process on top-gate thin-film transistors

Amorphous indium zinc oxide (a-IZO) thin-film transistors (TFTs) with bottom- and top-gate structures were fabricated at room temperature by direct current (DC) magnetron sputter in this research. High dielectric constant (κ) hafnium oxide (HfO₂) films and a-IZO were deposited for the gate insulator and the semiconducting channel under a mixture of ambient argon and oxygen gas, respectively. The bottom-gate TFTs showed good TFT characteristics, but the top-gate TFTs did not display the same characteristics as the bottom-gate TFTs despite undergoing the same process of sputtering with identical conditions. The electrical characteristics of the top-gate a-IZO TFTs exhibited strong relationships with sputtering power as gate dielectric layer deposition in this study. The ion bombardment and incorporation of sputtering ions damaged the interface between the active layer and the gate insulator in top-gate TFTs. Hence, the sputtering power was reduced to decrease damage while depositing HfO₂ films. When using 50 W DC magnetron sputtering, the top-gate a-IZO TFTs showed the following results: a saturation mobility of 5.62 cm²/V-s; an on/off current ratio of 1 × 10⁵; a sub-threshold swing (SS) of 0.64 V/decade; and a threshold voltage (V_th) of 2.86 V.     

Room‐Temperature Solution‐Synthesized p‐Type Copper(I) Iodide Semiconductors for Transparent Thin‐Film Transistors and Complementary Electronics

Here, room‐temperature solution‐processed inorganic p‐type copper iodide (CuI) thin‐film transistors (TFTs) are reported for the first time. The spin‐coated 5 nm thick CuI film has average hole mobility (µ_FE) of 0.44 cm² V^?1 s^?1 and on/off current ratio of 5 × 10². Furthermore, µ_FE increases to 1.93 cm² V^?1 s^?1 and operating voltage significantly reduces from 60 to 5 V by using a high permittivity ZrO₂ dielectric layer replacing traditional SiO₂. Transparent complementary inverters composed of p‐type CuI and n‐type indium gallium zinc oxide TFTs are demonstrated with clear inverting characteristics and voltage gain over 4. These outcomes provide effective approaches for solution‐processed inorganic p‐type semiconductor inks and related electronics.     

Amorphous In-Ga-Zn-O thin-film transistor with coplanar homojunction structure

Amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) with a coplanar homojunction structure are demonstrated. The coplanar source and drain regions made of a-IGZO were formed by depositing a hydrogenated silicon nitride (SiN_X:H) layer onto the a-IGZO layer. The a-IGZO regions on which the SiN_X:H layer was directly deposited showed the low resistivity of 4.7 × 10⁻³  Ω cm and degenerated conduction. The fabricated TFT showed excellent transfer and output characteristics with a field-effect mobility of 11 cm² V^− 1 s^− 1, a subthreshold swing of 0.17 V decade^− 1, and an on-to-off current ratio larger than 1 × 10⁹. The width-normalized source-to-drain resistance (R_sdW) calculated using a channel resistance method was 51 Ω cm. This TFT also showed good stability over environment change and under electrical stress.     

Amorphous oxide channel TFTs

Thin film transistors (TFTs) using amorphous oxides of post-transition metals: indium, gallium, and zinc for the channel materials are fabricated with radio-frequency magnetron sputtering methods for the deposition of the channel and the gate insulator layers, at room temperature with no high-temperature post-deposition annealing process. The TFTs operate as n-channel field-effect transistors with various structures of top/bottom gate and top/bottom source-and-drain contact including the inverse-stagger types, and with various materials for the gate insulators, the electrodes, and the substrates. The TFTs having smoother channel interfaces show the better performance at the saturation mobility beyond 10 cm² V^− 1 s^− 1 and the on-to-off current ratio over 10⁸ than the rough channel interfaces. The ring oscillator circuits operate with five-stage inverters of the top-gate TFTs or the inverse-stagger TFTs. Organic light-emission diode cells are driven by a simple circuit of the TFTs. It is also found by a combinatorial approach to the material exploration that the TFT characteristics can be controlled by the composition ratio of the metals in the channel layers. The amorphous oxide channel TFTs fabricated with sputtering deposition at low temperature could be a candidate for key devices of large-area flexible electronics.     

Wet etching rates of InGaZnO for the fabrication of transparent thin-film transistors on plastic substrates

The wet etch process for amorphous indium gallium zinc oxide (a-IGZO or a-InGaZnO) by using various etchants is reported. The etch rates of a-IGZO, compared to another indium-based oxides including indium gallium oxide (IGO), indium zinc oxide (IZO), and indium tin oxide (ITO), are measured by using acetic acid, citric acid, hydrochloric acid, perchloric acid, and aqua ammonia as etchants, respectively. In our experimental results, the etch rate of the transparent oxide semiconductor (TOS) films by using acid solutions ranked accordingly from high to low are IZO, IGZO, IGO and ITO. Comparatively, the etch rate of the TOS films by using alkaline ammonia solution ranked from high to low are IGZO, IZO, IGO and ITO, in that order.Using the proposed wet etching process with high etch selectivity, bottom-gate-type thin-film transistors (TFTs) based on a-IGZO channels and Y₂O₃ gate-insulators were fabricated by radio-frequency sputtering on plastic substrates. The wet etch processed TFT with 30 µm gate length and 120 µm gate width exhibits a saturation mobility of 46.25 cm² V^− 1 s^− 1, a threshold voltage of 1.3 V, a drain current on-off ratio > 10⁶ , and subthreshold gate voltage swing of 0.29 V decade^− 1. The performance of the TFTs ensures the applicability of the wet etching process for IGZO to electronic devices on organic polymer substrates.     

Optical and electrical properties of ZnO films prepared by URT-IP method

Optical and electrical properties were studied on thin polycrystalline ZnO films (200-nm thick) deposited on glass substrates at 200 °C by a DC-arc ion plating method (URamoto-Tanaka-type ion plating method). Effects of the oxygen flow rate (OFR) on film properties were examined. The resistivity of undoped films changed from 4.2×10⁻³ to 9.6×10⁻¹ Ω cm, corresponding to the carrier concentration of 1.0×10²⁰-1.2×10¹⁸ cm⁻³, depending on the increase in OFR from 0 to 40 sccm. The Hall mobility tends to be the maximum value of 28 cm² (V s)⁻¹ at OFR of 10 sccm. Photoluminescence (PL) spectra exhibited a dominant near-band-edge (NBE) emission together with weak PL bands at 2.2 and 3.2 eV. Intensity of NBE was maximum at OFR of 10 sccm. Intensity of the PL band at 2.2 eV increased with increase in OFR. As a result of Ga-doping, the resistivity decreased and the carrier concentration increased by one order of magnitude. The optical transmittance was more than 90% in 400-1200 nm. The ZnO:Ga (3 and 4 wt.% Ga-doped) thin films with the lowest resistivity of 2.6×10⁻⁴ Ω cm, the highest mobility of 25 cm² (V s)⁻¹, and the highest PL intensity were obtained at OFR of 10 sccm. Further increase of OFR led to the decrease in both mobility and PL intensity.