Self-aligned-gate GaInAs microwave MISFET's

A self-aligned-gate GaInAs metal-insulator-semiconductor FET (MISFET) fabrication process that minimizes gate overlap capacitance and offers the potential of achieving submicrometer gate lengths is described. GaInAs MISFETs (1-µm gate length) fabricated with this process have given 0.49-W/mm gate width and corresponding power-added efficiencies of 48 and 39 percent at 4 and 8 GHz, respectively, at a drain voltage of 5.5. V. A small-signal gain of 3.2 dB was obtained at 15 GHz. The estimated carrier velocity was 1.7 × 10⁷cm/s. More recent devices have carrier velocities of 2.5 × 10⁷cm/s and are expected to have improved microwave performance.     

A shallow junction submicrometer PMOS process without hightemperature anneals

A PMOS process resulting in very shallow, low-leakage source-drain junctions without high-temperature annealing following doping is discussed. The doping is performed using gas immersion laser doping which relies on a melt/regrowth process, initiated by a pulsed excimer laser (XeCl, λ=308 nm), to drive in the dopant species. The properties of the resulting source/drain layers are discussed. A significant feature of this process is that unwanted diffusions are eliminated because no high-temperature anneals are used after the doping step. Submicrometer PMOS devices fabricated using this process exhibit excellent short-channel behavior with some process conditions resulting in very little or no threshold-voltage shift down to submicrometer gate lengths     

0.4-µm gate-length devices fabricated by contrast-enhanced lithography

This letter describes the fabrication of submicrometer polysilicon-gate MOS devices by an advanced optical process called contrast enhancement. Functional devices having gate lengths as small as 0.4 µm were fabricated with this process. Contrast-enhanced lithography (CEL) allows usable photoresist patterns to be fabricated at smaller dimensions than is possible with conventional resist. The simultaneous replication of mask dimensions for isolated lines at 0.35 µm and above was achieved in this work using a single exposure on an Optimetrix 10:1 DSW system. Contrast enhancement has been applied to the fabrication of n-channel MOS devices having gate lengths from 0.4 to 1.5 µm in steps of 0.1 µm. Long-channel devices were also fabricated. The transconductance of the 0.4-µm devices is 40 mS/mm at Vds= 5 V. Threshold voltages (Vds= 0) are nearly independent of gate length, ranging from 1.21 to 1.31 V over the 7.5- to 0.4-µm range in gate length. The effective mobility for long-channel devices is 430 cm²/V.s.     

Ultra-shallow high-concentration boron profiles for CMOS processing

The fabrication of ultra-shallow high-concentration boron profiles in silicon has been carried out utilizing a XeCl excimer laser. The Gas Immersion Laser Doping (GILD) process relies on a dopant species, in this case diborane (B2H6), to be adsorbed on the clean silicon surface and subsequently driven in during a melt/regrowth process initiated upon exposure to the short laser pulse. Secondary Ion Mass Spectrometry and spreading resistance profiles show peak boron concentrations from 5 × 10¹⁹cm^-3to 5 × 10²⁰cm^-3depending on the number of laser pulses, with junction depths from 0.08 to 0.16 µm depending on the laser energy. Electrical characteristics show essentially ideal diode behavior following a 10-s 950°C anneal.     

A study of high-speed normally off and normally on Al0.5Ga0.5As heterojunction gate GaAs FET's (HJFET)

The dc, small-signal microwave, and large-signal switching performance of normally off and normally on Al0.5Ga0.5As gate heterojunction GaAs field-effect transistors (HJFET) with submicrometer gate lengths are reported. The structure of both types of devices comprises an n-type 10¹⁷-cm^-3Sn-doped active layer on a Cr-doped GaAs substrate, a p-type 10¹⁸-cm^-3Ge-doped Al0.5Ga0.5As gate layer and a p⁺-type 5 × 10¹⁸-cm^-3Ge-doped GaAs "contact and cap" layer on the top of the gate. The gate structure is obtained by selectively etching the p⁺-type GaAs and Al0.5Ga0.5As. Undercutting of the Al0.5Ga0.5As layer results in submicrometer gate lengths, and the resulting p⁺-GaAs overhang is used to self-align the source and the drain with respect to the gate. Normally off GaAs FET's with 0.5- to 0.7-µm long heterojunction gates exhibit maximum available power gains (MAG) of about 9 dB at 2 GHz. Large-signal pulse measurements indicate an intrinsic propagation delay of 40 ps with an arbitrarily chosen 100-Ω drain load resistance in a 50-Ω microstrip circuit. Normally on FET's with submicrometer gate lengths (∼0.6 µm) having a total gate periphery of 300 µm and a corresponding dc transconductance of 20-30 mmhos exhibit a MAG of 9.5 dB at 8 GHz. The internal propagation delay time measured under the same conditions as above is about 20 ps.     

High-transconductance p-channel AlGaAs/GaAs HFETs with low-energyberyllium and fluorine co-implantation self-alignment

The fabrication and electrical characteristics of p-channel AlGaAs/GaAs heterostructure FETs with self-aligned p⁺ source-drain regions formed by low-energy co-implantation of Be and F are reported. The devices utilize a sidewall-assisted refractory gate process and are fabricated on an undoped AlGaAs/GaAs heterostructure grown by MOVPE. Compared with Be implantation alone, the co-implantation of F⁺ at 8 keV with 2×10¹⁴ ions/cm² results in a 3× increase in the post-anneal Be concentration near the surface for a Be⁺ implantation at 15 keV with 4×10¹⁴ ions/cm². Co-implantation permits a low source resistance to be obtained with shallow p⁺ source-drain regions. Although short-channel effects must be further reduced at small gate lengths, the electrical characteristics are otherwise excellent and show a 77-K transconductance as high as 207 mS/mm for a 0.5-μm gate length     

A gallium arsenide overlapping-gate charge-coupled device

We have developed a new CCD fabrication process for producing an overlapping gate structure which permits submicrometer control of the gap size while using conventional lithography. This process has been used to fabricate four-phase 16-stage Schottky barrier CCD's on GaAs with charge transfer inefficiencies of less than 2 × 10^-4at a 1-MHz clock rate, indicating that charge loss due to potential troughs between the gates has been essentially eliminated. This control of the gap permits the CCD channel to be of submicrometer thickness, which simplifies the integration of CCD's with high-speed devices requiring submicrometer channel thicknesses.     

Submicrometer fully self-aligned AlGaAs/GaAs Heterojunction bipolar transistor

A novel submicrometer fully self-aligned AlGaAs/GaAs heterojunction bipolar transistor (HBT) for reducing parasitic capacitances and resistances is proposed. The fabrication process utilizes SiO2sidewalls for defining base electrode width and separating this electrode from both emitter and collector electrodes. Measured common-emitter current gain β for a fabricated HBT with 0.6 × 10-µm²emitter dimension and 0.7 × 10-µm²× 2 base dimension is 26 at 9 × 10⁴-A/cm²collector current density.     

Optimization of GaAs power MESFET device and material parameters for 15-GHz operation

The results of recent 15-GHz measurements on GaAs power FET's are described. The microwave performance has been determined as a function of epitaxial doping level and thickness, gate recess depth, gate finger width, and source-drain spacing. The optimum values of these parameters for 15-GHz operation are epitaxial doping level approximately 1.6 × 10¹⁷cm^-3, saturated drain current with zero gate voltage in the range 330- to 400-mA/mm gatewidth, gate recess depth between 500 and 1000 Å, gate finger width ≤ 150 µm, and source-drain spacing approximately 5 µm.     

A 64-bit 800-MHz insulated-gate CCD on InP

Sixty-four-bit 259-gate insulated gate buried-channel charge-coupled devices (CCD's) have been fabricated on semi-insulating InP using a planar ion implantation process. These 5-µm gate-length structures, exercised with sinusoidal clocks, have operated to a measurement-limited upper frequency of 800 MHz and exhibited average effective stored charge per unit area in their channels as high as 6 × 10¹²electrons cm^-2. Input-to-output delay-time measurements as a function of frequency clearly indicate proper CCD operation.     

In-situ low energy BF2+ion doping for silicon molecular beam epitaxy

An experimental study of the p-type ion dopant BF2+ in silicon molecular beam epitaxy (MBE) is described. BF2+ was used to dope MBE layers during growth to levels ranging from 1 × 10¹⁶/cm³to 4 × 10¹⁸/cm³over a growth temperature range of 650°C to 1000°C. The layers were evaluated using spreading resistance, chemical etching, and secondary ion mass spectroscopy. Complete dopant activation was observed for all growth temperatures. Remnant fluorine in the epitaxial layer was less than 2 × 10¹⁶/cm³in all cases. Diffused p-n junction diodes fabricated in BF2+-doped epitaxial material showed hard reverse breakdown characteristics.     

Submicrometer poly-Si CMOS fabrication with low-temperature laserdoping

The laser doping process for submicrometer CMOS devices with leakage currents as low as 10^-12 A/μm for both n-channel and p-channel devices is discussed. The I-V characteristics are comparable to those of poly-Si devices fabricated using ion implantation and high-temperature annealing processes. The laser-induced melting of predeposited impurity doping (LIMPID) process was used to fabricate submicrometer polycrystalline-Si CMOS devices. This process uses a very low temperature, so no dopant atom can diffuse along the grain boundaries in the solid region. The use of stacked Al/SiO₂ films as a protection layer made it possible to reduce the leakage current from several tens of picoamperes per micrometer to 1 pA/μm     

Characterization of InGaAs/AlGaAs pseudomorphic modulation-doped field-effect transistors

High-performance pseudomorphic InyGa1-yAs/Al0.15- Ga0.85As (0.05 le y le 0.2) MODFET's grown by MBE have been characterized at dc (300 and 77 K) and RF frequencies. Transconductances as high as 310 and 380 mS/mm and drain currents as high as 290 and 310 mA/mm were obtained at 300 and 77 K, respectively, for 1-µm gate lengths and 3-µm source-drain spacing devices. Lack of persistent trapping effects,I-Vcollapse, and threshold voltage shifts observed with these devices are attributed to the use of low mole fraction AlxGa1-xAs while still maintaining 2DEG concentrations of about 1.3 × 10¹²cm^-2. Detailed microwave S-parameter measurements indicate a current gain cut-off frequency Of 24.5 GHz Wheny = 0.20, which is as much as 100 percent better than similar GaAs/AlGaAs MODFET structures, and a maximum frequency of oscillation of 40 GHz. These superior results are in part due to the higher electron velocity of InGaAs as compared with GaAs. Velocity field measurement performed up to 3 kV/cm using the magnetoresistance method indicates an electron saturation velocity of greater than 1.7 × 10⁷cm/s at 77 K fory = 0.15, which is 20 percent higher than GaAs/AlGaAs MODFET's of similar structure.     

Studies on an In0.53Ga0.47As/In0.52Al0.48As single-quantum-well quasi-MISFET

We describe here the properties of a novel InGaAs/ InAlAs quasi-MISFET in which an inverted modulation-doped single quantum well forms the channel and an undoped semi-insulating InAlAs constitutes the gate barrier. The entire structure is grown lattice-matched to InP continuously by molecular-beam epitaxy in a single step. Rapid thermal annealing of implanted semiconductors and ohmic contacts have been investigated and have been used successfully in the fabrication of the MISFET's. Improved performance is obtained with the incorporation of Ti in the source-drain metallization, with which contact resistances as low as 0.1 ω . mm are measured. Charge-control modeling of the proposed device predicts the carrier concentration in the channel region fairly well at room temperature. A quantum mechanical modeling of the device in the effective mass approximation also has been done. The thickness of the InAlAs doping layer is found to be an important parameter that controls the device turn-on characteristics. The velocity-field characteristics of the two-dimensional channel electrons were measured by pulse current-voltage and pulsed Hall techniques. The maximum velocities measured at 300 and 77 K are 1.5 × 10⁷and 1.7 × 10⁷cm/s, respectively. Fairly high electron mobilities are measured in single-quantum-well MISFET structures even with well thicknesses as small as 100 Å. The InAlAs gate barrier is effective in reducing the gate leakage current. Gate leakage currents are reduced further with a composite dielectric consisting of oxidized Al and InAlAs. An extrinsic transconductance of 310 mS/mm is measured in a 1.0-µm gate device at 300 K. A value of fT= 32 GHz, measured in a 1.0-µm device, is the best obtained so far with this material system. It is expected that submicrometer gate lengths will lead to even better performance.     

γ—Radiation effects on MOSFET's fabricated with NMOS Submicrometer technology

In this letter, we report γ-radiation effects on MOSFET's fabricated with NMOS submicrometer technology. We have investigated the radiation sensitivity of n-channel MOSFET's with Leffvarying from 6 to 0.3 µm and with a gate oxide thickness of 250 Å. We observed that, for radiation doses ≤ 10⁴rad's, the threshold voltage shift is less than 75 mV and this shift is independent of the device geometry (even for Leff= 0.3 µm). A comparision has also been made between TaSi2gate MOSFET's and poly-gate MOSFET's. The deposition of TaSi2on poly/oxide/silicon structure does not decrease the radiation sensitivity of these MOSFET's. We have also compared MOSFET's fabricated with X-ray lithography and optical lithography. The X-ray lithography does not have a significant effect on the radiation sensitivity of these MOSFET's.     

1 µm MOSFET VLSI technology: Part VIII—Radiation effects

In this paper the effect of electron-beam radiation on polysilicon-gate MOSFET's is examined. The irradiations were performed at 25 kV in a vector scan electron-beam lithography system at dosages typical of those used to expose electron-beam resists. Two types of studies are reported. In the first type, devices fabricated with optical lithography were exposed to blanket electron-beam radiation after fabrication. In the second, discrete devices from a test chip, fabricated entirely with electron-beam lithography, were used. It is shown that in addition to the threshold voltage shift, caused by the accumulation of radiation-induced positive charge in the gate oxides, these charged centers and additional uncharged (neutral) electron traps lead to an increase in the electron trapping in irradiated oxides. Temperatures above 550°C are shown to be required to anneal both the positive and neutral traps completely from the oxide underlying polysilicon after exposure to radiation. Annealing of the radiation-induced positive charge from the oxide is shown to depend on the metallurgy overlying the gate insulator during heat treatment. Annealing treatments which remove the charged centers from aluminum-gated MOS structures are demonstrated to leave small (about 5 × 10¹⁰cm^-2) but significant amounts of charge in certain polysilicon-gate structures. The dependence of positive and neutral trap densities on direct electron-beam exposure was studied in the range between 10 and 200 µC/cm². Studies on the electron-beam fabricated devices indicate that indirect exposure of the gate oxide by electrons scattered from the primary beam during lithography in areas away from the gate oxide is sufficient to cause appreciable damage. After postmetal annealing at 400° C for 20 min, the minimum residual charge density found in the electron-beam fabricated devices is 4 × 10¹⁰cm^-2.     

A CV technique for measuring thin SOI film thickness

A technique is developed to measure silicon-on-insulator (SOI) silicon device film thickness using a MOSFET. The method is based on CV measurements between gate and source/drain at two different back-gate voltages. The SOI devices used in this study were n⁺ polysilicon gate n-channel MOSFETs fabricated with modified submicrometer CMOS technology on SIMOX (separation by implanted oxygen) wafers. The SIMOX wafers were implanted with a high dose of oxygen ions (10¹⁸ cm^-2) at 200 keV and subsequently annealed at 1230°C. The NMOS threshold boron implant dose is 2×10¹² cm^-2. This method is simple, nondestructive, and no special test structure is needed. Using this technique, SOI film thickness mapping was made on a finished wafer and a thickness variation of ±150 Å was found     

Dependence of GaAs power MESFET microwave performance on device and material parameters

The results of recent X-band measurements on GaAs Power FET's are described. These devices are fabricated with a simple planar process and at least 1-W output power at 9 GHz with 4-dB gain has been obtained from more than 25 slices having carrier concentrations in the range 5 to 15 × 10¹⁶cm^-3. The highest output powers observed to date are 1.0 W at 11 GHz and 3.6 W at 8 GHz with 4-dB gain. Devices have had up to 46-percent power-added efficiency at 8 GHz. The fabrication process is briefly described and the factors contributing to the high output powers reported here are discussed. Some of these factors are epitaxial carrier concentration near 8 × 10¹⁶cm^-3, good device heatsinking, and low parasitic resistance. The observed dependence of microwave performance on total gate width, gate length, pinchoff voltage, epitaxial doping level, etc., is described.     

Reverse short-channel effects on threshold voltage in submicrometersalicide devices

A reverse short-channel effect on threshold voltage caused by the self-aligned silicide process in submicrometer MOSFETs is reported. A physical model of lateral channel dopant redistribution due to the salicide process is proposed. The injection of vacancies and lattice strain during TiSi₂ formation causes defect-enhanced boron diffusion which results in a nonuniform lateral channel dopant redistribution and hence a threshold increase in short-channel devices. In addition to the small gate edge birds beak and the nonuniform oxidation-enhanced diffusion (OED) redistribution of channel dopant due to the polysilicon gate reoxidation, the self-aligned Ti silicide process can be major cause of the observed reverse short-channel effect in submicrometer MOSFET devices     

Observation of reduced boron penetration and gate depletion forpoly-Si0.8Ge0.2 gated PMOS devices

Poly-Si_0.8Ge_0.2-and poly-Si-gated PMOS capacitors with very thin gate oxides were fabricated. Boron penetration and poly-gate depletion effects (PDE) in these devices were both analyzed. Observations of smaller flat-band voltage shift and superior gate oxide reliability suggest less boron penetration problem in poly-Si _0.8Ge_0.2-gated devices. Higher dopant activation rate, higher active dopant concentration near the poly/SiO₂ interface and therefore improved PDE were also found in boron-implanted poly-Si_0.8Ge_0.2-gated devices as compared to poly-Si-gated devices. A larger process window therefore exists for a poly-Si_0.8Ge_0.2 gate technology with regard to the tradeoff between boron penetration and poly-gate depletion