New pin MOSFET structure for hot carrier suppression

As an alternative to lightly doped drain (LDD) structures, a new pin MOSFET structure has been developed with near-intrinsic doping in the channel near the source/drain ends. This new structure has better hot carrier suppression, current drive capability and short channel effects compared to LDD MOSFETs     

A time-dependent technique for carrier recombination and generation lifetime measurement in SOI MOSFET

A time-dependent technique is developed for carrier recombination–generation (R–G) lifetimes measurement in the silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET). One gate is kept in strong accumulation, and the other gate is kept in strong inversion. A ramp voltage is applied to the accumulated gate, and the drain current transients are monitored for both carrier R–G lifetimes extraction. The time-dependent technique shows an extensive applicability, and its credibility is proved by simulation.     

A lifetime prediction method for hot-carrier degradation insurface-channel p-MOS devices

Hot carrier degradation of p-MOS devices at low gate voltages (V_g<V_d) is examined. It is shown that the electronic gate current is the principal factor in stress damage in this gate voltage range and that the damage itself consists of trapped electrons, localized close to the drain junction. The saturation of the transconductance change as a function of time which is seen at long stress times of high stress voltages results from a change in the injected gate current as a function of time. This is caused by changes in electric field in the silicon due to charge trapping in the oxide during stress. The saturation effect can, however, be transformed into a simple power law if the time axis is multiplied by the square of the instantaneous gate current. This allows for the development of a lifetime-prediction method. The method is applied to 1.0-μm p-MOS devices, and a lifetime is estimated     

Experimental verification of the usefulness of the nth power law MOSFET model under hot carrier wearout

In this paper the usefulness of the nth power law MOSFET model under Hot Carrier Injection (HCI) wearout has been experimentally demonstrated. In order to do that, three types of nFET transistors have been analyzed under different HCI conditions and the nth power law MOSFET model has been extracted for each sample. The results show that the model can reproduce the MOSFET behavior under HCI wearout mechanism. Therefore, the impact of HCI on circuits can be analyzed by using the nth power law MOSFET model.     

Electrical parameters degradation law of MOSFET during ageing

A new method to extract the different electrical parameters lifetime of MOS transistors submitted to hot carriers degradation is proposed. This method leads to error on the lifetime below 15%, even if the parameter variation measurement reaches only 8%. The robustness of this method has been tested for various biases of stress and different technologies representative of different ageing mechanisms. Finally this method is a good indicator of the degradation modes occurring during the stress.     

Hot carrier degradation for narrow width MOSFET with shallow trench isolation

We have investigated the hot carrier reliability characteristics of narrow width MOSFET with shallow trench isolation. In the case of maximum substrate current condition, the lifetime of nMOSFET is slightly degraded by decreasing the device width. However, a significant degradation of device lifetime of the narrow width device was observed under channel hot electron condition (V_g=V_d). In the case of pMOSFET, we also found enhanced degradation of narrow width device under channel hot electron condition. Enhanced degradation of MOSFETs can be explained by both the current crowding and enhanced charge trapping at the shallow trench isolation edge. Considering pass transistor in DRAM cell, the degradation of lifetime for narrow width device under high gate bias condition causes a significant impact on circuit reliability.     

A high resolution method for measuring hot carrier degradation in matched transistor pairs

A new measurement methodology has been developed in order to perform high-resolution measurements of the hot carrier degradation on MOSFET's. With this methodology, degradations as low as 0.01% can be measured accurately. The high resolution measurements are necessary for measuring hot carrier degradation in matched transistor pairs. This is demonstrated by comparing the degradation at different stress conditions. A linear extrapolation is not applicable when extrapolating the degradation curves from 1 % to 100 ppm.     

Anomalous hot carrier degradation of nMOSFET's at elevatedtemperatures

An anomalous behavior of nMOSFET's hot carrier reliability characteristics has been investigated at an elevated temperature for the first time. Although the degradation of linear drain current is significantly reduced with increasing stress temperature, the degradation of saturation drain current is enhanced for high temperature stress. This behavior can be explained by the reduction of the velocity saturation length at an elevated temperature, which increases the net amount of interface states that can influence the channel current. This anomalous behavior causes a significant impact on the device reliability for future deep submicrometer devices at high operating temperatures     

Channel width dependence of NMOSFET hot carrier degradation

The channel width dependence of hot carrier reliability on NMOSFETs from 0.4-/spl mu/m to 0.13-/spl mu/m technology has been studied at both I/sub b,peak/ and V/sub g/ = V/sub d/ conditions. Enhanced degradation on narrow width devices happens on most technologies. The I/sub b//I/sub d/ value and vertical electric field are proposed to be the reasons for enhanced degradation on narrow width NMOSFETs.     

A physical alpha-power law MOSFET model

A new compact physics-based alpha-power law MOSFET model is introduced to enable projections of low power circuit performance for future generations of technology by linking the simple mathematical expressions of the original alpha-power law model with their physical origins. The new model, verified by HSPICE simulations and measured data, includes: 1) a subthreshold region of operation for evaluating the on/off current tradeoff that becomes a dominant low power design issue as technology scales, 2) the effects of vertical and lateral high field mobility degradation and velocity saturation, and 3) threshold voltage roll-off. Model projections for MOSFET CV/I indicate a 2X-performance opportunity compared to the National Technology Roadmap for Semiconductors (NTRS) extrapolations for the 250, 180, and 150 nm generations subject to maximum leakage current estimates of the roadmap. NTRS and model calculations converge at the 70 nm technology generation, which exhibits pronounced on/off current interdependence for low power gigascale integration     

Concurrent PBTI and hot carrier degradation in n-channel MuGFETs

The experimental investigations on the concurrent PBTI and CHC degradation in n-channel MuGFETs have been performed with different stress gate voltages, gate lengths, fin widths, and side surface orientations of fin body. The observed results suggest that the enhanced hot carrier degradation at elevated temperature is due to the interaction between PBTI and CHC degradation. The stress gate voltage is a dominant role in CHC degradation at elevated temperature. The device degradation is independent of the fin number and fin width when the total fin width is constant. The device degradation is more significant in 0° rotated fin body than in 45° rotated fin body.     

Investigation of hot carrier degradation in asymmetric nDeMOS transistors

Hot carrier degradation in asymmetric nDeMOS transistors is investigated in this paper. It is found that the worst case hot carrier stress condition in asymmetric nDeMOS transistors is at I_g,max, and not at I_b,max and hot-electron injection (HE, i.e. V_gs = V_ds). Further, the damage regions in transistors upon various hot carrier stress modes are located by using variable amplitude charge pumping technique. It is found that the interface traps generation in the gate/n-type graded drain (NGRD) overlap and spacer/NGRD regions is the dominant mechanism of hot carrier degradation in transistors upon I_g,max stress mode. Moreover, both the interface trap generation and the electron trapping are two important factors to induce the electrical parameters shifts of asymmetric nDeMOS transistors under I_b,max and HE stress.     

A comprehensive study of hot carrier stress-induced drain leakagecurrent degradation in thin-oxide n-MOSFETs

The mechanisms and characteristics of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs are investigated. Both interface trap and oxide charge effects are analyzed. Various drain leakage current components at zero V_gs such as drain-to source subthreshold leakage, band-to-band tunneling current, and interface trap-induced leakage are taken into account. The trap-assisted drain leakage mechanisms include charge sequential tunneling current, thermionic-field emission current, and Shockley-Read-Hall generation current. The dependence of drain leakage current on supply voltage, temperature, and oxide thickness is characterized. Our result shows that the trap-assisted leakage may become a dominant drain leakage mechanism as supply voltage is reduced. In addition, a strong oxide thickness dependence of drain leakage degradation is observed. In ultra-thin gate oxide (30 Å) n-MOSFETs, drain leakage current degradation is attributed mostly to interface trap creation, while in thicker oxide (53 Å) devices, the drain leakage current exhibits two-stage degradation, a power law degradation rate in the initial stage due to interface trap generation, followed by an accelerated degradation rate in the second stage caused by oxide charge creation     

New hot-carrier degradation mode and lifetime prediction method inquarter-micrometer PMOSFET

Hot-carrier-induced device degradation has been studied for quarter-micrometer level buried-channel PMOSFETs. It was found that the major hot-carrier degradation mode for these small devices is quite different from that previously reported, which was caused by trapped electrons injected into the gate oxide. The new degradation mode is caused by the effect of interface traps generated by hot hole injection into the oxide near the drain in the saturation region. DC device lifetime for the new mode can be evaluated using substrate current rather than gate current as a predictor. Interface-trap generation due to hot-hole injection will become the dominant degradation mode in future PMOSFETs     

A study of hot carrier degradation in NMOSEET's by gate capacitanceand charge pumping current

Hot carrier degradation in n-channel MOSFET's is studied using gate capacitance and charge pumping current for three gate stress voltages: V_g~V_b, V_d/2, V_d. The application of these two sensitive techniques reveals new information on the types of trap charges and the modes of degradation. At low V_g stress near threshold voltage, the fixed charge is attributed to holes. For high V_g stress, the fixed charge is predominantly electrons. Data for mid V_g stress suggest little net fixed charge trapping. Interface traps are observed for all stress conditions and are demonstrated from differential gate capacitance spectra to exhibit both donor and acceptor trap behavior. Mid V_g stress is shown to result in the highest density of interface traps. These traps can be annealed to a large extent for temperatures up to 300°C. A post-stress generation of interface traps is observed at low V_g stress, in agreement with recent observation. Further, a linear relation is found to exist between the change in overlap gate capacitance and the increase in peak charge pumping current, and suggests spatial uniformity in the degradation of the interface     

A mobility model for submicrometer MOSFET simulations includinghot-carrier-induced device degradation

The model presented includes the quantum effects of electrons in the inversion layer proposed by S.A. Schwarz and S.E. Russek (1983) and the surface scattering effects due to the interfacial charges. By comparison with experimental data from scaled MOSFETs, the limitation of K. Yamaguchi's (1983) mobility model in submicrometer device simulations is implied, while the quantum channel broadening effects have been proven significant in turn. In addition, it is shown that the modeling of the screening effect of Coulomb scattering plays an important role in simulating the hot-carrier-induced MOSFET degradation. The model can predict the current-voltage characteristics within 5% accuracy for scaled MOSFETs down to 0.5-μm, as well as the degradation of electrical characteristics due to hot-carrier effects for submicrometer MOSFETs     

Study of the impact of hot carrier injection to immunity of MOSFET to electromagnetic interferences

This paper presents an original study about the effect of hot carrier injection stress on the DC offsets induced by electromagnetic interferences (EMI) on a nanometric NMOS transistor, which is one of the major sources of failures in analog circuits. Measurements and simulations based on a simple model (Sakurai–Newton model) of fresh and stressed transistors are presented and show significant variations of EMI-induced DC shifts of drain current.     

Assessment of oxide reliability and hot carrier degradation in CMOS technology

The techniques and methodologies to be applied in R&D laboratories for the assessment of thin gate dielectrics reliability and hot carrier degradation are reviewed. Examples are given on how the application of these techniques allows to obtain a better insight in the physics of the degradation process. Two such examples are given related to the Dielectric breakdown of thin gate dielectrics and on the Stress-Induced Leakage Current in thin dielectrics.