Dual-loop DLL-based clock synchroniser

A clock synchronisation scheme based on a newly proposed dual-loop delay locked loop (DLL) is presented. The proposed scheme incorporates analogue and digital DLLs to align phases of two different frequency clocks. Simulation results show that the internal clock can be synchronised to the reference clock by tracking the dual feedback loop. The whole circuit design was implemented using 0.35 μm CMOS technology. Power dissipation is ~42 mW with a single 3.3 V supply     

Resynchronising delay-locked loop

The delay-locked loop (DLL) is a device that is often used for PN-code tracking to synchronise direct sequence spread spectrum (DS-SS) systems. A DLL with resynchronising capability, which is more robust against loss of lock, is presented. The new scheme has two modes: a normal tracking mode and a resynchronising mode. The structure of the new loop and its function are described     

Low-voltage pulsewidth control loops for SOC applications

The proposed pulsewidth control loop (PWCL) adopts the same architecture as the conventional PWCL, but with a new duty-cycle detector and a new pulse generator. Using the new building block circuits, the clock frequency can be increased tremendously, and the output of the PWCL has fixed rising edge, which will not disturb the phase-locking result by a preceding phase-locked loop (PLL) or delay-locked loop (DLL). This means that the clock buffer can include a PLL/DLL and a PWCL to perform phase locking as well as pulsewidth adjustment simultaneously. All the building blocks used in the new PWCL have simple circuit structures that are suitable for low-voltage operation. A test chip is implemented in a 0.35-/spl mu/m CMOS process with only 1.8-V V/sub DD/ successfully generates a clock signal with a 0.6-ns pulsewidth for a heavily pipelined multiplier to operate at 400 MHz. The features of operating at low voltage, providing variable duty cycle, and being able to cooperate with PLL/DLL make the new PWCL suitable for system-on-chip (SOC) applications.     

延迟锁定环路的大步进快速捕获

本文提出一种新的延迟锁定环路的大步进快速捕获方法，主要解决目前尚未很好解决的低信噪比长序列伪随机码的快速捕获问题。文中讨论了在步进快速捕捕获延迟锁定环路的原理与实现，分析了这种环路的平均捕获时间，解扩相关器的输出成分及大步进搜索时的虚警与检测概率。     

可实现快速锁定的FPGA片内延时锁相环设计

延时锁相环（DLL）是一种基于数字电路实现的时钟管理技术。DLL可用以消除时钟偏斜,对输入时钟进行分频、倍频、移相等操作。文中介绍了FPGA芯片内DLL的结构和设计方案,在其基础上提出可实现快速锁定的延时锁相环OSDLL设计。在SMIC0．25μm工艺下,设计完成OSDLL测试芯片,其工作频率在20-200MHz,锁定时间相比传统架构有大幅降低。     

Design-for-testability for embedded delay-locked loops

This paper introduces a new approach to testing a basic analog-only delay-locked loop (DLL) that is embedded in a field-programmable gate array, an application specific integrated circuit, or a system-on-chip (SoC). Part of the DLL circuitry is duplicated and then connected to the DLL in a way that produces a replica of the control voltage. This shadow of the control voltage is used to measure the loop's response to a step in phase. The concept of test construct (TC) gain is introduced as a means of improving detectability. The benefit of the testing approach is demonstrated by injecting defects into the DLL and detecting them through the TC at the observation point.     

The Generalized Delay-Locked Loop

The delay-locked loop (DLL) is a synchronization device that is widely used for PN-code tracking in spread spectrum systems. The error detector characteristic (S-curve) of the DLL has a major impact on the performance. Using more than two correlators will extend the tracking range of the S-curve. The Generalized DLL (GenDLL) theory provides a concept to analyze a large class of DLL configurations including the classical DLL. The focus of the performance criteria is on tracking jitter and the mean time to lose lock (MTLL). It is shown that the MTLL can be considerably improved by using extended S-curves. However, the tracking jitter is increased by additional correlators. The tradeoff between the two criteria is explained. With the GenDLL theory loop configurations can be designed having both low tracking jitter and high loop robustness against loss of lock.     

A 250-622 MHz deskew and jitter-suppressed clock buffer usingtwo-loop architecture

A 250-622 MHz clock buffer has been developed, using a two-loop architecture: a delay-locked loop (DLL) for deskew, and a frequency-locked loop (FLL) for reference frequency supply to the DLL. The DLL incorporates a current-mode phase detector which utilizes a flip-flop metastability to detect a phase difference in the order of 20 ps. A measured jitter is suppressed to less than 40 ps RMS over the operating frequency range. A DLL acquisition time of 150 ns typical is simulated at 400 MHz. A 0.4-μm CMOS technology is used to fabricate the chip     

Noncoherent delay-lock tracking loop for chip-interleaving DS SSsystem

A noncoherent delay-lock loop (DLL) is proposed for code tracking in chip-interleaving (CI) direct sequence (DS) spread spectrum (SS) systems. Analyses show that the proposed loop achieves the same code-tracking performance as the traditional noncoherent DLL does for conventional DS SS systems     

A dual-loop delay-locked loop using multiple voltage-controlleddelay lines

This paper describes a dual-loop delay-locked loop (DLL) which overcomes the problem of a limited delay range by using multiple voltage-controlled delay lines (VCDLs). A reference loop generates quadrature clocks, which are then delayed with controllable amounts by four VCDLs and multiplexed to generate the output clock in a main loop. This architecture enables the DLL to emulate the infinite-length VCDL with multiple finite-length VCDLs. The DLL incorporates a replica biasing circuit for low-jitter characteristics and a duty cycle corrector immune to prevalent process mismatches. A test chip has been fabricated using a 0.25-μm CMOS process. At 400 MHz, the peak-to-peak jitter with a quiet 2.5-V supply is 54 ps, and the supply-noise sensitivity is 0.32 ps/mV     

Convergence characteristic of delay-lock loop in multipathenvironment

The delay-lock loop (DLL) is utilised to recover the synchronising signal of the PN code in CDMA systems. However, few papers wholly illustrate the convergence characteristics of the DLL in multipath cases; this problem is studied by the authors. Theoretical analysis and simulation show that the DLL would lock at a point that is the linear combination of the different delays of each multipath signal, weighted by its power level. Therefore, there is an inherent error in the DLL in multipath environments     

一种用于DS-CDMA基站的全数字非相干延迟锁相环

本文根据直接序列扩频码分多址(DS-CDMA)系统上行链路伪随机码跟踪的特点,给出并分析一种全数字非相干延迟锁相环 (DLL),该DLL采用了二元鉴相和数字序贯滤波的实现结构。文中推导了多用户环境下环路的数学模型及鉴相误差统计特性,给出了跟踪性能的计算机仿真结果。研究结果表明,本文给出的DLL能以小的复杂度实现良好的跟踪性能,具有较高的应用价值。     

Low-jitter multi-phase digital DLL with closest edge selection scheme for DDR memory interface

A multi-phase digital delay-locked loop (DLL) capable of a low-jitter feature for DDR memory interface is reported. The DLL repeatedly selects the output clock edge which is closest to the reference clock edge to reduce the total jitter. A test chip was fabricated in a 0.18 mm CMOS process to verify its functionality. The measured RMS and peak-to-peak jitter of the DLL are 6.2 and 20.4 ps, respectively. The power consumption of the DLL is 12 mW from a 1.8 V supply voltage.     

A semi-digital delay-locked loop using an analog-based finite state machine

This brief describes a low-power full-rate semi-digital delay-locked loop (DLL) architecture using an analog-based finite state machine (AFSM) and a polyphase filter. The AFSM architecture uses low-power analog blocks to map high-frequency loop feedback information to low frequency, thus reducing the total power required for digital signal processing and for the macro as a whole. The polyphase filter generates full-rate multiphase outputs for a phase rotator, hence a reference clock of the semi-digital DLL can be generated by any reference source including a phase-locked loop with an LC voltage-controlled oscillator. The prototype semi-digital DLL in 0.12-/spl mu/m CMOS exhibits less than 10/sup -12/ bit error rate at 3.2 Gb/s consuming 60 mW.     

A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces

A DLL featuring jitter reduction techniques for a noisy environment is described. It controls a loop response mode by monitoring the magnitude of input jitter caused by supply noise. This technique varies the probability of phase error tracking. It reduces the output jitter of the DLL due to a low effective variance of input phase error and a narrow effective loop bandwidth. The DLL is implemented in a 0.13 $muhbox{m}$ CMOS process. Under noisy environments, the output clock of 1 GHz has 4.58 ps RMS and 29 ps peak-to-peak jitter.      

1064 nm, 565 Mbits/s PSK transmission experiment with homodyne receiver using synchronisation bits

An optical 565 Mbit/s transmission system at 1064 with phase shift keying and homodyne detection using a new carrier recovery technique is presented. The phase error signal in the receiver is obtained by means of synchronisation bits. This method combines the advantages of the Costas loop with the simplicity of the pilot carrier technique.<>     

基于延迟锁相环的到达时间估计算法

超宽带脉冲信号具有高时间分辨能力,能达到厘米级的定位精度。目前,脉冲超宽带测距定位系统中普遍采用基于能量检测的非相关到达时间(TOA)估计算法的性能通常受限于阈值门限和估计偏差。该文在原先锁相环方案基础之上引入延时迟支路和衰减因子,提出了一种易于实现的基于延迟锁相环的TOA估计算法。通过在迟支路中设置不同的衰减因子,仿真结果表明,在IEEE802.15.4a4种信道模型CM1~CM4中,新算法均能有效提升测距定位精度,即缩短了首达路径与锁相环稳态锁定点之间的时差,其估计偏差最低可降至原有方案的1/10。     

A Multiphase-Output Delay-Locked Loop With a Novel Start-Controlled Phase/Frequency Detector

This paper presents a multiphase-output delay-locked loop (MODLL). The proposed phase/frequency detector (PFD) utilizes a new NAND-resettable dynamic D-flip-flop (DFF) circuit to achieve a shorter reset path. Thus, lower power consumption and higher speed can be obtained. The proposed voltage-controlled delay element used in this design can operate at a lower supply voltage and overcome the dead-band issue of the voltage-controlled delay line. An experimental multiphase-output DLL was designed and fabricated using a TSMC 0.35-$mu$m 2P4M CMOS process. The delay-locked loop (DLL) power consumption is 3.4 mW with a 2 V supply and a 100 MHz input. The measured rms and peak-to-peak jitters are 17.575 ps and 145 ps, respectively. In addition, the supply voltage of the experimental multiphase-output DLL can vary from 1.5 V to 2.5 V without causing malfunctions. The active area is 426 $mu$m $times$ 381 $mu$m.      

采用可复位延迟链形成无谐波、快速锁定的延迟锁相环

为提高锁定速度,一种带单步复位（RES）延迟链的全数位延迟锁相环（ADDLL）得以发展。随着新的可复位技术的发展,DLL快速锁定和无谐波的特点逐渐显现。主要在常见的DLL电路中加入可复位延迟链,采用SI MC 180 nmCOMS工艺,并采用Synopsys的HSI M仿真器对电路进行仿真。仿真结果显示,改进的DLL工作频率范围可达50～250 MHz,锁定时间明显减小,且无谐波信号。     

Analysis of DLL Jitter due to Voltage-Controlled Delay Line

In this paper we analyze jitter in a delay-locked loop (DLL) due to uncertainties in the voltage-controlled delay line (VCDL). To obtain a closed-form equation for jitter in the DLL, time-domain equations of the DLL are used. The jitter at the intermediate stages of the VCDL and the jitter of a conventional delay cell are analyzed. The simulation results show that the jitter of the DLL due to mismatch of the delay cells is zero at the beginning and end of the VCDL and is highest at the middle of the VCDL. Also, a DLL is designed in TSMC 0.18 μm CMOS technology to show the accuracy of the proposed analytical method.