基于90nm CMOS工艺的2GS/s 8-bit 折叠插值ADC的设计*

本文基于90nm CMOS工艺设计了一个单通道 2GSPS, 8-bit 折叠插值模数转换器。本设计采用折叠级联结构,通过在折叠电路间增加级间采样保持器的方法增加量化时间。电路中采用了数字前台辅助校正技术以提高信号的线性度。后仿结果表明,在奈奎斯特采样频率,该ADC的微分非线性DNL<±0.3LSB,积分非线性INL<±0.25LSB,有效位数达到7.338比特。包括焊盘在内的整体芯片面积为880×880 μm2。电路在1.2V 电源电压下功耗为210mW.     

A 1-V 1.25-GS/S 8-Bit Self-Calibrated Flash ADC in 90-nm Digital CMOS

We present an 8-bit 1.25-GS/s flash analog-to-digital converter (ADC) in 90-nm digital CMOS with wide analog input bandwidth and low power dissipation. The ADC employs two key techniques: a self-biased track-and-hold amplifier which enhances the ADC full-scale voltage and enables the converter operating under a single 1-V supply; and an improved calibration scheme based on reference pre-distortion to enhance the ADC linearity without sacrificing its sampling speed. The prototype converter thus achieves 7-, 6.9-, 6.5–bit ENOB at 1.25 GS/s for input signal frequencies of 10 MHz, 600 MHz, and 1.3 GHz, respectively, and better than 52-dB SFDR across the full Nyquist-band, while dissipating 207 mW from a single 1-V supply.      

一个5-bit 4 GS/s的插值型模数转换器设计

设计了一款5-bit 4 GS/s的电阻插值型模数转换器(ADC),由预放大器阵列、高速比较器和编码器模块组成。定量分析了预放大器阵列的带宽和增益对ADC性能的影响,选取了最优的预放大器阵列结构,采样保持电路则选择了分布式采样,并采用电流逻辑模(CML)的比较器和编码电路。基于TSMC 65 nm工艺下进行仿真:在4 GHz的采样频率下,输入信号为200 MHz时,有效位数(ENOB)为4.85,SNDR为30.97,系统功耗为85 m W。     

A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS

A 6-bit 3.5-GS/s flash ADC is reported. A load circuit with a clamp diode and a replica-biasing scheme is developed for low-voltage and high-speed operation. An acceleration capacitor is introduced for high-speed overdrive recovery of a comparator. An averaging and interpolation network is employed in this ADC. The interpolation factor is optimized considering random offset, active area, and systematic offset to realize low offset and small active area. The ADC is fabricated in a 90-nm CMOS process and occupies 0.15 mm². It consumes 98 mW with a 0.9-V power supply. With Nyquist input, SNDR and SFDR at 3.5 GS/s are 31.18 dB and 38.67 dB, respectively.     

5-bit 1.25GS/s Flash ADC的设计及数字后台校正的实现

-本文设计了一款高速的全并行模数转换器,并基于Volterra级数设计了校正反模型,对此款ADC进行了数字后台校正。首先,基于0.18 CMOS设计了一个采样频率为1.25GHz分辨率为5位的Flash ADC,该ADC采用分布式采保结构对输入信号进行量化。同时,基于Volterra级数,实现了数字后台校正模型的设计,并基于此模型对所设计的高速Flash ADC的非线性进行了补偿和校正。仿真结果表明,ADC的输出信号谐波得到了很好的抑制,当输入信号频率为117.1M时,有效位数达到了4.83bit;当输入信号接近奈奎斯特频率时,有效位数达到了4.74bit。     

一种低延迟折叠插值12位1.5 GS/s ADC

基于4级级联折叠插值架构,提出了一种12位ADC。电路采用0.18μm SiGe BiCMOS工艺设计。单核达到1.5 GS/s的转换速度,接口输出为2-lane LVDS,延迟时间小于7 ns。前端采样保持电路和折叠插值量化器采用纯双极设计,在不修调的情况下可达到12位量化精度。最后,给出版图设计要点和测试结果。     

单通道8bit1.4GS/s折叠内插ADC

基于0.18 μm CMOS工艺设计并实现了一种8 bit 1.4 GS/s ADC.芯片采用多级级联折叠内插结构降低集成度,片内实现了电阻失调平均和数字辅助失调校准.测试结果表明,ADC在1.4GHz采样率下,有效位达6.4bit,功耗小于480 mW.文章所提的综合校准方法能够有效提高ADC的静态和动态性能,显示出...     

一种12位100 MS/s流水线ADC的设计

设计了一种12位100 MS/s流水线型模数转换器。采用3.5位/级的无采保前端和运放共享技术以降低功耗;采用首级多位数的结构以降低后级电路的输入参考噪声。采用一种改进型的双输入带电流开关的运放结构,以解决传统运放共享结构所引起的记忆效应和级间串扰问题。在TSMC 90 nm工艺下,采用Cadence Spectre进行仿真验证,当采样时钟频率为100 MS/s,输入信号频率为9.277 34 MHz时,信干噪比(SNDR)为71.58 dB,无杂散动态范围(SFDR)为86.32 dB,电路整体功耗为220.8 mW。     

A 1.9 Gb/s 358 mW 16–256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS

A 16-256 state coarse-grain reconfigurable Viterbi accelerator fabricated in 1.3 V_t 90 nm dual-CMOS technology is described for 3.8 GHz operation, with 1.9 Gb/s data rate in 32-state mode. Radix-4 ripple-carry ACS circuits, reconfigurable path metric read/write control, and tree-bitline traceback memory circuits with programmable ring-buffer decoders enable 358 mW total power, measured at 1.3 V, 50degC, with performance scalable to 2.35 Gb/s at 1.7 V, 50degC.     

200Ms/s 177mW 8位折叠内插结构的CMOS模数转换器

介绍了一个采用折叠内插结构的CMOS模数转换器,适合于嵌入式应用.该电路与标准的数字工艺完全兼容,经过改进的无需电阻就能实现的折叠模块有助于减小芯片面积.在输入级,失调平均技术降低了输入电容,而分布式采样保持电路的运用则提高了信号与噪声的失真比.该200MHz采样频率8位折叠内插结构的CMOS模数转换器在3.3V电源电压下,总功耗为177mW,用0.18μm 3.3V标准数字工艺实现.     

A 20 GS/s 5-Bit SiGe BiCMOS Dual-Nyquist Flash ADC With Sampling Capability up to 35 GS/s Featuring Offset Corrected Exclusive-Or Comparators

The design and wafer probe test results of a 5-bit SiGe Flash ADC are presented. The integrated circuit, fabricated in a 200/250 GHz ${rm f}_{rm T}/{rm F}_{max}$, SiGe BiCMOS technology, provides a 5-bit analog to digital conversion with dual Nyquist operation at sample frequencies up to 20 GHz. Sampling clock rates are demonstrated as high as 35 GS/s. The ADC makes use of a comparator with an integrated exclusive-or function to reduce power consumption. The device also generates two half-rate interleaved outputs to ease data capture with laboratory equipment. An effective number of bits (ENOB) of nearly 5.0 is achieved for low-frequency input tones, dropping to 4.0 at 10 GHz.      

8 bit 400 MS/s CMOS折叠插值结构ADC的设计

折叠插值结构是高速ADC设计中的常用结构。提出了一种新的在折叠插值结构ADC中只对THA进行时间交织的技术,可以在基本不增加芯片功耗和面积的情况下,使ADC的系统速度提高近1倍。位同步技术可以保证粗分和细分通路之间的同步,在位同步的基础上设计了新的编码方式。基于上述技术设计了8 bit 400 MS/s CMOS折叠插值结构ADC,核心电路电流为110mA,面积仅1mm×0.8mm,Nyquist采样频率下SNDR为47.2dB,SFDR为57.1dB。     

200Ms/s 177mW 8位折叠内插结构的CMOS模数转换器

介绍了一个采用折叠内插结构的CMOS模数转换器,适合于嵌入式应用.该电路与标准的数字工艺完全兼容,经过改进的无需电阻就能实现的折叠模块有助于减小芯片面积.在输入级,失调平均技术降低了输入电容,而分布式采样保持电路的运用则提高了信号与噪声的失真比.该200MHz采样频率8位折叠内插结构的CMOS模数转换器在3.3V电源电压下,总功耗为177mW,用0.18μm3.3V标准数字工艺实现     

基于混合结构的一种高性能90nm CMOS逐次逼近A/D转换器

实现了一种10位2.5MS/s逐次逼近A/D转换器。在电路设计上采用了R-C混合结构D/A转换、伪差分比较结构以及低功耗电平转换方式实现。为了实现好的匹配性能,在版图布局上分别采用电阻梯伪电阻包围对策以及电容阵列共中心对称布局方式进行布局。整个A/D转换器基于90nm CMOS工艺实现,在3.3V模拟电源电压以及1.0V数字电源电压下,测得的DNL和INL分别为0.36LSB和0.69LSB。在采样频率为2.5MS/s,输入频率为1.2MHz时,测得的SFDR和ENOB分别为72.86dB和9.43bits。包括输出驱动在内,测得整个转换器的功耗为6.62mW。整个转换器的面积约为238um×214um。设计结果显示该转换器性能良好,非常适合多电源嵌入式SoC的应用。     

A 130 nm CMOS 6-bit Full Nyquist 3 GS/s DAC

This paper presents a 6-bit very high-speed, low-power digital-to-analog converter (DAC). It is based on a current steering binary weighted architecture and achieves 10-bit static linearity without calibration. Due to the use of a pseudo-segmented structure instead of a thermometer decoder, the operating speed of the converter can be up to 4.5 GS/s. The DAC occupies 0.4 mm $times$ 0.5 mm in a standard 130 nm CMOS technology. A spurious-free dynamic range (SFDR) of more than 36 dB has been measured over the complete Nyquist interval at sampling frequencies up to 3 GS/s. The power consumption at a 3 GHz clock frequency for a near-Nyquist sinusoidal output signal equals 29 mW .      

A high performance 90 nm CMOS SAR ADC with hybrid architecture

A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design chal-lenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlin-earity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238×214 μm~2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.     

An 85 mW, 10 b, 40 Msample/s CMOS parallel-pipelined ADC

The design of a low-power 10 b, 40 Msample/s ADC integrated in a 0.8 μm multithreshold CMOS process is presented. The fully differential design employs parallel-pipelined ADC each using a combination of single- and multibit-per-stage pipelined architectures. The ADC, targeted for high-resolution video terminals and ultrasound scanning applications, achieves a nonlinearity-plus-quantization-error of ±1 LSB at 10 b, dissipates 85 mW from a single 2.7 V supply, and occupies an area of 1.9 mm by 2.1 mm     

一个单通道10位160兆每秒的逐次逼近式模数转换器

This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register （SAR） analog-to-digital converter （ADC） in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 ×200 μm^2 is occupied.     

A 6.9 mA 5 bits 90 nm 1 GS/s ADC without calibration for UWB application

Power consumption of high-speed low-resolution ADCs can be reduced by means of calibration. However, this solution presents some drawbacks like allocating a calibration time, calibration algorithm complexity, calibration circuit implementation, etc. In alternative, this paper presents a 5-bit 1 Gs/s ADC without calibration, realized in a 90 nm-CMOS. The device is based on the use of an improved version of double tail dynamic comparators, operating with a fixed bias current. These comparators present a reduced kickback noise, allowing increasing the input transistors sizes in order to improve the matching. The ADC current consumption is equal to 6.9 mA from a 1.2 V supply.     

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm².