Improved parallel weighted bit-flipping decoding algorithm for LDPC codes

Aiming at seeking a low-complexity decoder with fast decoding convergence speed for short or medium low-density parity-check (LDPC) codes, an improved parallel weighted bit-flipping (IPWBF) algorithm, which is applied flexibly for two classes of codes is presented here. For LDPC codes with low column weight in their parity check matrix, both bootstrapping and loop detection procedures, described in the existing literature, are included in IPWBF. Furthermore, a novel delay-handling procedure is introduced to prevent the codeword bits of high reliability from being flipped too hastily. For large column weight finite geometry LDPC codes, only the delay-handling procedure is included in IPWBF to show its effectiveness. Extensive simulation results demonstrate that the proposed algorithm achieves a good tradeoff between performance and complexity.     

汽车车内噪声主动控制变步长NFB-LMS算法

为规避最小均方（Least Mean Square,LMS）算法不能同时提高收敛速度和降低稳态误差的固有缺陷,以及已有变步长LMS算法存在收敛速度慢和稳态误差估计精度差的问题,文中提出了一种基于变步长归一化频域块（Normalized Frequency-domain Block,NFB） LMS算法的汽车车内噪声主动控制方法。为了比较,应用传统的LMS算法、基于反正切函数的变步长LMS算法和变步长NFB-LMS算法分别进行实测汽车车内噪声的主动控制。结果表明,与其他两个算法相比,变步长NFB-LMS算法的收敛速度提高了70%以上,稳态误差减小了90%以上。变步长NFB-LMS算法在处理车内噪声信号时具有很高的效率,为进行汽车车内噪声主动控制提供了一种新方法。     

基于FxLMS的汽车车内噪声变步长主动均衡算法

提出了一种可用于汽车车内噪声主动均衡控制的变步长主动噪声均衡（Active Noise Equalization,ANE）算法,与传统车内噪声主动抵消控制方法所采用的滤波x最小均方（Filtered-x Least Mean Square,FxLMS）算法相比具有更好的实用性。应用固定步长主动噪声均衡（Active Noise Equalization,ANE）算法、所提出变步长ANE算法和已有变步长ANE算法分别进行汽车车内噪声主动均衡控制。结果表明,所提出变步长ANE算法具有更快的收敛速度和较低的稳态误差,并且能进一步降低汽车车内噪声响度,为汽车车内声品质主动控制提供了一种新方法。     

一种新颖的水声相干通信接收算法

为了克服水声信道的多径衰落,消除码间干扰,获得可靠的数据传输,提出了一种新颖的水声相干通信接收算法。该新型算法有两个优点:一是将自适应判决反馈均衡器和迭代译码技术相结合,二是译码采用Turbo译码原理,整个译码系统可以看作是串联迭代译码器,只是其中的内部译码器被编码比特对数似然率(LLR)计算器所取代,有效地降低了运算复杂度。同时,自适应判决反馈均衡器采用了变步长因子算法,改善了均衡器的收敛速度。仿真实验验证了该组合接收算法的性能     

Improved low-complexity low-density parity-check decoding

A practical low-complexity decoding of low-density parity-check codes is studied. A fast decoding scheme for weighted bit-flipping (WBF) based algorithms is first proposed. Then, an optimised 2 bit decoding scheme and its VLSI architecture are presented. It is shown that the new approach has significantly better decoding performance while having comparable hardware complexity compared with WBF-based algorithms.     

一种变步长的自适应特征值分解时延估计方法

在房间声场环境下基于传声器阵列的说话人定位中,时延估计算法是其中的关键步骤。与其它常用时延估计方法相比,自适应特征值分解（Adaptive Eigenvalue Decomposition,AED）时延估计算法因其优越的抗混响性能受到越来越多的关注。但在受噪声和混响干扰的语音条件下,传统的自适应特征值分解算法收敛速度较慢,对初值敏感。通过引进动量因式,提出了一种变步长的特征值分解算法,通过理论分析和仿真实验,证实了新算法的收敛性能要优于传统的特征值分解算法,节省收敛时间,使算法的整体性能有所提高。     

Two new decoding algorithms for Reed-Solomon codes

The subject of decoding Reed-Solomon codes is considered. By reformulating the Berlekamp and Welch key equation and introducing new versions of this key equation, two new decoding algorithms for Reed-Solomon codes will be presented. The two new decoding algorithms are significant for three reasons. Firstly the new equations and algorithms represent a novel approach to the extensively researched problem of decoding Reed-Solomon codes. Secondly the algorithms have algorithmic and implementation complexity comparable to existing decoding algorithms, and as such present a viable solution for decoding Reed-Solomon codes. Thirdly the new ideas presented suggest a direction for future research. The first algorithm uses the extended Euclidean algorithm and is very efficient for a systolic VLSI implementation. The second decoding algorithm presented is similar in nature to the original decoding algorithm of Peterson except that the syndromes do not need to be computed and the remainders are used directly. It has a regular structure and will be efficient for implementation only for correcting a small number of errors. A systolic design for computing the Lagrange interpolation of a polynomial, which is needed for the first decoding algorithm, is also presented.This research was supported by a grant from the Canadian Institute for Telecommunications Research under the NCE program of the Government of Canada     

A novel approach to generating long low-density parity-check codes using two configurations

A new low-complexity generating method is given for the construction of long low-density parity-check (LDPC) codes. The method is based on performing a combinatorial operation between two given configurations. Combinatorial structures such as lattices, affine and projective planes are considered as the constituent configurations. Using this method, we present several classes of well-structured four-cycle free LDPC codes of high rates most of which are quasi-cyclic. From among the main advantages of this approach, we may refer to its low-complexity property and the fact that from performance perspective the constructed codes compete with the pseudorandom LDPC codes.     

A new LDPC decoding algorithm aided by segmented cyclic redundancy checks for magnetic recording channels

We introduce a new low-density parity-check (LDPC) decoding algorithm that exploits the cyclic redundancy check (CRC) information of data segments. By using the error detection property of the CRC, we can successively decode data segments of a codeword corrupted by random errors and erasures. The key idea is that the messages from the variable nodes with correct checksum are fixed to deterministic log likelihood ratio values during LDPC iterative decoding. This approach improves the decoding speed and codeword error rate without significant modification of the LDPC decoding structure. Moreover, the CRC is also used for an early stopping criterion of LDPC decoding. Simulation results verify our claims.     

Improved regular and semi-random rate-compatible low-density parity-check codes with short block lengths

Powerful rate-compatible codes are essential for achieving high throughput in hybrid automatic repeat request (ARQ) systems for networks utilising packet data transmission. The paper focuses on the construction of efficient rate-compatible low-density parity-check (RC-LDPC) codes over a wide range of rates. Two LDPC code families are considered; namely, regular LDPC codes which are known for good performance and low error floor, and semi-random LDPC codes which offer performance similar to regular LDPC codes with the additional property of linear-time encoding. An algorithm for the design of punctured regular RC-LDPC codes that have low error floor is presented. Furthermore, systematic algorithms for the construction of semi-random RC-LDPC codes are proposed based on puncturing and extending. The performance of a type-ll hybrid ARQ system employing the proposed RC-LDPC codes is investigated. Compared with existing hybrid ARQ systems based on regular LDPC codes, the proposed ARQ system based on semi-random LDPC codes offers the advantages of linear-time encoding and higher throughput.     

A complete immunoglobulin-based artificial immune system algorithm for two-stage assembly flowshop scheduling problem with part splitting and distinct due windows

This paper considers a two-stage assembly flowshop scheduling problem with distinct due windows to minimise the sum of weighted earliness and tardiness. There are several identical parallel machines which produce parts in the first stage. When the required parts are available, a single assembly machine can group these parts into products in the second stage. It is assumed that a part can be split into sub-parts which can be processed independently on the parallel machines in the first stage. Setup is also considered. A mathematical model is established to describe and define the proposed problem. A new decoding method is developed by extending an existing decoding method. Two novel operators, named part splitting (PS) and optimal idle time insertion (ITI), are incorporated into the decoding procedure for improving the quality of the solution. A rule named Priority of Earliness and Tardiness (PET) and a Complete Immunoglobulin-based Artificial Immune System (C-IAIS) algorithm are proposed for solving the problem. To evaluate PET and C-IAIS algorithm, several existing algorithms are used in the experiments. Computational results show that C-IAIS algorithm performs better than other algorithms for solving the proposed problem.     

独立分量分析的算法分析与改进

Fast ICA算法是基于一批已取得的样本数据进行处理,它不适用信道矩阵变化的情况;虽基于自然梯度的Info max法是根据单次观测的样本值来调整分离矩阵,但它仅适合单类信源情况。在信道恒定和变化情况下,仿真比较上述算法的优缺点,同时为解决在线算法中收敛速度和稳态误差的矛盾,提出一种改进的变步长算法。该算法将步长变化与信号的分离程度相联系,根据信号之间的相似性测度变化量自适应地控制步长,最后仿真验证该算法的实用性。     

改进变步长LMS算法及在自适应噪声抵消中的应用

在分析传统LMS算法、变步长LMS算法及其改进算法的基础上,通过建立步长因子μ与误差信号е之间的非线性关系,提出了一种改进的变步长LMS自适应滤波算法,并将其应用于自适应噪声抵消中,还分析了参数对算法性能的影响,结果表明该算法具有较快的收敛速度和较小的稳态失调。文中最后给出了仿真结果,仿真结果与理论分析一致。     

Improved imperialist competitive algorithms for rebalancing multi-objective two-sided assembly lines with space and resource constraints

In this paper, a mathematical model and an improved imperial competition algorithm (IICA) are proposed to solve the multi-objective two-sided assembly line rebalancing problem with space and resource restrictions (MTALRBP-SR). The aim is to find lines’ rebalance with the trade-off between efficiency, rebalancing cost and smoothing after reconfiguration. IICA utilises a new initialisation heuristic procedure based on classic heuristic rules to generate feasible initial solutions. A novel heuristic assimilation method is developed to vigorously conduct local search. In addition, a group-based decoding heuristic procedure is developed to fulfil the final task reassignment with the additional restrictions. To investigate the performance of the proposed algorithm, it is first tested on MTALRBP of benchmark problems and compared with some existing algorithms such as genetic algorithm, variable neighbourhood search algorithm, discrete artificial bee colony algorithm, and two iterated greedy algorithms. Next, the efficiency of the proposed IICA for solving MTALRBP-SR is revealed by comparison with a non-dominated sorting genetic algorithm (NSGA-II) and two versions of original ICA. Computational results and comparisons show the efficiency and effectiveness of IICA. Furthermore, a real-world case study is conducted to validate the proposed algorithm.     

An effective shuffled frog-leaping algorithm for solving the hybrid flow-shop scheduling problem with identical parallel machines

In this article, an effective shuffled frog-leaping algorithm (SFLA) is proposed to solve the hybrid flow-shop scheduling problem with identical parallel machines (HFSP-IPM). First, some novel heuristic decoding rules for both job order decision and machine assignment are proposed. Then, three hybrid decoding schemes are designed to decode job order sequences to schedules. A special bi-level crossover and multiple local search operators are incorporated in the searching framework of the SFLA to enrich the memetic searching behaviour and to balance the exploration and exploitation capabilities. Meanwhile, some theoretical analysis for the local search operators is provided for guiding the local search. The parameter setting of the algorithm is also investigated based on the Taguchi method of design of experiments. Finally, numerical testing based on well-known benchmarks and comparisons with some existing algorithms are carried out to demonstrate the effectiveness of the proposed algorithm.     

一种自适应EPF算法及其在光纤水听器中的应用

基于椭圆拟合的相位生成载波(Phase Generated Carrier,PGC)解调方法是消除非线性因素对光纤水听器PGC解调结果影响的一种有效手段,椭圆曲线参数的最优估计问题是实现该方法的关键。扩展卡尔曼粒子滤波(Extended Kalman Particle Filter,EPF)是解决此类非线性估计问题的一种常用的最优估计算法。但传统的EPF算法在用于常参数过程方程的参数或状态估计问题时,过程噪声的方差通常设置为一个常量,这使得算法难以兼顾收敛速度和估计精度,一定程度上限制了算法的整体性能。为了解决这个问题,文章对现有的EPF进行了改进,提出了一种自适应扩展卡尔曼粒子滤波(Adaptive Extended Kalman Particle Filter,AEPF)算法。模拟仿真和实验结果表明,文中所提出的AEPF算法能根据基于椭圆拟合的PGC解调方法有效地解调出待测声信号,相比EKF算法和EPF算法,AEPF算法的收敛速度和估计精度都得到了提升。此外,文章所提出的AEPF算法也适用于其他具有常参数过程方程的参数或状态估计问题,具有一定的通用性。     

基于改进双曲正切函数的变步长最小平均p范数算法

在信号处理领域,传统的自适应滤波算法采用的固定步长会导致稳态误差和收敛速度无法同时兼顾。针对这个问题,对最小平均p范数(Least Mean p-norm,LMP)算法进行改进,提出了一种基于改进双曲正切(tanh)函数的变步长最小平均p范数算法。该算法利用改进的tanh函数来调节步长,采用移动加权平均法构造变步长函数;同时引入了一个调节函数以进一步提升算法的性能。通过在海洋脉冲噪声干扰下进行仿真,实验表明,与已有的固定步长和变步长算法相比,改进的变步长LMP算法较好地兼顾系统的收敛速度和稳态误差;引入调节函数后的新算法在保证原有算法收敛速度的同时进一步降低了算法的稳态误差,从而兼顾了算法的收敛性和稳定性,具有较好的可行性。     

A Low-Complexity Circuit for On-Sensor Concurrent A/D Conversion and Compression

A low-complexity circuit for on-sensor compression is presented. The proposed circuit achieves complexity savings by combining a single-slope analog-to-digital converter with a Golomb-Rice entropy encoder and by implementing a low-complexity adaptation rule. The adaptation rule monitors the output codewords and minimizes their length by incrementing or decrementing the value of the Golomb-Rice coding parameter k. Its hardware implementation is one order of magnitude lower than existing adaptive algorithms. The compression circuit has been fabricated using a 0.35 muM CMOS technology and occupies an area of 0.0918 . Test measurements confirm the validity of the design.     

Enforcing maximum-transition-run code constraints and low-density parity-check decoding

We present a novel algorithm for imposing the maximum-transition-run (MTR) code constraint in the decoding of low-density parity-check (LDPC) codes over a partial response channel. This algorithm provides a gain of about 0.2 dB. We also develop log and max-log versions of the MTR enforcer, similar to the well-known "log-MAP" (maximum a posteriori ) and "max-log-MAP" variants of the LDPC decoder, that have performance equivalent to that of the original version.     

Low-density parity-check codes for volume holographic memory systems

We investigate the application of low-density parity-check (LDPC) codes in volume holographic memory (VHM) systems. We show that a carefully designed irregular LDPC code has a very good performance in VHM systems. We optimize high-rate LDPC codes for the nonuniform error pattern in holographic memories to reduce the bit error rate extensively. The prior knowledge of noise distribution is used for designing as well as decoding the LDPC codes. We show that these codes have a superior performance to that of Reed-Solomon (RS) codes and regular LDPC counterparts. Our simulation shows that we can increase the maximum storage capacity of holographic memories by more than 50 percent if we use irregular LDPC codes with soft-decision decoding instead of conventionally employed RS codes with hard-decision decoding. The performance of these LDPC codes is close to the information theoretic capacity.