A current monitoring technique for IDDQ testing in digital integrated circuits

Although I_DDQ testing has become a widely accepted defect detection technique in CMOS ICs, its effectiveness in nanometer technologies is threatened by the increased leakage current variations. In this paper, a current monitoring technique that overcomes the current variations problem in I_DDQ testing is proposed. According to this, a core is partitioned into two subcircuits and the intrinsic leakage current of the one subcircuit is used to control the leakage current at the I_DDQ sensing node of the other and vice-versa during test application. This way process related leakage current variations are taken into account and small defective currents turn to be detectable according to the needs of modern nanometer technologies. Additionally, a Built-In Current Sensor is presented, which exploits the proposed technique and experimental results are illustrated by its application on a fabricated chip.     

Leakage current,active power,and delay analysis of dynamic dual Vt CMOS circuits under P–V–T fluctuations

The leakage current, active power and delay characterizations of the dynamic dual V_t CMOS circuits in the presence of process, voltage, and temperature (P–V–T) fluctuations are analyzed based on multiple-parameter Monte Carlo method. It is demonstrated that failing to account for P–V–T fluctuations can result in significant reliability problems and inaccuracy in transistor-level performance estimation. It also indicates that under significant P–V–T fluctuations, dual V_t technique (DVT) is still highly effective to reduce the leakage current and active power for dynamic CMOS circuits, but it induces speed penalty. At last, the robustness of different dynamic CMOS circuits with DVT against the P–V–T fluctuations is discussed in detail.     

Impact of technology scaling on thermal behavior of leakage current in sub-quarter micron MOSFETs: perspective of low temperature current testing

The increase in the off-state current for sub-quarter micron CMOS technologies is making conventional I_DDQ testing ineffective. Since natural process variation together with low-V_TH devices can significantly increase the absolute leakage value and the variation, choosing a single threshold for I_DDQ testing is impractical. One of the potential solutions is the cooling of the chip during current testing. In this paper we analyze the impact of CMOS technology scaling on the thermal behavior of different leakage current mechanisms in n-MOSFETs and estimate the effectiveness of low temperature I_DDQ testing. We found that the conventional single threshold low temperature I_DDQ testing is not effective for sub-quarter micron CMOS technologies and propose the low temperature ΔI_DDQ test method. The difference between pass and fail current limits was estimated more than 200× for 0.13-μm CMOS technology.     

SeparateI DDQ testing of signal and bias paths in CMOS ICs for defect diagnosis

I _DDQ testing uses an important property of CMOS ICs that in the steady state, the current consumption is very small. Therefore, a higher steady state current is an indicator of a probable process defect. Published literature gives ample evidence that elevation in the steady state current could be caused due to a variety of reasons besides process defects. As technology moves into deep sub-micron region, the increase in various transistor leakage currents have the potential of reducing theI _DDQ effectiveness. In this article, we propose the separation of VDD and VSS supplies for signal and bias paths so that various leakage current components are measured or computed. The methodology provides means for unambiguousI _DDQ testing, better defect diagnosis, and can be used for deep sub-micronI _DDQ testing.     

“Higher-κ” dielectrics for advanced silicon microelectronic devices: A combinatorial research study

Combinatorial methodology is used to rapidly screen suitable ternary higher-κ dielectrics for future complementary metal oxide semiconductor (CMOS), and dynamic random access memory (DRAM) devices. Dielectric constant (κ) and leakage current (L_C) were mapped from capacitance–voltage (C–V) and current–voltage (I–V) measurements. HfO₂–TiO₂–Y₂O₃ library films, made by pulsed laser deposition (PLD), have been characterized. We found a band of compositions in the middle of the HfO₂–TiO₂–Y₂O₃ phase diagram that have dielectric constants in the range of 50–80, with reasonably low leakage currents, that are therefore promising for these applications.     

Current Mode Techniques for Sub-pico-Ampere Circuit Design

In this paper we explore the low current limit that standard CMOS technologies offer for current mode based VLSI designs. We show and validate a reliable circuit design technique for current mode signal processing down to fempto-amperes. We will take advantage of specific-current extractors and logarithmic current splitters to obtain on-chip sub-pA currents. Then we will use a special on-chip saw-tooth oscillator to monitor and measure currents down to a few fempto-amps. This way, sub-pA currents are characterized without driving them off-chip, nor requiring expensive instrumentation with complicated low leakage setups. A special current mirror is also introduced for reliably replicating such low currents. As an example, a simple log-domain first-order low-pass filter is implemented that uses a 100 fF capacitor and a 3.5 fA bias current to achieve a cut-off frequency of 0.5 Hz and using an area of 12 × 24.35 μm² in a standard 0.35 μm CMOS process. A technique for characterizing noise at these currents is described and verified. Also, temperature dependence of leakage currents is measured as well.     

Fully integrated signal conditioning of an accelerometer for implantable pacemakers

This paper shows the development of a fully integrated G _m -C 0.5–7 Hz bandpass amplifier (gain G = 400), for a piezoelectric accelerometer to be employed in rate adaptive pacemakers. The circuit, fabricated in a standard 0.8 micron CMOS technology, operates with a power supply as low as 2 V, consumes 230 nA of current, and has only a 2.1 μV_rms input referred noise. Detailed circuit specifications, measurements, and a system performance comparative analysis are presented. The physical activity system includes a fully integrated G _m -C rectifier and 3-second time average. Fully integrated very low frequency circuits were implemented with the aid of series-parallel current division in symmetrical OTAs. OTAs as low as 33 pS (equivalent to a 30 GΩ resistor) were designed, fabricated, and tested.     

A high performances CMOS CCII and high frequency applications

In this paper, we propose an improved translinear based CCII configuration. Heuristic algorithm is used for optimal sizing regarding static and dynamic performances. PSPICE simulations for AMS 0.35 μm CMOS technology show that the current and voltage bandwidths are respectively 2.6 GHz and 3.9 GHz, and the parasitic resistance at port X (R _X ) has a value of 18 Ω for a control current of 100 μA. The improved configuration is used as a building block into high frequency design applications: a current controlled oscillator and a tunable fully integrable band pass filter. The oscillator frequency can be tuned in the range of [290–475 MHz] by a simple variation of a DC current. The central frequency of the band pass filter can be varied in the range of [1.22–1.56 GHz] and the quality factor vary in the range [8–306] with a simple variation of a DC current.     

Thick Metal CMOS Technology on High Resistivity Substrate and Its Application to Monolithic L-Band CMOS LNAs

Thick metal 0.8 µm CMOS technology on high resistivity substrate (RF CMOS technology) is demonstrated for the L-band RF IC applications, and we successfully implemented it to the monolithic 900 MHz and 1.9 GHz CMOS LNAs for the first time. To enhance the performance of the RF circuits, MOSFET layout was optimized for high frequency operation and inductor quality was improved by modifying the technology. The fabricated 1.9 GHz LNA shows a gain of 15.2 dB and a NF of 2.8 dB at DC consumption current of 15 mA that is an excellent noise performance compared with the off-chip matched 1.9 GHz CMOS LNAs. The 900 MHz LNA shows a high gain of 19 dB and NF of 3.2 dB despite of the performance degradation due to the integration of a 26 nH inductor for input match. The proposed RF CMOS technology is a compatible process for analog CMOS ICs, and the monolithic LNAs employing the technology show a good and uniform RF performance in a five inch wafer.     

Reliability of submicron InGaAs/InP DHBT under thermal and electrical stresses

We report on the reliability of InGaAs/InP DHBT technology which has applications in very high-speed ICs (over 100 Gbits/s). This work presents the results of accelerated aging tests under thermal and electrical stresses performed on HBT up to 2000 h. Stress conditions consist in applying collector–emitter bias V_CE from 1.3 to 2.7 V and collector current densities J_C of 400 and 610 kA/cm². The corresponding junction temperatures T_J extends from 83 to 137 °C. The base current ideality factor η_B increase and the current gain β decrease have revealed a degradation of the base–emitter junction. The normalized current gain β_norm drop has occurred earlier for higher V_CE and/or higher T_J. A 20% decrease of β_norm chosen as the failure criterion leads to an activation energy of 1.1 eV.     

A multiple-output switched-capacitor DC–DC converter for individual brightness control of RGB LEDs with time-interleaved control and output current regulation

In this paper, an integrated multiple-output switched-capacitor (SC) converter with time-interleaved control and output current regulation is presented. The SC converter can reduce the number of passive components and die areas by using only one flying capacitor and by sharing active devices. The proposed converter has three outputs for individual brightness control of red–green–blue (RGB) LEDs. Each output directly regulates the current due to the V–I characteristics of LEDs, which are sensitive to PVT variations. In the proposed converter, the current-sensing technique is used to control the output current, instead of current-regulation elements (resistors or linear regulators). Additionally, in order to reduce the active area, three outputs share one current-sensing circuit. In order to improve the sensing accuracy, bias current compensation is applied to a current-sensing circuit. The proposed converter has been fabricated with a CMOS 0.13-μm 1P6M CMOS process. The input voltage range of the converter is 2.5–3.3 V, and the switching frequency is 200 kHz. The peak power efficiency reaches 71.8 % at V _IN =2.5 V, I _LED1 = 10 mA, I _LED2 = 18 mA, and I _LED3 = 20 mA. The current variations of individual outputs at different supply voltages are less than 0.89, 0.72, and 0.63 %, respectively.     

Second-layer polysilicon structures for gate end-around leakage-current compensation in bulk CMOS ICs

CMOS integrated circuits (ICs) operating in space or other radiation environments can suffer from three different reliability problems due to the radiation: total dose effects, dose rate effects, and single event effects. The two most significant total-dose reliability problems are subthreshold, gate, end-around leakage current and threshold voltage shift. This article documents the theory, design, implementation, and testing of new, second-layer polysilicon structures that can compensate for radiation-induced, subthreshold, gate, end-around, leakage current. Second-layer polysilicon is available in many commercial, bulk CMOS processes and is normally used for floating-gate devices, such as EEPROMs and FPLAs, and charge-coupled devices such as CCD focal plan arrays. The use of the described structures in CMOS ICs would allow radiation tolerant ICs to be fabricated with commercial, bulk CMOS processes, greatly reducing manufacturing costs when compared to the cost of fabricating ICs on dedicated, radiation-hardened process lines.     

Activation energy of drain-current degradation in GaN HEMTs under high-power DC stress

We have investigated the role of temperature in the degradation of GaN High-Electron-Mobility-Transistors (HEMTs) under high-power DC stress. We have identified two degradation mechanisms that take place in a sequential manner: the gate leakage current increases first, followed by a decrease in the drain current. Building on this observation, we demonstrate a new scheme to extract the activation energy (E_a) of device degradation from step-temperature measurements on a single device. The E_a’s we obtain closely agree with those extracted from conventional accelerated life test experiments on a similar device technology.     

Highly linear wide input range CMOS OTA architectures operating in subthreshold and strong inversion

A very low distortion low-voltage CMOS OTA with very wide g_m adjustment and input range is presented. It is based on a fixed gain novel highly linear voltage-to-current conversion input stage and uses electronically programmable current mirrors to achieve very wide transconductance gain adjustment range. The OTA input range remains approximately constant with g_m adjustment. Bandwidth and input signal range can be adjusted independent of g_m. Simulations results in 0.5 μm CMOS technology with ±1 V supplies and 1 V input range are presented which confirm the characteristics of the proposed structure.     

A prognostic approach for non-punch through and field stop IGBTs

Development of prognostic approaches for insulated gate bipolar transistors (IGBTs) is of interest in order to improve availability, reduce downtime, and prevent failures of power electronics. In this study, a prognostic approach was developed to identify anomalous behavior in non-punch through (NPT) and field stop (FS) IGBTs and predict their remaining useful life. NPT and FS IGBTs were subjected to electrical–thermal stresses until their failure. X-ray analysis performed before and after the stress tests revealed degradation in the die attach. The gate–emitter voltage (V_GE), collector–emitter voltage (V_CE), collector–emitter current (I_CE), and case temperature were monitored in situ during the experiment. The on-state collector–emitter voltage (V_CE(ON)) increased and the on-state collector–emitter current (I_CE(ON)) decreased during the test. A Mahalanobis distance (MD) approach was implemented using the V_CE(ON) and I_CE(ON) parameters for anomaly detection. Upon anomaly detection, the particle filter algorithm was triggered to predict the remaining useful life of the IGBT. The system model for the particle filter was obtained by a least squares regression of the V_CE(ON) at the mean test temperature. The failure threshold was defined as a 20% increase in V_CE(ON). The particle filter approach, developed using the system model based on the V_CE(ON), was demonstrated to provide mean time to failure estimates of IGBT remaining useful life with an error of approximately 20% at the time of anomaly detection.     

I DDQ testing: A review

Quiescent power supply current (I _DDQ ) testing of CMOS integrated circuits is a technique for production quality and reliability improvement, design validation, and failure analysis. It has been used for many years by a few companies and is now receiving wider acceptance as an industry tool. This article begins with a brief history of CMOS ICs to provide perspective on the origin of I _DDQ testing. Next, the use of I _DDQ testing for IC quality improvement through increased defect and fault detection is described. Then implementation issues are considered, including test pattern generation software, hardware instrumentation, limit setting, IC design guidelines, and defect diagnosis. An extended reference list is provided to help the reader obtain more information on specific aspects.     

Compact modeling of response time and random-dopant-fluctuation-induced variability in nanoscale CMOS inverter

As MOSFETs are scaled down to nanometer feature size, random dopant fluctuation (RDF) severely affects CMOS digital integrated circuits (ICs). This paper proposes compact models for estimation of response time and RDF-induced variability in nanoscale CMOS inverter by solution of differential equation considering both input rise time and gate–drain coupling capacitance. The timing characteristics, including propagation delay, overshooting time and transition time, as well as its variability, are accurately modeled in analytical expressions. The proposed models are verified with HSPICE simulations. Monte Carlo analysis also confirms that the models are simple and effective in different design decisions such as width length ratios, load capacitances and source voltages. The studies show that a 7.59% spread in V_T variation due to RDF results in about 5% spread in delay variability for the 65 nm CMOS inverter.     

Electrophysical properties of lead zirconate titanate films doped with lanthanum

The influence of lanthanum doping of lead zirconate titanate films (PZTL) on their polarization properties and leakage currents is studied. The films of Pb_{1 ? x} La _x (Zr_0.48Ti_0.52)_{1 ? x/4}O₃ with x = 0, 0.02, 0.05, 0.08, and 0.1 and a thickness of 240 nm were produced using the sol-gel method at an annealing temperature of 650°C on the substrates with a Si-SiO₂-TiO₂-Pt structure. It is found that the residual polarization and the coercive field are weakened after doping with La. The films with x = 0.02 exhibit satisfactory ferroelectric characteristics (7 μC/cm², 25 kV/cm) that make them suitable for use in ferroelectric memory. The current-voltage curves of PZTL films have two characteristic regions. In weak fields (up to 80–90 kV/cm), the leakage current is attributable primarily to the high resistance of the depletion region of the reverse-biased Schottky barrier at the electrode-ferroelectric interface, and the leakage current is thus practically independent of the La content. When the threshold voltage is exceeded, the Schottky barrier breakdown occurs, and the leakage current in strong fields is defined by the density of free carriers in the bulk of the film. This density depends on the La doping level. The leakage current at x = 0.02 is reduced by about two orders of magnitude compared to undoped PZT film. Further increases in the La content are accompanied by an increase in the leakage current in strong fields. This effect is attributed to a change in the conduction type and an increase in the density of n-type carriers.     

A Compact 3V, 70mW, 12-bit Video-Speed CMOS ADC

A 12-bit video speed pipelined switched capacitor analog-to-digitalconverter (ADC) has been implemented in a 0.5 µmstandard CMOS process. It operates from a single 2.6–;3.3Vsupply, dissipates 23mA (independent of supply voltage) at 20MSPS and occupies only 1.1mm ². A 61dB SINAD (f_in = 4.5 MHz) and an effective resolution bandwidthof 9 MHz is achieved.