基于电路模块自相似性的硬件木马检测方法

由于硬件木马种类的多样性和SoC电路制造过程中不可预测的工艺变化,硬件木马检测变得极具挑战性。现有的旁路信号分析法存在两个缺点,一是需要黄金模型作为参考,二是工艺波动会掩盖部分硬件木马的活动效果。针对上述不足,提出一种利用电路模块结构自相似性的无黄金模型检测方法。通过对32位超前进位加法器的软件仿真实验和对128位AES加密电路的硬件仿真实验,验证了该方法的有效性。实验结果表明,在45 nm工艺尺寸下,对于面积占比较小的硬件木马,该方法的检测成功率可以达到90.0%以上。     

高分辨率多点触控红外触摸屏设计

红外触摸屏是大尺寸触摸屏的首选方案,但是实际应用中红外触摸屏普遍存在分辨率不高、响应速度较慢的不足,而且生产环节存在加工组装复杂的弊端。针对以上不足,提出了一种红外屏设计方案。硬件部分设计了二维选通红外扫描电路、接收电路和滤波电路,实现了发射与接收电路的模块化,为加工组装提供了便利。软件部分首先提出了脉冲式红外扫描方式,并给出了基于STM32F205片内Timer和ADC的脉冲扫描实现方法,提高了红外屏的扫描速度;然后介绍了细分扫描的设计思路,并通过二次细分扫描在不增加硬件成本的基础上提高了红外屏触点的定位精度。最后介绍了支持多点触摸的HID报告描述符的实现方法,实现了红外屏免驱安装。实际证明,该设计方案降低了加工制造复杂度,实现了红外屏即插即用,有效地提高了红外触摸屏的分辨率和响应速度。     

Solder joints inspection using a neural network and fuzzyrule-based classification method

In this paper, we described an approach in automation, the visual inspection of solder joint defects of surface mounted components on a printed circuit board, using a neural network with fuzzy rule-based classification method. Inherently, the solder joints have a curved, tiny, and specular reflective surface. This presents the difficulty in taking good images of the solder joints. Furthermore, the shapes of the solder joints tend to greatly vary with their soldering conditions, and are not identical with each other, even though some of the solder joints belong to a set of the same soldering quality. This problem makes it difficult to classify the solder joints according to their properties. To solve this intricate problem, a new classification method is here proposed which consists of two modules: one based upon an unsupervised neural network, and the other based upon a fuzzy set theory. The novel idea of this approach is that a fuzzy rule table reflecting the knowledge of criteria of a human inspector, is utilized in order to correct any possible misclassification made by the neural network module. The performance of the proposed approach was tested on numerous samples of printed circuit boards in commercially available computers, and then compared with that of a human inspector. Experimental results reveal that the proposed method is superior to the neural network classification method alone, in terms of its accuracy of classification     

Optimization-based multifrequency test generation for analog circuits

A robust test set for analog circuits has to detect faults under maximal masking effects due to variations of circuit parameters in their tolerance box. In this paper we propose an optimization based multifrequency test generation method for detecting parametric faults in linear analog circuits. Given a set of performances and a frequency range, our approach selects the test frequencies that maximize the observability on a circuit performance of a parameter deviation under the worst masking effects of normal variations of the other parameters. Experimental results are provided and validated by HSpice simulations to illustrate the proposed approach.     

Dopingless Impact Ionization MOS (DL-IMOS)- A remedy for complex process flow

We propose a unique approach for realizing dopingless impact ionization MOS (DL-IMOS) based on the charge plasma concept as a remedy for complex process flow. It uses work-function engineering of electrodes to form charge plasma as surrogate doping. This charge plasma induces a uniform p-region in the source side and an n-region in the drain side on intrinsic silicon film with a thickness less than the intrinsic Debye length. DL-IMOS offers a simple fabrication process flow as it avoids the need of ion implantation, photo masking and complicated thermal budget via annealing devices. The lower thermal budget is required for DL-IMOS fabrication enables its fabrication on single crystal silicon-on-glass substrate realized by wafer scale epitaxial transfer. It is highly immune to process variations, doping control issues and random dopant fluctuations, while retaining the inherent advantages of conventional IMOS. To epitomize the fabrication process flow for the proposed device a virtual fabrication flow is also proposed here. Extensive device simulation of the major device performance metrics such as subthreshold slope, threshold voltage, drain induced current enhancement, and breakdown voltage have been done for a wide range of electrodes work-function. To evaluate the potential applications of the proposed device at circuit level, its mixed mode simulations are also carried out.     

Variability aware SVM macromodel based design centering of analog circuits

Design centering is the term used for a procedure of obtaining enhanced parametric yield of a circuit despite the variations in device and design parameters. The process variability in nanometer regimes manifest into variations in these devices and design parameters. During design space exploration of analog circuits, a methodology to find design-instances with better yield is necessitated; this would ensure that the circuit will function as per specifications after fabrication, even with impact of statistical variations. We need to evaluate circuit performance for a given instance of a circuit-design identified by possessing a set of nominal values of device-design parameters. A lot of instances need be searched, having different sizes for a given circuit topology. HSPICE is very compute intensive. Instead, we employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits of different sizing during yield optimization loops. These performance macromodels are found to be as accurate as SPICE and at the same time, time-efficient for use in sizing of analog circuits with optimal yield. Process variability aware SVM macromodels are first trained and then used inside the Genetic algorithm loops for design centering of different circuits, subsequently resulting into sized-circuit instances having optimal yield. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. The application of this design centering approach as process variability analysis tool is illustrated on various circuits e.g. two stage op amp, voltage controlled oscillator and mixer circuit with layouts drawn into 90?nm UMC technology (Euro-practice).     

基于SoPC的红外解码IP核设计与实现

提出一种红外解码IP核在SoPC系统中的设计与实现方案,重点研究红外系统的数据编码和传输机制,红外解码电路的HDL设计,IP核的制作及在SoPC系统中的应用。该方案的红外发送接收芯片分别是TC9012和DS338S,在DE2开发板对IP核进行测试。结果表明,红外解码IP能顺利地添加到SoPC系统中,实现快速、稳定、正确的红外解码功能,达到预期设计目标。     

Statistical Simulation for Process Design and Optimization in IC Manufacture

An approach to multidimensional statistical simulation for process design and optimization in IC manufacture is proposed. It essentially takes account of the sensitivity of circuit parameters to the random variability of process parameters. The approach is implemented in an algorithm and software for process statistical analysis and optimization. The response-surface methodology and pattern-recognition techniques are used for the approximation of relations between process and circuit parameters. The capabilities of the approach are evaluated from simulated and measured data on the fabrication of transistors by routine bipolar and CMOS technologies.     

基于MATLAB定点运算的数字集成电路协同设计方法

为提高超大规模数字集成电路设计中算法评估和电路仿真的效率,介绍了一种基于MATLAB定点运算模型的数字集成电路协同设计方法。针对定点运算的基本操作,建立了一套可与硬件电路行为精确对应的MATLAB模型,并据此搭建出系统的总体定点算法模型。该模型既可与系统浮点算法模型对比以评估算法性能,又能模拟电路的操作,为硬件设计提供精确参考。通过与电路仿真软件的协同操作,可实现仿真结果的自动检查以及错误源头的快速定位,提高仿真和验证的效率。基于该方法设计了2种系统级芯片,均一次流片成功,证明了该方法的有效性。     

Analog circuit optimization using adjoint network based sensitivity analysis

Performance optimization as per the desired specifications is a major requirement of analog and mixed signal circuit design process. Rapid scaling of the semiconductor technology demands efficient optimization techniques with minimal manual efforts. In this paper, a gradient based method for analog circuit optimization using adjoint network based sensitivity analysis is presented. The sensitivity of circuit response with respect to the different parameters is computed by using analog circuit and its adjoint transformation. The proposed method is applied to optimize performance of a two stage operational amplifier (OpAmp). Subsequently, the OpAmp circuit is simulated using Cadence Virtuoso for optimized parameters and the results are validated with post fabrication measurement results.     

High-performance current conveyor implementation

Wideband precision current conveyor performance can be obtained by adapting an approach previously developed for current convertors. The proposed circuit implementation of a CCII+ current conveyor significantly exceeds the performance of all previous conveyor circuit formulations and is also more suitable for monolithic fabrication.     

Soft Fault Diagnosis of Analog Circuits via Frequency Response Function Measurements

This paper provides a novel method for single and multiple soft fault diagnosis of analog circuits. The method is able to locate the faulty elements and evaluate their parameters. It employs the information contained in the frequency response function (FRF) measurements and focuses on finding models of the circuit under test (CUT) as exact as possible. Consequently, the method is capable of getting different sets of the parameters which are consistent with the diagnostic test, rather than only one specific set. To fulfil this purpose, the local plolynomial approach is applied and the associated normalized FRF is developed.The proposed method is especially suitable at the pre-production stage, where corrections of the technological design are important and the diagnostic time is not crucial. Two experimental examples are presented to clarify the proposed method and prove its efficiency.     

Genetic-Algorithm-Based Method for Optimal Analog Test Points Selection

A new approach to an optimal analog test points selection is proposed. The described method uses ambiguity set concept and evolutionary computations to determine the optimal set of analog test points. After a brief introduction to analog testing and genetic algorithms, the proposed strategy is explained. The presented evolutionary approach is illustrated by a practical example of analog circuit and by a series of hypothetical circuits. The efficiency of the technique is compared with a method based on entropy index, and the obtained results are discussed     

A monolithic decode-drive circuit for magnetic memories

The highly replicated decode-drive circuitry of magnetic memories is being produced at a very low cost with batch-fabricated integrated-circuit technology. This has resulted from judiciously reconfiguring traditional circuit forms in order to optimize their fabrication. A new monolithic circuit function and its application are described. The circuit is used for low-cost high-speed 400-mA switching in magnetic memories. The functions of address decoding and timing control are also incorporated into the circuit. The address scheme employs no transformers and possesses the advantages of miniaturization. Details of the circuit configuration, topology, and packaging are described and illustrated.     

On minimal set of test nodes for fault dictionary of analog circuit fault diagnosis

A method is proposed to obtain a minimal set of test nodes of an analog circuit for isolating all faulty conditions in the fault dictionary approach. Relevant theorem along with the proof is also given. Proposed method is extremely fast. This method is illustrated with an active filter circuit example.     

Electrical failure analysis of peristaltic micropumps fabricated with PZT actuators

A detection method based on electrical analysis for valveless peristaltic lead zirconate titanate (PZT) micropump fabrication is proposed. The modified Butterworth-Van Dyke (BVD) model is used to analyze the properties of resistant or capacitive elements related to various failures. The series resistance and parallel capacitance in the BVD model are used to detect faults and classify the failure type. The failure analysis of the micropump assembly process focuses on the three common failures: (a) PZT cracking, (b) uneven silver epoxy distribution, and (c) PZT inversion. The analysis approach combines experimental results with a circuit model to determine PZT micropump fabrication reliability. It can be used to detect defects in peristaltic PZT micropumps and classify failure type.     

A simple CMOS-based inductor simulator and frequency performance improvement techniques

In this paper, a new CMOS grounded positive tunable inductor simulator based on using two simple CMOS transconductors and an inverting amplifier is presented. The introduced inductor simulator uses a grounded capacitor; accordingly, it is suitable for integrated circuit (IC) fabrication. In addition a CMOS circuit for realizing negative tunable resistor which can be used for parasitic cancellation in inductor simulators and consequently enhancing their frequency performances is developed. A novel method for providing high-frequency performance improvement of simulated inductors is also introduced. Simulation and experimental results are given to demonstrate the performance of the developed inductor simulator and validity of the proposed frequency performance improvement method.     

A bridge technique for memristor state programming

ABSTRACT

In order to effectively use a memristor in analog circuits, its memristance should be adjusted to a desired value between its limits. Since the maximum and minimum required memristance typically varies considerably between different types of memristors, it is almost impossible to tune the resistance of each memristor based on a reference resistor. Which is mostly done using some programmer circuits. Moreover, those programming strategies involving pulses are time-consuming and they impose high hardware headroom. In this paper, a novel CMOS circuit is presented for programming memristors. A Wheatstone bridge circuit is used to measure the current memristance, while the programming current is flowing through the device. Using such an approach reading the state and its adjustment are done simultaneously, which reduces the programming latency. In the proposed method, instead of tuning the memristance, the state of the memristor will be set to the desired value, which is proportional to a control voltage. The low programming latency, six-bit accuracy, and use of a simple circuit for programming, are the main advantages of our solution. The proposed circuit is designed and laid out in 0.35 µm CMOS technology and takes 0.0273mm². Furthermore, the proposed approach is applied to a memristor emulator to demonstrate its correct operation in real applications.     

A novel laser direct write technique for fabrication of thin filmMICs

A technique for fabrication of thin-film circuits for microwave integrated circuit (MIC) application is presented. This low-cost fabrication technique utilizes laser direct write of copper patterns on alumina substrates. The method obviates the need for photomasks and photolithography. The film deposition mechanism, deposit film analysis, and MIC fabrication sequence are presented. Performance evaluation of MICs fabricated using this technique is also included     

Design and Application of Adaptive Delay Sequential Elements

Lower operating voltages and faster clock frequencies in advanced fabrication processes increase the circuit delay sensitivity to voltage, temperature, and process variations and modeling approximations. Uncorrelated delay variations along data and clock paths cause timing violations. In this paper, we propose a method for correcting timing violations by in-circuit tuning of clock latencies after fabrication. We introduce adaptive delay sequential elements (ADSEs) that use charge storage on pMOS floating gates to tune the clock latencies of timing critical flip-flops. ADSEs facilitate in-circuit optimization of clock latencies under varying operating conditions. ADSE tuned clock latencies are nonvolatile and can be repeatedly adjusted after fabrication using only electrical signals. We present examples of implicit and explicit pulsed ADSEs and their tuning operations. Our experiments with fabricated prototypes show that ADSEs can tune their clock latencies with picosecond resolution over one-half of the clock period. Our experiments also show that ADSE sensitivities to supply voltage, temperature, noise, and transistor mismatch are comparable to nonadaptive sequential elements. We present experimental data that show ADSE tuned delays change only 15% after ten years at 125degC. We propose a method for selective tuning of embedded ADSEs and demonstrate its application in a fabricated prototype. ADSEs can selectively replace timing-critical flip-flops of a circuit with negligible area impact