TURBO码中的交织器设计及其改进

Turbo码是近年来提出的一种信道编码.该系统在编码时采用并行的反馈系统卷积码(RSC).在编码的同时,对原始信息和经过交织(interleave)乱序的信息进行编码.Turbo码的解码一般采用软输入软输出解码器(SISO).其解码算法主要有SOVA、MAP以及改进的LOGMAN算法.Turbo码的编解码中,交织器的性能是一个关键问题.文章对交织器的设计和各种交织器的性能进行了探讨,并提出了一种易于硬件实现的交织器设计方法.     

一种应用CPM扩频调制的Turbo CDMA系统

本文首先介绍了连续相位调制CPM (Continuous Phase Modulation) 的分解模型^[1],得到CPM调制可以分解为一个线性连续相位编码CPE (Continuous Phase Encoder)和无记忆调制的组合;接着基于CPM的错误事件和递归特性,推出了采用CPM扩频调制的Turbo CDMA系统模型,这里CPM扩频调制作为递归内码,与外编码器及交织器级连构成Turbo迭代系统,该系统有明显的交织增益.利用系统的迭代解调解扩和解码的特点,设计了软输入输出的接收机,接收机中解调器采用MAP(Maximum A Posterior)和SOVA(Soft Output Viterbi Algorithm)算法,解码器采用MAP算法.仿真结果表明CPM调制器作为内码形成级连迭代系统交织增益非常明显.     

Turbo码的迭代译码及在DS—CDMA和OFDM／CDMA中的应用

本文简单介绍了Turbo码基本原理、子码编码器和交织器设计等,详细地分析了Turbo码的基于MAP译码算法和基于SOVA译码算法的迭代译码方法及其性能,并与卷积码的性能进行了比较.重点论述了Turbo码在DS-CDMA移动通信系统的码率与扩频增益折衷设计、迭代译码和性能仿真结果.最后,简单论述了Turbo码在OFDM/CDMA中的应用.     

基于Matlab的Turbo码仿真研究

为了使Turbo码仿真更容易,研究并建立了基于Matlab中Simulink通信模块的Turbo码仿真模型.Turbo码编码器采用两个相同的分量编码器通过交织器并行级联而成.Turbo码译码器采用不同的译码算法,这些算法由S函数调用m文件实现.使用所建立的模型进行仿真,结果表明,在信噪比相同的情况下,交织长度越大、迭代次数越多、译码算法越优,Turbo码性能越好.设计实际系统时,应综合考虑各因素.     

Turbo编译码器中交织器的选择

本文探讨了Turbo编译码器中交织器的选择问题。首先从Turbo码的并行级联编码方案和基于最大后验概率(MAP)算法的迭代译码原理出发分析了交织器对Turbo码的纠错性能的巨大影响,然后总结了Turbo码中交织器设计的一些基本方法并分析其各自特点,最后给出了Turbo码中有关交织器的实用性结论。     

一种短延时Turbo编码调制系统的设计

本文设计了一种比传统体制减少了一半延时的Turbo编码调制系统,介绍了交织器的相关限制.提出了一种在译码过程中对信道值的估计方法,使得外信息的计算更加趋于精确,从而提高了译码性能.这种迭代译码算法是标准格码调制译码算法的一种自然推广,同时也类似于二元Turbo码在BPSK调制下的逐比特译码算法.采用吞吐率为2bits/s/Hz的8PSK调制,比特错误率为10^-5所需的信噪比与Shannon限相距不到0.4dB.     

Turbo编码MIMO/OFDM系统中的Turbo均衡

针对Turbo编码MIMO/OFDM系统,本文提出一种低复杂度的Turbo均衡算法,均衡器采用性能近于最优检测的概率数据辅助（Probabilistic Data Association）算法,与软输入软输出的Turbo信道解码器之间迭代交换外信息,实现信道均衡与信道解码的迭代更新,以充分利用已获得的信息,克服传统判决反馈均衡器误差传播的缺陷。仿真表明,该均衡算法性能要比MMSE＋MF线性检测算法提高约1dB,在Eb/No为4dB时误比特率达到10-6,且算法复杂度仅为O（N3）,经两次迭代就可获得较为满意的码间干扰消除效果。     

Turbo码解码过程中的加权算法

本文通过调整迭代解码过程中系统位接收值的加权系数,提出了一种Turbo码加权迭代解码算法。该算法改变了迭代运算后Turbo码解码器输出软值中系统位接收值信息和它的外部估计信息的比重,使Turbo码无论在低信噪比或是在高信噪比时均具有优良的纠错性能。仿真结果显示,采用Turbo码加权迭代解码算法,不仅能提高Turbo码的收敛速度,而且能进一步降低Turbo码解码时的地板值,使Turbo码的比特误码率在高、低信噪比时都能够得到进一步改善。     

跳频系统下Turbo编译码器的设计

在介绍Turbo码编译码原理基础上,针对特定跳频系统,设计了一种Turbo编译码方案。详细论述了该方案中编译码器的设计、建模和仿真过程。该方案中采用MAX-LOG-MAP的迭代译码算法,仿真验证了译码器采用6次迭代可以在保证抗干扰性能的前提下,面向硬件实现计算量适中。因此,该方法具有一定的工程应用价值。     

一种频选衰落信道下的Turbo多用户检测算法

联合MAP多用户检测与信道解码的迭代多用户检测(MUD)技术可显著提高宽带移动CDMA系统的容量和性能.在多径时变衰落的编码信道下,提出一种迭代实现干扰抑制、符号估计、信道解码的Turbo多用户检测算法.在每次迭代中,MUD自适应地实现干扰抑制并输出符号估计的软信息,软输入软输出的信道解码器使用LOG MAP方法实现信道解码并反馈符号估计的软信息作为下一次TurboMUD迭代的先验信息.仿真结果证实了该算法在频选衰落信道下经两次迭代就能逼近单用户编码CDMA系统的接收性能.     

High-performance VLSI architectures for turbo decoders with QPP interleaver

This paper analyses different VLSI architectures for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. Data flow graphs for standard SISO MAP (maximum a posteriori) turbo decoder, SW – SISO MAP turbo decoder, PW SISO MAP turbo decoder have been presented, thus analysing their performance. Two variants of quadratic permutation polynomial (QPP) interleaver have been proposed which tend to simplify the complexity of ‘mod’ operator implementation and provide best compromise between area, delay and power dissipation. Implementation of decoder using one variant of QPP interleaver has also been discussed. A novel approach for area optimisation has been proposed to reduce required number of interleavers for parallel window turbo decoder. Multi-port memory has also been used for parallel turbo decoder. To increase the throughput without any effective increase in area complexity, circuit-level pipelining and retiming have been used. Proposed architectures have been synthesised using Synopsys Design Compiler using 45-nm CMOS technology.     

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

We present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) interleaver. The high-throughput 3GPP LTE/LTE-Advance Turbo codes require a highly-parallel decoder architecture. Turbo interleaver is known to be the main obstacle to the decoder parallelism due to the collisions it introduces in accesses to memory. The QPP interleaver solves the memory contention issues when several MAP decoders are used in parallel to improve Turbo decoding throughput. In this paper, we propose a low-complexity QPP interleaving address generator and a multi-bank memory architecture to enable parallel Turbo decoding. Design trade-offs in terms of area and throughput efficiency are explored to find the optimal architecture. The proposed parallel Turbo decoder has been synthesized, placed and routed in a 65-nm CMOS technology with a core area of 8.3 mm² and a maximum clock frequency of 400 MHz. This parallel decoder, comprising 64 MAP decoder cores, can achieve a maximum decoding throughput of 1.28 Gbps at 6 iterations     

一种低开销双二元turbo译码器设计

设计一种低开销双二元turbo译码器,提出了一种能够适应滑动窗算法的交织器结构,通过与传统方案中的交织器联合使用,大大降低了交织与解交织过程所需要的存储单元.同时将取模归一化(modulo normalization)技术运用到双二元turbo译码器加比选(ACS)模块的设计上,缩短了关键路径的延时,提高了时钟频率和吞吐量.采用FPGA对译码器进行了验证,提出的译码器和传统的译码器相比,存储资源节省12%,和使用存储器存储交织/解交织地址的译码器相比,存储资源节省97%.     

Design of Prunable Interleavers for Parallel Turbo Decoder Architectures

In this paper we propose a technique to implement in a parallel fashion a turbo decoder based on an arbitrary permutation, and to expand its interleaver in order to produce a family of prunable S-random interleavers suitable for parallel implementations. We show that the spread properties of the obtained interleavers are almost optimal and we prove by simulation that they are very competitive in terms of error floor performance. A few details on the decoder architecture are also provided     

Parallel turbo coding interleavers: avoiding collisions in accessesto storage elements

High-speed, low latency convolutional turbo codes require a parallel decoder architecture. To maximise the gain in speed, the interleaver also should have a parallel structure. Here, a class of optimum parallel interleavers regarding the access to storage elements is presented. They combine regularity (easy implementation) with no latency in data transfer between the decoder module and intrinsic/extrinsic values memories, and show excellent BER performance     

Interleaver design for turbo codes

The performance of a turbo code with short block length depends critically on the interleaver design. There are two major criteria in the design of an interleaver: the distance spectrum of the code and the correlation between the information input data and the soft output of each decoder corresponding to its parity bits. This paper describes a new interleaver design for turbo codes with short block length based on these two criteria. A deterministic interleaver suitable for turbo codes is also described. Simulation results compare the new interleaver design to different existing interleavers     

Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support

This paper presents a unified, radix-4 implementation of turbo decoder, covering multiple standards such as DVB, WiMAX, 3GPP-LTE and HSPA Evolution. The radix-4, parallel interleaver is the bottleneck while using the same turbo-decoding architecture for multiple standards. This paper covers the issues associated with design of radix-4 parallel interleaver to reach to flexible turbo-decoder architecture. Radix-4, parallel interleaver algorithms and their mapping on to hardware architecture is presented for multi-mode operations. The overheads associated with hardware multiplexing are found to be least significant. Other than flexibility for the turbo decoder implementation, the low silicon cost and low power aspects are also addressed by optimizing the storage scheme for branch metrics and extrinsic information. The proposed unified architecture for radix-4 turbo decoding consumes 0.65 mm² area in total in 65 nm CMOS process. With 4 SISO blocks used in parallel and 6 iterations, it can achieve a throughput up to 173.3 Mbps while consuming 570 mW power in total. It provides a good trade-off between silicon cost, power consumption and throughput with silicon efficiency of 0.005 mm²/Mbps and energy efficiency of 0.55 nJ/b/iter.     

Iterative threshold decoding without interleaving for convolutional self-doubly orthogonal codes

A novel iterative error control technique based on the threshold decoding algorithm and new convolutional self-doubly orthogonal codes is proposed. It differs from parallel concatenated turbo decoding as it uses a single convolutional encoder, a single decoder and hence no interleaver, neither at encoding nor at decoding. Decoding is performed iteratively using a single threshold decoder at each iteration, thereby providing good tradeoff between complexity, latency and error performance.     

LTE turbo 解码器设计

本文提出一种可以用于lte小基站的turbo码解码器设计, 它支持LTE标准中的188种不同长度的TURBO码解码。设计采用了最多16路的并行解码,迭代次数可设定。解码器提采用了一种改进的软输入软输出设计。设计采用了轮流计算前向状态矩阵,和后项状态矩阵。这样可以缩短基二算法的关键路径,同时分支传输概率也可以直接用于计算不再需要保存。分组数据利用列地址映射,和行数据交换完成整个码的交织计算,利用相反的过程完成解交织计算。每个时钟都可以产生交织与解交织数据,用于解码和存储运算。