Gate Workfunction Engineering in Bulk FinFETs for Sub-50-nm DRAM Cell Transistors

We proposed a new bulk FinFET that has a p⁺/n⁺ poly-Si gate consists of p⁺ region near the source and n⁺ region near the drain and analyzed current-voltage characteristics and electric field profiles of 50-nm devices by changing the n⁺ poly-Si gate length (L_s). For given gate length (L_gles50 nm) and fin body width (W_finles30 nm), L_s was designed to satisfy the I _off requirement (i.e., 1 fA) of DRAM cell. Optimum L_s /L_g of 30-nm device was ~0.4 at a W_fin of 10 nm and ~0.2 at a W_fin of 15 nm     

Sub-0.1 μm NMOS transistors fabricated using laser-plasmapoint-source X-ray lithography

We report the experimental results of the first MOSFET's ever fabricated using a laser plasma-source X-ray stepper. The minimum gate length of these transistors is 0.12 μm with an effective channel length of 0.075 μm. These transistors were patterned using a mix-and-match lithography scheme where the gate level was printed using a 1.4 nm plasma-source X-ray stepper while the other layers were patterned using optical lithography     

Field-Based Capacitance Modeling for Sub-65-nm On-Chip Interconnect

Back-end-of-the-line (BEOL) interconnect becomes a limiting factor to circuit performance in scaled complementary metal–oxide–semiconductor design. To accurately extract its paratactic capacitance for circuit simulation, compact models should be scalable with wire geometries and should capture the latest technology advances, such as the air gap and Cu diffusion barrier. This paper achieves these goals based on the distribution of the electric field in on-chip BEOL structures. By decomposing the electric field into various regions, the proposed method physically solves each basic capacitance component into a closed-form solution; the total ground and coupling capacitances are then the sum of all related components. Such a component-based approach is convenient in incorporating new interconnect structures. Its physics basis minimizes the complexity and the error in a traditional model fitting process. Compared with Raphael simulations at the 45-nm node, the new compact model accurately predicts the capacitance value, even in the presence of the air gap and diffusion barrier, covering a wide range of BEOL dimensions. The complete set of equations will be implemented at http://www.eas.asu.edu/~ptm.      

Sub-100-nm vertical MOSFET with threshold voltage adjustment

Sub-100-nm vertical MOSFET has been developed for fabrication with low cost processing. This is the first vertical MOSFET design that combines 1) a vertical L_DD structure processed with implantation and diffusion steps, 2) high-pressure oxide growing at source/drain (S/D) regions to reduce the gate overlapped capacitances, and 3) threshold voltage adjustment with a doped APCVD film. The drive current per unit channel width and S/D punch-through voltage are higher than that of previously published vertical MOSFETs. Fabrication processes are well established, and equipment of the 1 μm CMOS generation can be used to fabricate sub-100-nm channel length MOSFETs with good electrical characteristics and high performance     

A high-Q quasi-planar filtering solution for 60-GHz applications

A low insertion loss 2.2% bandwidth two-pole cavity filter was fabricated at 60 GHz by bonding metallized lids on each side of a 250-/spl mu/m silicon substrate. The lids are made by dry etching of a 500-/spl mu/m silicon substrate. The same process is used to etch via holes on the intermediate substrate. The position of these via holes fixes the external coupling and the coupling between the resonators. The measured unloaded quality factor is lied on the height of the cavity (1.05 mm) and is around 1100.     

Subhalf-micrometer p-channel MOSFET's with 3.5-nm gate Oxide fabricated using X-ray lithography

Subhalf-micrometer p-channel MOSFET's with ultra-thin gate oxide (3.5 nm) have been fabricated using X-ray lithography and electron cyclotron resonance (ECR) plasma etching. The fabricated MOSFET's with 0.2-µm channel lengths show long-channel behavior and extremely high (200 mS/mm) transconductance.     

n+/p+ Gate Bulk FinFETs With Locally Separated Channel Structure for Sub-50-nm DRAM Cell Transistors

We proposed a new p⁺/n⁺ poly-Si gate bulk fin-type field-effect transistor that has two channel fins separated locally by a shallow trench filled with oxide or p⁺ polygate. Key device characteristics were investigated by changing the n⁺ poly-Si gate length La, the material filling the trench, and the width and length of the trench at a given gate length L_g. It was shown that the trench filled with p⁺ poly-Si gate should not be contacted with the source/drain diffusion region to achieve an excellent I_on/I_off (> 1010) that is suitable for sub-50-nm dynamic random access memory cell transistors. Based on the aforementioned device structure, we designed reasonable Ls/Lg and channel fin width W_cfin at given L_g 's of 30, 40, and 50 nm.     

Modeling Aspects of Sub-100-nm MOSFETs for ULSI-Device Applications

Ultrathin oxides (1-3 nm) are foreseen to be used as gate dielectric in complementary-MOS technology during the next ten years. Nevertheless, they require new approaches in modeling and characterization due to the onset of quantum effects. Predicting device characteristics including quantum effects requires solving of Schroumldinger's equation together with Poisson's equation. In this paper, Poisson's equation is solved in two dimensions (2-D) over the entire device using Green's function approach, while Schroumldinger's equation is decoupled using triangular-potential-well approximation. The carrier density thus obtained is included in the space-charge density of Poisson's equation to obtain quantum-carrier confinement effects in the modeling of sub-100-nm MOSFETs. The framework also consists of the effects of source/drain-junction curvature and depth, short-channel effects, and drain-induced barrier-lowering effect. The 2-D potential profiles thus obtained with above said effects form the basis for an estimation of threshold voltage. Using this potential distribution, the transfer characteristics of the device are also evaluated. The method presented is comprehensive in the treatment, as it neither requires self-consistent numerical modeling nor it contain any empirical or fitting expression/parameter to provide formulation for quantized-carrier effect in the inversion layer of MOSFETs. The results obtained show good agreement with available results in the literature and with simulated results, thus proving the validity of our model     

Computer Simulation of a Nanoscale Ballistic SOI MOSFET with a Sub-10-nm Si Layer

A physical model and a computer simulation program for nanoscale ballistic SOI MOSFETs are developed. The model includes transistor parameters such as the type and level of doping in the source and drain regions, gate length, Si and gate-oxide thicknesses, spacer length, gate-material work function, etc. Transistor performance is characterized in terms of transconductance, subthreshold slope, on- and off-state drain currents, gate–source overlap capacitance, etc. The software enables one to optimize the transistor parameters.     

High-performance n-type organic field-effect transistors fabricated by ink-jet printing using a C60 derivative

We report on the performance of ink-jet-printed n-type organic thin-film transistors (OTFTs) based on a C₆₀ derivative, namely, C₆₀-fused N-methyl-2-(3-hexylthiophen-2-yl)pyrrolidine (C₆₀TH-Hx). The new devices exhibit excellent n-channel performance, with a highest mobility of 2.8 × 10^?2 cm² V^?1 s^?1, an I_On/I_Off ratio of about 1 × 10⁶, and a threshold voltage of 7 V. The C₆₀TH-Hx films show large crystalline domains that result from the influence of an evaporation-induced flow, thus leading to high electron mobility in the ink-jet-printed devices.     

Sub-50-nm physical gate length CMOS technology and beyond usingsteep halo

Sub-50-nm CMOS devices are investigated using steep halo and shallow source/drain extensions. By using a high-ramp-rate spike annealing (HRR-SA) process and high-dose halo, 45-nm CMOS devices are fabricated with drive currents of 650 and 300 μA/μm for an off current of less than 10 nA/μm at 1.2 V with T_ox^inv =2.5 nm. For an off current less than 300 nA/μm, 33-nm pMOSFETs have a high drive current of 400 uA/μm. Short-channel effect and reverse short-channel effect are suppressed simultaneously by using the HRR-SA process to activate a source/drain extension (SDE) after forming a deep source/drain (S/D). This process sequence is defined as a reverse-order S/D (R-S/D) formation. By using this formation, 24-nm nMOSFETs are achieved with a high drive current of 800 μA/μm for an off current of less than 300 μA/μm at 1.2 V. This high drive current might be a result of a steep halo structure reducing the spreading resistance of source/drain extensions     

Plasma Etching for Sub-45-nm TaN Metal Gates on High-k Dielectrics

Etching of TaN gates on high-k dielectrics (HfO₂ or HfAlO) is investigated using HBr/Cl₂ chemistry in a decoupled plasma source (DPS). The patterning sequence includes 248-nm lithography, plasma photoresist trimming, etching of a SiN-SiO₂ hard mask, and photoresist stripping, followed by TaN etching. TaN etching is studied by design of experiment (DOE) with four variables using a linear model with interactions. It is found that at a fixed substrate temperature and wafer chuck power, etch critical dimensions (CD) gain decreases with decreasing HBr/Cl₂ flow rate ratio and pressure and with increasing source power and total gas flow rate. Based on these DOE findings, subsequent optimization is performed and a three-step etching process is developed; a main feature of the process is progressively increasing HBr/Cl₂ flow rate ratio. The optimized process provides etch CD gain within 2 nm and gate profile close to vertical and reliable etch-stop on high-k dielectric. This process is successfully applied to the fabrication of the 40-nm HfAlO/TaN gate stack p-MOSFETs with good electrical parameters     

An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS

This paper describes an integrated network-on-chip architecture containing 80 tiles arranged as an 8x10 2-D array of floating-point cores and packet-switched routers, both designed to operate at 4 GHz. Each tile has two pipelined single-precision floating-point multiply accumulators (FPMAC) which feature a single-cycle accumulation loop for high throughput. The on-chip 2-D mesh network provides a bisection bandwidth of 2 Terabits/s. The 15-FO4 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. In a 65-nm eight-metal CMOS process, the 275 mm² custom design contains 100 M transistors. The fully functional first silicon achieves over 1.0 TFLOPS of performance on a range of benchmarks while dissipating 97 W at 4.27 GHz and 1.07 V supply.     

PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Only p-channel sleep transistors and a dual-threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high-threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by up to 77% and 97% as compared to the standard dual-threshold voltage domino logic circuits at the high and low die temperatures, respectively. Similarly, a 22% to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total energy consumption during short idle periods.     

Simulation Study of High-Performance Modified Saddle MOSFET for Sub-50-nm DRAM Cell Transistors

A novel modified saddle MOSFET to be applied to sub-50-nm DRAM technology with high performance and easy scalability is proposed, and its characteristics at a given recess open width of 40 nm is studied by device simulation. The proposed device has$sim$21% lower gate capacitance and lower$I_ off$by two orders of magnitude than a conventional saddle device under nearly the same$I_ on$. In addition, the proposed device showed less threshold voltage sensitivity to the corner shape and lower gate delay time$(CV/I)$by$sim$30% than the conventional recess channel device while keeping nearly the same$I_ off$.     

100% Fill-Factor Aspheric Microlens Arrays (AMLA) With Sub-20-nm Precision

Substitution of a single aspheric microlens (array) for a complex multilens system results in not only smaller size, lighter weight, compacter geometry, and even possibly lower cost of an optical system, but also significant improvement of its optical performance such as better imaging quality. However, fabrication of aspheric microlens or microlens array is technically challenging because conventional technologies used for macro-sized aspheres like single-point diamond milling, and those for spherical microlens like thermal reflow, are not capable of defining a complicated lens profile in an area as small as several to tens of micrometers. Here we solve the problem by using femtosecond laser micro-nanofabrication via two photon polymerization. Not only well-defined single lens, but also 100% filling ratio aspheric microlens array were readily produced. The average error of the lens profile is only 17.3 nm deviated from the theoretical model, the smallest error reported so far.      

Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation

This paper describes a method to numerically calculate the design margin and to estimate the yield associated with the read access failure for sub-100-nm SRAM. Process variations at sub-100 nm not only affect SRAM cells but also periphery circuits, such as the sense amplifier (SA) and the tracking scheme. Simulation that incorporates both SRAM cells and surrounding circuits is either accurate but computationally expensive (comprehensive Monte Carlo simulation), or overly simple (fixed corner design) and unable to capture crucial statistical variation concern, dominant in sub-100-nm designs. By mathematically combining the separate Monte Carlo simulation results of SRAM cells and each peripheral block, we show that the distribution of the SA input voltage can be estimated accurately in a case where fixed corner simulation underestimates by 19%. We also present the yield equation by combining the SA input voltage and the SA offset distribution, which can be used to choose the design point. In addition, yield sensitivities are derived from the yield data to make sure that the yield has good dependence to design variables.      

High-speed monolithically integrated silicon photoreceivers fabricated in 130-nm CMOS technology

A complementary metal-oxide-semiconductor (CMOS) monolithically integrated photoreceiver is presented. The circuit was fabricated in a 130-nm unmodified CMOS process flow on 2-/spl mu/m-thick silicon-on-insulator substrates. The receiver operated at 8 Gb/s with 2-dBm average input optical power and a bit error rate of less than 10/sup -9/. The integrated lateral p-i-n photodetector was simultaneously realized with the amplifier and had a responsivity of 0.07 A/W at 850 nm. The measured receiver sensitivities at 5, 3.125, 2, and 1 Gb/s, were -10.9, -15.4, -16.5, and -19 dBm, respectively. A 3-V single-supply operation was possible at bit rates up to 3.125 Gb/s. The transimpedance gain of the receivers was in the range 53.4-31 dB/spl Omega/. The circuit dissipated total power between 10 mW and 35 mW, depending on the design.     

Improved electrical and reliability Characteristics of HfN--HfO/sub 2/-gated nMOSFET with 0.95-nm EOT fabricated using a gate-first Process

By using a high-temperature gate-first process, HfN--HfO/sub 2/-gated nMOSFET with 0.95-nm equivalent oxide thickness (EOT) was fabricated. The excellent device characteristics such as the sub-1-nm EOT, high electron effective mobility (peak value /spl sim/232 cm/sup 2//V/spl middot/s) and robust electrical stability under a positive constant voltage stress were achieved. These improved device performances achieved in the sub-1-nm HfN--HfO/sub 2/-gated nMOSFETs could be attributed to the low interfacial and bulk traps charge density of HfO/sub 2/ layer due to the 950/spl deg/C high-temperature source/drain activation annealing process after deposition of the HfN--HfO/sub 2/ gate stack.     

Direct Evaluation of Gate Line Edge Roughness Impact on Extension Profiles in Sub-50-nm n-MOSFETs

In this paper, the impact of gate line edge roughness (LER) on two-dimensional carrier profiles in sub-50-nm n-MOSFETs was directly evaluated. Using scanning tunneling microscopy (STM), it was clearly observed that the roughness of extension edges induced by gate LER strongly depended on the implanted dose, pockets, and coimplantations. Impurity diffusion suppressed by a nitrogen (N) coimplant enhanced the roughness of the extension edges, which caused fluctuations in the device performance. The expected effect based on the carrier profiles measured by STM of the N coimplant on the electrical performance of the n-MOSFETs was verified