共查询到20条相似文献,搜索用时 0 毫秒
1.
We proposed a new bulk FinFET that has a p+/n+ poly-Si gate consists of p+ region near the source and n+ region near the drain and analyzed current-voltage characteristics and electric field profiles of 50-nm devices by changing the n+ poly-Si gate length (Ls). For given gate length (Lgles50 nm) and fin body width (Wfinles30 nm), Ls was designed to satisfy the I off requirement (i.e., 1 fA) of DRAM cell. Optimum Ls /Lg of 30-nm device was ~0.4 at a Wfin of 10 nm and ~0.2 at a Wfin of 15 nm 相似文献
2.
Rittenhouse C.E. Mansfield W.M. Kornblit A. Cirelli R.A. Tomes D. Celler G.K. 《Electron Device Letters, IEEE》1995,16(7):322-324
We report the experimental results of the first MOSFET's ever fabricated using a laser plasma-source X-ray stepper. The minimum gate length of these transistors is 0.12 μm with an effective channel length of 0.075 μm. These transistors were patterned using a mix-and-match lithography scheme where the gate level was printed using a 1.4 nm plasma-source X-ray stepper while the other layers were patterned using optical lithography 相似文献
3.
Faure-Muret N. Baillargeat D. Verdeyme S. GaliLre J. Estebe E. Ghesquiers J.-P. Bernard F. 《Microwave and Wireless Components Letters, IEEE》2005,15(5):354-356
A low insertion loss 2.2% bandwidth two-pole cavity filter was fabricated at 60 GHz by bonding metallized lids on each side of a 250-/spl mu/m silicon substrate. The lids are made by dry etching of a 500-/spl mu/m silicon substrate. The same process is used to etch via holes on the intermediate substrate. The position of these via holes fixes the external coupling and the coupling between the resonators. The measured unloaded quality factor is lied on the height of the cavity (1.05 mm) and is around 1100. 相似文献
4.
《Electron Devices, IEEE Transactions on》2009,56(9):1862-1872
5.
Sub-100-nm vertical MOSFET with threshold voltage adjustment 总被引:1,自引:0,他引:1
Sub-100-nm vertical MOSFET has been developed for fabrication with low cost processing. This is the first vertical MOSFET design that combines 1) a vertical LDD structure processed with implantation and diffusion steps, 2) high-pressure oxide growing at source/drain (S/D) regions to reduce the gate overlapped capacitances, and 3) threshold voltage adjustment with a doped APCVD film. The drive current per unit channel width and S/D punch-through voltage are higher than that of previously published vertical MOSFETs. Fabrication processes are well established, and equipment of the 1 μm CMOS generation can be used to fabricate sub-100-nm channel length MOSFETs with good electrical characteristics and high performance 相似文献
6.
n+/p+ Gate Bulk FinFETs With Locally Separated Channel Structure for Sub-50-nm DRAM Cell Transistors
Han-A-Reum Jung Ki-Heung Park Jong-Ho Lee 《Electron Device Letters, IEEE》2007,28(12):1126-1128
We proposed a new p+/n+ poly-Si gate bulk fin-type field-effect transistor that has two channel fins separated locally by a shallow trench filled with oxide or p+ polygate. Key device characteristics were investigated by changing the n+ poly-Si gate length La, the material filling the trench, and the width and length of the trench at a given gate length Lg. It was shown that the trench filled with p+ poly-Si gate should not be contacted with the source/drain diffusion region to achieve an excellent Ion/Ioff (> 1010) that is suitable for sub-50-nm dynamic random access memory cell transistors. Based on the aforementioned device structure, we designed reasonable Ls/Lg and channel fin width Wcfin at given Lg 's of 30, 40, and 50 nm. 相似文献
7.
《Electron Device Letters, IEEE》1987,8(6):266-268
Subhalf-micrometer p-channel MOSFET's with ultra-thin gate oxide (3.5 nm) have been fabricated using X-ray lithography and electron cyclotron resonance (ECR) plasma etching. The fabricated MOSFET's with 0.2-µm channel lengths show long-channel behavior and extremely high (200 mS/mm) transconductance. 相似文献
8.
Ultrathin oxides (1-3 nm) are foreseen to be used as gate dielectric in complementary-MOS technology during the next ten years. Nevertheless, they require new approaches in modeling and characterization due to the onset of quantum effects. Predicting device characteristics including quantum effects requires solving of Schroumldinger's equation together with Poisson's equation. In this paper, Poisson's equation is solved in two dimensions (2-D) over the entire device using Green's function approach, while Schroumldinger's equation is decoupled using triangular-potential-well approximation. The carrier density thus obtained is included in the space-charge density of Poisson's equation to obtain quantum-carrier confinement effects in the modeling of sub-100-nm MOSFETs. The framework also consists of the effects of source/drain-junction curvature and depth, short-channel effects, and drain-induced barrier-lowering effect. The 2-D potential profiles thus obtained with above said effects form the basis for an estimation of threshold voltage. Using this potential distribution, the transfer characteristics of the device are also evaluated. The method presented is comprehensive in the treatment, as it neither requires self-consistent numerical modeling nor it contain any empirical or fitting expression/parameter to provide formulation for quantized-carrier effect in the inversion layer of MOSFETs. The results obtained show good agreement with available results in the literature and with simulated results, thus proving the validity of our model 相似文献
9.
A physical model and a computer simulation program for nanoscale ballistic SOI MOSFETs are developed. The model includes transistor parameters such as the type and level of doping in the source and drain regions, gate length, Si and gate-oxide thicknesses, spacer length, gate-material work function, etc. Transistor performance is characterized in terms of transconductance, subthreshold slope, on- and off-state drain currents, gate–source overlap capacitance, etc. The software enables one to optimize the transistor parameters. 相似文献
10.
Wakabayashi H. Ueki M. Narihiro M. Fukai T. Ikezawa N. Matsuda T. Yoshida K. Takeuchi K. Ochiai Y. Mogami T. Kunio T. 《Electron Devices, IEEE Transactions on》2002,49(1):89-95
Sub-50-nm CMOS devices are investigated using steep halo and shallow source/drain extensions. By using a high-ramp-rate spike annealing (HRR-SA) process and high-dose halo, 45-nm CMOS devices are fabricated with drive currents of 650 and 300 μA/μm for an off current of less than 10 nA/μm at 1.2 V with Toxinv =2.5 nm. For an off current less than 300 nA/μm, 33-nm pMOSFETs have a high drive current of 400 uA/μm. Short-channel effect and reverse short-channel effect are suppressed simultaneously by using the HRR-SA process to activate a source/drain extension (SDE) after forming a deep source/drain (S/D). This process sequence is defined as a reverse-order S/D (R-S/D) formation. By using this formation, 24-nm nMOSFETs are achieved with a high drive current of 800 μA/μm for an off current of less than 300 μA/μm at 1.2 V. This high drive current might be a result of a steep halo structure reducing the spreading resistance of source/drain extensions 相似文献
11.
Eun Young Park Jin Sun Park Tae-Dong Kim Kwang-Sup Lee Hyun Seok Lim Jong Sun Lim Changjin Lee 《Organic Electronics》2009,10(5):1028-1031
We report on the performance of ink-jet-printed n-type organic thin-film transistors (OTFTs) based on a C60 derivative, namely, C60-fused N-methyl-2-(3-hexylthiophen-2-yl)pyrrolidine (C60TH-Hx). The new devices exhibit excellent n-channel performance, with a highest mobility of 2.8 × 10?2 cm2 V?1 s?1, an IOn/IOff ratio of about 1 × 106, and a threshold voltage of 7 V. The C60TH-Hx films show large crystalline domains that result from the influence of an evaporation-induced flow, thus leading to high electron mobility in the ink-jet-printed devices. 相似文献
12.
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS 总被引:3,自引:0,他引:3
Vangal S.R. Howard J. Ruhl G. Dighe S. Wilson H. Tschanz J. Finan D. Singh A. Jacob T. Jain S. Erraguntla V. Roberts C. Hoskote Y. Borkar N. Borkar S. 《Solid-State Circuits, IEEE Journal of》2008,43(1):29-41
This paper describes an integrated network-on-chip architecture containing 80 tiles arranged as an 8x10 2-D array of floating-point cores and packet-switched routers, both designed to operate at 4 GHz. Each tile has two pipelined single-precision floating-point multiply accumulators (FPMAC) which feature a single-cycle accumulation loop for high throughput. The on-chip 2-D mesh network provides a bisection bandwidth of 2 Terabits/s. The 15-FO4 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. In a 65-nm eight-metal CMOS process, the 275 mm2 custom design contains 100 M transistors. The fully functional first silicon achieves over 1.0 TFLOPS of performance on a range of benchmarks while dissipating 97 W at 4.27 GHz and 1.07 V supply. 相似文献
13.
Bliznetsov V.N. Bera L.K. Haw Yun Soo Balasubramanian N. Kumar R. Guo-Qiang Lo Won Jong Yoo Chih Hung Tung Linn L. 《Semiconductor Manufacturing, IEEE Transactions on》2007,20(2):143-149
Etching of TaN gates on high-k dielectrics (HfO2 or HfAlO) is investigated using HBr/Cl2 chemistry in a decoupled plasma source (DPS). The patterning sequence includes 248-nm lithography, plasma photoresist trimming, etching of a SiN-SiO2 hard mask, and photoresist stripping, followed by TaN etching. TaN etching is studied by design of experiment (DOE) with four variables using a linear model with interactions. It is found that at a fixed substrate temperature and wafer chuck power, etch critical dimensions (CD) gain decreases with decreasing HBr/Cl2 flow rate ratio and pressure and with increasing source power and total gas flow rate. Based on these DOE findings, subsequent optimization is performed and a three-step etching process is developed; a main feature of the process is progressively increasing HBr/Cl2 flow rate ratio. The optimized process provides etch CD gain within 2 nm and gate profile close to vertical and reliable etch-stop on high-k dielectric. This process is successfully applied to the fabrication of the 40-nm HfAlO/TaN gate stack p-MOSFETs with good electrical parameters 相似文献
14.
Wei Yuan Lingping Zeng Taochang Zhang Yuanyuan Zhou Jianchuan Wang Shangkun Jiang Li Li Qiang Liao Zidong Wei 《Advanced functional materials》2023,33(36):2307041
As a key component of low-cost anion exchange membrane fuel cells (AEMFCs), anion exchange membranes (AEMs) are far from commercial application, because of dissatisfactory alkaline stability and conductivity. Herein, a new insight is proposed to prepare high performance AEMs by constructing of confined ion channel. With an intermediate oligomer produced before the main copolymerization, novel poly(vinyl-carbazolyl aryl piperidinium) AEMs with confined sub-2-nm ion channel are successfully prepared. The unique sub-2-nm ion channel enable membranes ultrahigh hydroxide conductivity of 261.6 mS cm−1, and the state-of-the-art chemical stability over 5000 h. Moreover, the AEMs also exhibit good mechanical stability with lower water uptake and dimensional swelling. Based on the as-prepared AEMs and ionomer, fuel cells exhibit outstanding peak power density of 1.8 and 0.2 W cm−2 with Pt-based catalysts and completely non-precious metal catalysts, respectively. 相似文献
15.
Zhiyu Liu Kursun V. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(12):1311-1319
A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Only p-channel sleep transistors and a dual-threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high-threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by up to 77% and 97% as compared to the standard dual-threshold voltage domino logic circuits at the high and low die temperatures, respectively. Similarly, a 22% to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total energy consumption during short idle periods. 相似文献
16.
《Electron Device Letters, IEEE》2006,27(9):759-761
A novel modified saddle MOSFET to be applied to sub-50-nm DRAM technology with high performance and easy scalability is proposed, and its characteristics at a given recess open width of 40 nm is studied by device simulation. The proposed device has$sim$ 21% lower gate capacitance and lower$I_ off$ by two orders of magnitude than a conventional saddle device under nearly the same$I_ on$ . In addition, the proposed device showed less threshold voltage sensitivity to the corner shape and lower gate delay time$(CV/I)$ by$sim$ 30% than the conventional recess channel device while keeping nearly the same$I_ off$ . 相似文献
17.
《Circuits and Systems II: Express Briefs, IEEE Transactions on》2008,55(9):907-911
18.
《Photonics Technology Letters, IEEE》2009,21(20):1535-1537
19.
Csutak S.M. Schaub J.D. Wu W.E. Shimer R. Campbell J.C. 《Lightwave Technology, Journal of》2002,20(9):1724-1729
A complementary metal-oxide-semiconductor (CMOS) monolithically integrated photoreceiver is presented. The circuit was fabricated in a 130-nm unmodified CMOS process flow on 2-/spl mu/m-thick silicon-on-insulator substrates. The receiver operated at 8 Gb/s with 2-dBm average input optical power and a bit error rate of less than 10/sup -9/. The integrated lateral p-i-n photodetector was simultaneously realized with the amplifier and had a responsivity of 0.07 A/W at 850 nm. The measured receiver sensitivities at 5, 3.125, 2, and 1 Gb/s, were -10.9, -15.4, -16.5, and -19 dBm, respectively. A 3-V single-supply operation was possible at bit rates up to 3.125 Gb/s. The transimpedance gain of the receivers was in the range 53.4-31 dB/spl Omega/. The circuit dissipated total power between 10 mW and 35 mW, depending on the design. 相似文献
20.
In this paper, we investigate the impact of fin-shape, dimension, and geometry of tapered FinFET with 5-nm node (N5) technology using TCAD simulation. Fixed gate length (LG) of 9 nm, spacer length (LSP) of 7 nm, and bottom fin-width (FWB) of 6 nm were used. The other parameters, such as top fin-width (FWT) and fin-height (FH) were modulated to see the impact on the electrical characteristic and physical behaviors of the device. The simulation results show that increasing FH can enhance the saturation current (ISAT) effectively. However, the threshold voltage (VTH) will suffer so much. In addition, a higher FH means that a larger aspect ratio, thus it is not easy to fabricate in the manufacturing process. On the other hand, the saturation current can be improved by widening FWB. Nevertheless, it may not be a good choice because a wider FWB lets a larger cross-section device area for epitaxy source and drain. Tuning FWT may be the best choice to have a current gain. Additional 1 nm FWT can enhance approximately 30% of the saturation current. Moreover, the VTH has no significant impact and it is good for source-drain epitaxy. By careful control of FH and FWT, the device performance can be predicted very well. As the results, Moore's law still can work even in N5 CMOS technology. 相似文献