Foreword Wafer-Level Packaging

The four papers in this special section focus on wafer-level packaging. The selected papers cover the state-of-the-art and future development trends for wafer level chip scale packages (WLCSPs) by the leading institutes and industries operating in this field.     

圆片级封装技术

圆片级封装(Wafer-LevelPackaging,WLP)已成为先进封装技术的重要组成部分,圆片级封装能够为芯片封装带来批量加工的规模经济效益。在圆片规模上开始加工,结束于芯片规模的圆片级封装技术将在面型阵列倒装芯片的封装中得到日益广泛的应用。圆片级封装加工将成为业界前端和后端之间的高性能衔接桥梁。综述了圆片级封装的技术及其发展趋势。     

晶圆片级芯片规模封装技术(WLCSP)

本文主要介绍了一种新型的 CSP 高级封装——晶圆片级芯片规模封装技术(WLCSP)及其特点,并简述了 CSP 封装的主要特点及发展前景。     

Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs

Micro-springs for integrated circuit test and packaging are demonstrated as soldered flip chip interconnects in a direct die to printed circuit board package. The spring interconnects are fabricated with thin film metallization as the last step in a wafer-scale process. The z-compliance of the interconnects can be used to test and/or burn-in parts in wafer form. After the parts are diced from the wafer, the springs then become the first-level (and often the last-level) interconnect between the chip and the board. The xy-compliance of the interconnect enables considerably large die to be soldered to an organic printed circuit board without underfill using a surface mount compatible process. To demonstrate this concept, daisy chain test vehicles were fabricated on die measuring 11.5 mm $times$ 6.5 mm with 48 spring contacts on a 0.8 mm $times$ 0.65 mm grid array, each spring measuring 400 $, mu$m $times$ 100 $mu$m. The parts were placed onto organic boards with screen printed solder paste using a pick and place machine. The parts were reflowed to complete the solder connection to each spring using eutectic and lead-free solder. Assembled parts have undergone ${>}20thinspace 000$ hot plate thermal cycles and ${>}1000$ oven thermal cycles without failure.      

扇出型晶圆级封装中圆片翘曲研究

在扇出型晶圆级封装工艺中,由于芯片材料与塑封料之间的热膨胀系数差异,晶圆塑封过程中必然会形成一定的翘曲.如何准确预测晶圆的翘曲并对翘曲进行控制是扇出型晶圆级封装技术面临的挑战之一.在讨论圆片翘曲问题时引入双层圆形板弯曲理论与复合材料等效方法,提出一套扇出型晶圆级封装圆片翘曲理论模型,并通过有限元仿真与试验测试验证了该翘...     

WLCSP封装技术中的集成无源器件

芯片规模封装技术一直倍受高性能、小形状因素解决方案在各类应用中的关注。芯片规模封装与球栅阵列(BGA)封装之间的区别变得不可分辨,已成为“细间距BGA”的同义词。芯片规模封装成本也是业界关注的焦点之一。芯片规模晶圆级封装是提供小形状、高性能和低成本的最快途径。论述了集成无源器件加工、低成本化的晶圆级芯片规模封装技术。     

A Novel Wafer-Level Hermetic Packaging for MEMS Devices

Some emerging microelectromechanical systems (MEMS) devices such as high-performance inertial sensors and high-speed actuators must be operated in a high vacuum and in order to create this vacuum environment, specific packaging is required. To satisfy this demand, this paper presents a novel method for hermetic and near-vacuum packaging of MEMS devices. We use wafer-level bonding technology to combine with vacuum packaging, simultaneously. For this packaging solution, the wafers with air-guided micro-through-holes were placed on a custom-built design housed in a vacuum chamber maintained at a low-pressure environment of sub-10 mtorr. Packaging structure is then sealed by solder ball reflow process with the lower heating temperature of 300degC to fill up micro-through-hole. Experimental results shown the hermetical packaging technique using solder sealing is adapted to the wafer-level microfabrication process for MEMS devices and can achieve better yield and performance. Thus, this technique is very useful for many applications with high performance and low packaging cost can be obtained due to wafer-level processing.     

Titanium-Based Getter Solution for Wafer-Level MEMS Vacuum Packaging

Ultrahigh-vacuum conditions can be achieved by employing porous absorbent materials such as Ti, Zr, Ta, and Yt. Commercial getters are primarily Zr-based, since Zr possesses the best adsorption characteristics. Titanium is not considered as a candidate, since adsorption of gases by Ti is significantly reduced due to oxidation and other contamination. In the present work, it is demonstrated that the adsorption property of Ti can be substantially enhanced and benchmarked against other Zr-based commercial getters by employing a sacrificial layer such as Ni over Ti, and also by using other surface engineering techniques. It has been confirmed that, in addition to the activation temperature, the vacuum level during getter activation also plays a pivotal role in influencing the adsorption characteristics of Ti. It has been determined that the getter life could be significantly improved by the reversible adsorption characteristic of H₂ gas, facilitating regeneration cycles.     

圆片级真空封装技术在MEMS陀螺中的应用

为维持MEMS硅微陀螺的真空度,利用两次硅-玻璃阳极键合和真空长期维持技术,实现了MEMS硅微陀螺的圆片级真空气密性封装。制作过程包括:先将硅和玻璃键合,在硅-玻璃衬底上采用DRIE工艺刻蚀出硅振动结构;再利用MEMS圆片级阳极键合工艺在10-5 mbar(1 mbar=100 Pa)真空环境中进行封装;最后利用吸气剂实现圆片的长期真空气密性。经测试,采用这种方式制作出的硅微陀螺键合界面均匀平整无气泡,漏率低于5.0×10-8 atm.cm3/s。对芯片进行陶瓷封装,静态下测试得出品质因数超过12 000,并对样品进行连续一年监测,性能稳定无变化。     

金锡键合在薄膜体声波滤波器晶圆级封装中的研究

薄膜体声波滤波器(FBAR)作为一种无源、体积小和耐功率高的器件,被广泛应用于射频信号处理中。晶圆级气密封装作为小型化封装的代表,在各种高可靠性应用场景中占据重要地位。金-金键合和金-锡键合被广泛应用于薄膜体声波滤波器的气密性晶圆级封装中,但金-锡键合在工艺上更易实现。该文针对金-锡键合在气密性晶圆级封装中的应用进行了研究,在保证键合强度的情况下制作了3 GHz滤波器样品,其性能测试一致性良好,可靠性达到要求。     

Planar Microspring—A Novel Compliant Chip-to-Package Interconnect for Wafer-Level Packaging

In this paper, a novel compliant chip-to-package interconnect, planar microspring, is presented in terms of design consideration, wafer-level fabrication process and mechanical characterization. Several spring designs have been evaluated, and results indicate that a $J$-shaped spring design produces a combination of high 3-D compliances and acceptable electrical parasitics. Further, numerical analyses on the $J$ -shaped microspring interconnect examined the dependence of mechanical and electrical performance upon geometry parameters. A wafer-level fabrication flow combining complementary metal oxide semiconductor (CMOS) back-end-of-line (BEOL) process and 3-D surface micromachining technique has been successfully implemented to create planar microspring interconnect prototypes with a fine pitch (100 $mu{rm m}$ ). The mechanical robustness of the prototype interconnects have been evaluated by nanoindentation. Finally, high-frequency electrical simulation suggested that the interconnect application can be extended up to $sim$35 GHz without significant power loss.      

晶圆级多层堆叠技术

随着5G和人工智能等新型基础设施建设的不断推进,单纯通过缩小工艺尺寸、增加单芯片面积等方式带来的系统功能和性能提升已难以适应未来发展的需求。晶圆级多层堆叠技术作为能够突破单层芯片限制的先进集成技术成为实现系统性能、带宽和功耗等方面指标提升的重要备选方案之一。对目前已有的晶圆级多层堆叠技术及其封装过程进行了详细介绍;并对封装过程中的两项关键工艺,硅通孔工艺和晶圆键合与解键合工艺进行了分析;结合实际封装工艺对晶圆级多层堆叠过程中的可靠性管理进行了论述。在集成电路由二维展开至三维的发展过程中,晶圆级多层堆叠技术将起到至关重要的作用。     

超级CSP—一种晶圆片级封装

研究了圆片级芯片尺寸封装。使用再分布技术的圆片级封装制作了倒装芯片面阵列。如果用下填充技术，在再分布层里和焊结处的热疲劳应力可以减小，使倒装芯片组装获得大的可靠性。     

Wafer-Level Modular Testing of Core-Based SoCs

Product cost is a major driver in the consumer electronics market, which is characterized by low profit margins and the use of core-based system-on-chip (SoC) designs. Packaging has been recognized as a significant contributor to the product cost for such SoCs. To reduce packaging cost and the test cost for packaged chips, wafer-level testing (wafer sort) is used in the semiconductor industry to screen defective dies. However, since test time is a major practical constraint for wafer sort, even more so than for package test, not all the scan-based digital tests can be applied to the die under test. We present an optimal test-length selection technique for wafer-level testing of core-based SoCs. This technique, which is based on a combination of statistical yield modeling and integer linear programming, allows us to determine the number of patterns to use for each embedded core during wafer sort such that the probability of screening defective dies is maximized for a given upper limit on the SoC test time. We also present a heuristic method to handle large next-generation SoC designs. Simulation results are presented for five of the ITC'02 SoC Test benchmarks, and the optimal test-length selection approach is compared with the heuristic method.     

不断推进的圆片级三维封装

当减小芯片面积时,3-D封装能减轻互相连接所带来的延迟问题,根据集成电路是否已经进行了3-D互相的设计,描述了3种选择方法。     

金属化布线晶片级测试系统

晶片级测试方法是半导体器件（ＶＬＳＩ）金属化可靠性试验中的一种新方法,本研究在现有设备的基础上进行了一系列的设计和改进,建立了一套同微机控制的晶片级金属化电徒动测试系统,为金属化可靠性测试和在线监测的研究奠定了良好的基础。     

High-Q Above-IC Inductors Using Thin-Film Wafer-Level Packaging Technology Demonstrated on 90-nm RF-CMOS 5-GHz VCO and 24-GHz LNA

High-Q inductors are important for the realization of high-performance, low-power RF-circuits. In this paper, on-chip inductors with Q-factors above 40 have been realized above the passivation of a 90-nm RF-CMOS process using wafer-level packaging (WLP) techniques . The influence of a patterned polysilicon and metal ground shield on the inductor-Q is compared and the influence of highly doped active area underneath the inductors is shown. A 5-15 GHz above-IC balun has been realized on 20 Omegamiddotcm silicon with the use of patterned ground shield. The technology is demonstrated by a low-power 90-nm RF-CMOS 5-GHz VCO with a core current consumption of only 150 muA with a 1.2-V supply, and a 10% tuning range with a worst case phase noise of -111 dBc/Hz at 1-MHz offset. A 24-GHz single-stage common-source low-noise amplifier has been realized, with a noise figure of 3.2 dB, a gain of 7.5 dB, and a low power consumption of 10.6 mW     

Wafer-Level Packaged Light-Emitting Diodes Using Photodielectric Resin

A large area $(hbox{1600} muhbox{m} times hbox{800} muhbox{m})$ high-brightness light-emitting diode (HB LED) employing rearranged metal pads and multipassivation layers is presented. To enlarge the active layer with a smaller mesa area and improve package productivity using large bonding pads, two electrodes were used to fabricate the LED; a primary electrode was in contact with the $n$, $p$-GaN as a conventional LED, and the second electrode was connected to the primary electrode with a passivation layer having photodielectric resin interposed between them. The LED was directly bonded to the metal-core printed circuit board without wire bonding or epoxy molding. The resultant HB LED has a low forward voltage ( $sim$3.2 V at 350 mA) due to the optimized $n$, $p$ -contact scheme, and an optical power of 75 mW with no encapsulation.