Versatile multiplier architectures in fields using the Montgomery multiplication algorithm

Many sequential multipliers for polynomial basis GF(2^k) fields have been proposed using the LSbit and MSbit multiplication algorithm. However, all those designs are defined over fixed size GF(2^k) fields and sometimes over fixed special form irreducible polynomials (AOL, trinomials, pentanomials). When such architectures are redesigned for arbitrary GF(2^k) fields and generic irreducible polynomials, therefore made versatile, they result in high space complexity (gate–latch number), low frequency (high critical path) and high latency designs. In this paper a Montgomery multiplication element (MME) architecture specially designed for arbitrary GF(2^k) fields defined over general irreducible polynomials, is proposed, based on an optimized version of the Montgomery multiplication (MM) algorithm for GF(2^k) fields. To evaluate the proposed MME and prove the efficiency of the MM algorithm in versatile designing, three distinct versatile Montgomery multiplier architectures are presented using this proposed MME. They achieve small gate–latch number and high clock frequency compared to other sequential versatile designs.     

High-performance two''s complement divider

This paper presents a novel area-efficient two's complement high radix divider without affecting the high speed of the radix-2^k structure. In the proposed approach, only the odd values (rather than all the 2^k values) of the quotient digit set are used to generate the multiples of divisor. Moreover, the set of (N+k+1)-bit additions are replaced with a set of few most significant bits (k+2 bits) additions followed by two (N+3)-bit additions only. The new radix-2^k structure has been evaluated for different values of k. It is shown that the silicon area required by the new design could be as low as 15% of that of the conventional two's complement radix-2^k architecture for radix-64 (20% for radix-32) while the speed is nearly the same. Despite that the proposed algorithm is originally developed in order to improve the performance of the two's complement approach, it has also been compared with the redundant SRT algorithm. The area–time ratios of the new radix-16 and radix-32 dividers to that of the SRT divider are equal to 85% and 77%, respectively.     

A general quantitative cryptanalysis of permutation-only multimedia ciphers against plaintext attacks

In recent years secret permutations have been widely used for protecting different types of multimedia data, including speech files, digital images and videos. Based on a general model of permutation-only multimedia ciphers, this paper performs a quantitative cryptanalysis on the performance of these kind of ciphers against plaintext attacks. When the plaintext is of size M×N and with L different levels of values, the following quantitative cryptanalytic findings have been concluded under the assumption of a uniform distribution of each element in the plaintext: (1) all permutation-only multimedia ciphers are practically insecure against known/chosen-plaintext attacks in the sense that only O(log_L(MN)) known/chosen plaintexts are sufficient to recover not less than (in an average sense) half elements of the plaintext; (2) the computational complexity of the known/chosen-plaintext attack is only O(n·(MN)²), where n is the number of known/chosen plaintexts used. When the plaintext has a non-uniform distribution, the number of required plaintexts and the computational complexity is also discussed. Experiments are given to demonstrate the real performance of the known-plaintext attack for a typical permutation-only image cipher.     

On the construction of the unit tight frames in code division multiple access systems under total squared correlation criterion

We focus on the application of unit norm tight frames to design code division multiple (CDMA) systems spreading sequences with constant chip magnitude. An algorithm for the design of the overloaded real-valued signature sets with minimum total-squared-correlation equal to the Welch bound equality (WBE) set is presented. By using this algorithm we solved the open problem of existence of complex-valued WBE sequence sets with constant chip magnitude in the case when K=N+1, where K is the number of active users in the system and N is the processing gain. The normalized cross-correlation between any pair of signatures in a set obtained by the proposed algorithm is either 1/(K-1) or -1/(K-1) corresponding to equiangular sequences. The results are derived in the context of synchronous CDMA systems. Numerical examples for K=5 users for real WBE sequences and for K=4,3 users for complex WBE sequences with constant chip magnitude are provided.     

A simple and efficient block motion estimation algorithm based on full-search array architecture

This paper first presents an array structure using ±1 full-search (FS) architecture as the search engine of block motion estimation which takes advantage of the design regularity of FS. An efficient algorithm named modified gradient-descent search (MGDS) is then introduced based on the proposed architecture. MGDS utilizes an adaptive computation distribution mechanism to efficiently allocate computation of the employed ±1 FS array to blocks or frames of video sequences. Experimental results indicate that MGDS uniformly achieves a higher quality than FS by an amount that is dependent on motion activities of sequences.     

Dependency of thermal spreading resistance on convective heat transfer coefficient

This paper presents a study of the thermal spreading resistance R_th of a small heat source on a conductive substrate subject to bottom-side convective cooling. This problem has been investigated for a very long time and is well covered in the literature. However, instead of using the design curves found in many papers, the results are presented as function of the heat transfer coefficient h. Doing so, a remarkable property is revealed. The thermal resistance is proportional to the logarithm of the reciprocal heat transfer coefficient, for a broad range of at least three decades . This behaviour can be reasonably explained using an approximate one-dimensional heat spreading model. Being dictated by a logarithmic law, the dependency of R_th on h is rather weak. This is made clearer by the temperature profiles at the substrate bottom. Decreasing h leads to a wider spreading and hence a larger surface with the coolant is utilised, which partly compensates the poorer cooling.     

Zero skew clock routing in X-architecture based on an improved greedy matching algorithm

As technology advances into nanometer territory, clock network layout plays an increasingly important role in determining circuit quality indicated by timing, power consumption, cost, power supply noise and tolerance to process variation. To alleviate the challenges to the existing routing algorithms due to the continuous increase of the problem size and the high-performance requirement, X-architecture has been proposed and applied to routing in that it can reduce wirelength and via counts, and thus improves the performance and routability compared with the conventional Manhattan routing. In this paper, we investigate zero skew clock routing using X-architecture based on an improved greedy matching algorithm (GMZSTX). The fitted Elmore delay model is employed to improve the accuracy over the Elmore delay model. The interactions among distance, delay balance and load balance are analyzed. Based on this analysis, an effective and efficient greedy matching scheme is suggested to reduce wire snaking and to get a more balanced clock tree. The proposed algorithm is simple and fast for practical applications. Experimental results on benchmark circuits show that our algorithm (GMZSTX) achieves a reduction of 8.15% in total wirelength, 30.19% in delay and 55.31% in CPU time on average compared with zero skew clock routing in the Manhattan plane (BB+DME-2, which means using the top-down balanced bipartition (BB) method [T.H. Chao, Y.C. Hsu, J.M. Ho, et al., Zero skew routing with minimum wirelength, IEEE Trans. Circuits Syst. II—Analog & Digital Signal Process 39 (11) (1992) 799–814] to generate the tree topology and using the Deferred-Merge Embedding (DME) algorithm [T.H. Chao, Y.C. Hsu, J.M. Ho, et al., Zero skew routing with minimum wirelength, IEEE Trans. Circuits Syst. II—Analog & Digital Signal Process 39 (11) (1992) 799–814] to embed the internal nodes), and reduces delay and CPU time by 17.44% and 62.21% on average over the BB+DME-4 method (which is similar to BB+DME-2, but routing in X-architecture). Our SPICE simulation further verifies the correctness of the resulting clock tree.     

Progress towards high-power, high-brightness neodymium-based thin-disk lasers

The characteristics of thin-disk lasers utilising neodymium-doped gain media are examined both experimentally and theoretically. The properties of the thin-disk geometry are shown to be rather different for these materials compared to the more commonly used ytterbium-doped media. Parametric studies indicate the potential benefits of Nd:GdVO₄ and this is backed-up by initial experimental results. Physical optics modelling is used to map-out routes to high brightness, rather than merely high power. The particular advantages of composite gain media are highlighted.     

Implantable stimulator and recording device for artificial prosthesis control

This paper presents an application-specific integrated circuit (ASIC) consisting of both, a four-channel neural stimulator and a single-channel recording amplifier, along with their digital control and regulated voltage supplies. The ASIC has been designed to be compatible with different types of electrodes although the use of sieve electrodes was considered a priority. The main performances of this ASIC as stimulator are: fully programmability for several stimuli shapes (monophasic, biphasic, arbitrary amplitude/duration pairs for stimulation and recovery phases), wide frequency range (7 Hz to more than 350 Hz with 1 Hz resolution) and high-current range ( in two scales, with 6 bits resolution). Furthermore, any anode can be associated with any cathode, thus improving the spatial selectivity of some electrode types. From the recording viewpoint, the ASIC exhibits very low noise , high CMRR (94 dB) and digitally programmable gain and bandwidth. The overall digital control is designed to control up to 16 stimulation channels and four recording amplifiers using a regular and modular implementation for the analog parts which gives rise to higher ASIC performances with a small increase in area. The system has been integrated using high voltage CMOS technology. “In vitro” experimental results are also presented.     

Space–time codes for quaternary CPFSK systems with large number of receiver antennas

In this letter, novel space–time (ST) trellis codes are developed for quaternary continuous phase frequency shift keying (CPFSK) modulation systems (i.e., ) with large number of receiver antennas in quasi-static fading channels. The ST codes are obtained from the code search algorithm applying the maximizing minimum squared Euclidean distance criterion (MMSEDC). The simulation results show that a significant performance gain can be obtained from the ST codes of the code search algorithms compared to the codes obtained from the delay diversity (DD) scheme for CPFSK modulation systems.     

(Ga,Mn)As on patterned GaAs(0 0 1) substrates: Growth and magnetotransport

A new type of (Ga,Mn)As microstructures with laterally confined electronic and magnetic properties has been realized by growing (Ga,Mn)As films on -oriented ridge structures with (1 1 3)A sidewalls and (0 0 1) top layers prepared on GaAs(0 0 1) substrates. The temperature- and field-dependent magnetotransport data of the overgrown structures are compared with those obtained from planar reference samples revealing the coexistence of electronic and magnetic properties specific for (0 0 1) and (1 1 3)A (Ga,Mn)As on a single sample.     

APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement

The Y architecture has recently received much attention due to its many potential advantages, such as substantially reduced wirelength, power consumption and significantly improved throughput. To fully utilize the virtues of Y architecture, several hexagon/triangle placement (HTP) algorithms suitable for the Y architecture were presented, however the wirelength optimization is not included in the algorithms. Wirelength estimation is fundamental to guide the wirelength optimization process in early design stages. In this paper, we present an accurate and efficient wirelength estimation technique called APWL-Y appropriate for the Y architecture, and especially for HTP floorplanner and placer. The average error of APWL-Y is 4.41% for 1.57 million nets from industrial circuits. When developing APWL-Y, we find out that 3-SMT wirelength is a power function of aspect ratio of bounding box of the given n-pin nets. The time complexity of APWL-Y is O(n). APWL-Y is very effective to guide the wirelength optimization in a HTP placer. Moreover, we develop an efficient HTP algorithm with wirelength optimization driven by APWL-Y estimator. The placement results by our placer subject to different optimization objectives are presented. Compared to the HTP placer with only area optimization, our placer can reduce the wirelength by 54.3% with a small area overhead of 9.07% on average. In addition, we explore the HPWL technique in the Y architecture. To the best of our knowledge, this paper is the first in-depth study on wirelength estimation technique in Y architecture and HTP floorplanning optimization with consideration of interconnects.     

A low-power ADPLL using feedback DCO quarterly disabled in time domain

We propose a low-power ADPLL (all-digital phase-locked loop) using a controller which employs a binary frequency searching method in this paper. Glitch hazards and timing violations which occurred very often in the prior ADPLL designs are avoided by the control method and the modified DCO (digital-controlled oscillator) with multiplexers. Besides, the feedback DCO is disabled half a cycle in every two cycles so as to reduce 25% of dynamic power theoretically. The proposed design is implemented by only using the standard cells of a typical CMOS process. The feature of power saving is verified on silicon to be merely 1.53 mW at a 133 MHz output.     

Correlation between barrier heights and ideality factors of H-terminated Sn/p-Si(1 0 0) Schottky barrier diodes

Schottky barrier diodes (SBDs) were prepared by evaporation on H-terminated p-Si(1 0 0) surfaces. The Si(1 0 0)-H surfaces were obtained by wet chemical etching in diluted hydrofluoric acid. The current–voltage (I–V) characteristics of real SBDs are described by using two fitting parameters that are the effective barrier height (EBH) and ideality factor n. They were determined from I–V characteristics of SBDs (30 diodes) fabricated under experimentally identical conditions. The obtained values of EBHs varied from 0.729 to 0.749 eV, and the values of ideality factors varied from 1.083 to 1.119. The results showed that both parameters of SBDs differ from one diode to another even if they are identically prepared. The EBH distributions were fitted by two Gaussian distribution functions, and their mean values were found to be 0.739 ± 0.003 eV and 0.733 ± 0.001 eV, respectively. The homogeneous barrier height of SBDs was found to be 0.770 eV from the linear relationship between EBHs () and ideality factors (n).     

Barrier studies on porous silk semiconductor dielectric

Barrier integrity of Ta-films deposited using the enhanced coverage by re-sputtering (EnCoRe¹) barrier was investigated on untreated surfaces of blanket porous SiLK^{, 2} semiconductor dielectric (developmental version 7, hereinafter v7). Barrier integrity of a bi-layer EnCoRe Ta(N)/Ta film was studied on single damascene lines using v7 and porous SiLK semiconductor dielectric (developmental version 9, hereinafter v9). On blanket wafers more than 30 nm barrier thickness is necessary to achieve complete pore sealing. Analysis of the sheet resistance showed that when tantalum is deposited, a low resistivity -phase is nucleated on the low-k surface. When deposited onto single damascene structures, EnCoRe Ta(N)/Ta is successful in providing a continuous metallic barrier layer over v7 and v9 semiconductor dielectric lines.     

Small-scale plasticity in thin Cu and Al films

Flow stresses in thin metal films significantly exceed the flow stresses of their bulk counterparts. In order to identify the underlying deformation mechanisms and correlate them with microstructure, we analysed epitaxial and polycrystalline Cu and Al thin films. The films (100–2000 nm thickness) were magnetron sputtered on (0001) -Al₂O₃ single crystals or on nitrided and oxidised (001) Si substrates. For epitaxial films, the flow stress measurements, which were obtained from substrate-curvature tests, agree with predictions from a dislocation-based model [1 and 2], whereas for polycrystalline films the stresses measured for film thicknesses down to 400 nm are much higher than predicted. However, thinner films reveal a plateau in room temperature flow stress. This behavior, as well as the stress–temperature evolution of the various films will be discussed in terms of existing theories for plasticity in thin metal films, and under consideration of recent in situ transmission electron microscopy studies.     

Silicon stencil masks for masked ion beam lithography proximity printing

Silicon membranes with 2 μm to 6 μm thickness and ≈ 10×10 mm² mask field have been fabricated with the help of electrochemical etch stop techniques. The Si foil was coated with 0.3 μm thick PECVD Si₃N₄. Shaped electron beam lithography was done in ARCH (OCG) positive resist. RIE etching into the nitride layer was done with CHF₃/Ar/SF₆. Silicon trench etching was based on Cl₂/Ar/BCl₃ plasma chemistry implementing gas chopping. Ion beam proximity printing of the Silicon stencil mask structures was done with 55 keV Helium ions into 0.4 μm thick AZ PN114 negative resist using the Alpha ion projector of the Society for the Advancements of Microelectronics in Austria in the MIBL (Masked Ion Beam Lithography) mode. Pattern transfer of a mask feature of less than 100 nm diameter (25:1 aspect ratio in the stencil mask) could be demonstrated even for a mask to wafer gap of 1 mm. The prospects of fabricating large area (> 100×100 mm²) Silicon stencil masks for MIBL printing of gate levels for

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ystems (MEMS) is discussed.     

Unreliable sensor grids: coverage, connectivity and diameter

We consider an unreliable wireless sensor grid network with n nodes placed in a square of unit area. We are interested in the coverage of the region and the connectivity of the network. We first show that the necessary and sufficient conditions for the random grid network to cover the unit square region as well as ensure that the active nodes are connected are of the form p(n)r²(n)  log(n)/n, where r(n) is the transmission radius of each node and p(n) is the probability that a node is “active” (not failed). This result indicates that, when n is large, even if each node is highly unreliable and the transmission power is small, we can still maintain connectivity with coverage.

We also show that the diameter of the random grid (i.e., the maximum number of hops required to travel from any active node to another) is of the order . Finally, we derive a sufficient condition for connectivity of the active nodes (without necessarily having coverage). If the node success probability p(n) is small enough, we show that connectivity does not imply coverage.     

Adaptive robust controller design for multi-link flexible robots

Energy-based robust control strategy was proposed in [12] to improve the control performance of the traditional joint PD control by introducing additional control efforts through the evaluation of vibration related variables. Although the energy-based robust controller always guarantees closed-loop stability, it is not easy to find suitable gains of the terms for a satisfactory control performance. In this paper, adaptive energy-based robust control is presented for both closed-loop stability and automatic tuning of the gains of the additional control terms for desired performance. Simulation results are provided to show the effectiveness of the presented approach.