针对一种多模式逻辑单元结构FPGA的工艺映射

结合FPGA设计的特点,提出一种可灵活配置的多模式FPGA逻辑单元结构及对其进行工艺映射的工具VMAP.该工具中除了采用一般的工艺映射算法外,还结合逻辑单元结构特点提出了专门的合并优化算法.该算法基于图的最大基数匹配,将部分查找表进行合并,减小了映射结果的面积开销.实验结果表明.对于标准的测试电路,结合文中的逻辑单元结构和合并算法得到的工艺映射结果平均可以减少15.7%的基本逻辑单元使用个数.     

基于对可编程逻辑块建模的FPGA通用装箱算法

装箱是FPGA工艺映射中的最后一步流程。该文提出了一种全新的对FPGA可编程逻辑块进行功能级建模的方法，并给出了基于此建模的通用性装箱算法FDUPack。实验中应用该建模方法对几种不同类型的FPGA的逻辑块进行建模，并使用装箱算法将大量的测试电路装箱到这些不同的逻辑块中，经过与已有的针对某一特定结构的装箱算法比较，该算法体现了很好的通用性。     

一种基于图模式匹配的逻辑单元映射算法

基于数学中图模式匹配的概念,根据电路特征在于图同构算法中加入图约束条件,研究了针对不同结构的FPGA逻辑单元都能适用的映射算法FDUMap．实验中应用FDUMap将测试电路映射到不同的逻辑单元中,该算法比现有的专用的逻辑单元映射算法通用性更好,而平均性能上仅相差3％。     

CSPack:采用CSP图匹配的新型装箱算法

现代FPGA芯片可编程单元的日益复杂化对装箱提出了更大挑战,为了使依赖硬件结构的装箱过程不断适应芯片结构变化的过程,提出一种基于CSP图匹配的装箱算法CSPack.用配置库来描述芯片可编程逻辑块的各种电路功能,根据配置库并利用CSP图匹配算法进行电路匹配,找出满足约束的子电路,并以指令的形式将子电路映射到可编程逻辑块内.该算法已经应用于复旦大学自主研发的FPGA芯片FDP2008软件流程的装箱模块中,且针对不同芯片系列只需修改描述芯片功能配置的文件就能实现装箱.实验结果表明,与T-VPack算法相比,CSPack算法在时序性能上提升了6.1%,同时可减少1.4%的芯片占用面积.     

基于区域重组的异构FPGA工艺映射算法

传统异构FPGA工艺映射算法一般不打破实现专用功能和查找表功能的子网表之间的层次边界,因而缩小了映射的优化空间.为此提出一种利用区域重组打破单元间层次边界的异构FPGA工艺映射算法.首先利用贪心策略实现FPGA多单元的映射,即优先使用性能好的专用功能单元;然后利用标记锥实现子网表之间的区域重组,打破专用功能单元和查找表之间的层次边界,减小了映射结果的面积和延迟开销.实验结果表明,与公认的ABC中的工艺映射算法相比,该算法能平均减少逻辑单元面积12.2%,减少电路关键路径延时2.5%.     

基于性能驱动的工艺映射算法

用多级逻辑实现控制器的逻辑综合,工艺映射是其中的一个重要步骤。本文叙述的工艺映射算法TTMAP,是在映射过程中考虑了电路的时延与芯片面积等性能因素,在多级逻辑综合中将因子化的逻辑函数映射为CMOS的串并赶电路单元,产生可布图的网表文件。本算法在比利时HMEC研究中心开发,为多级逻辑综合系统MLL中的一个模块。经实例运行,与美国加州大学柏克莱分校的MISⅡ软件相比,本算法的结果较优。     

Library-free映射在电路面积优化中的应用

针对基于单元库映射中因单元电路已预先设计且在映射中不可改变,进而影响电路面积优化的问题,利用Library-free映射中单元电路可以根据相应约束动态生成的特点,提出基于Library-free映射的电路面积优化算法.首先提出利用逻辑努力和逻辑函数表达式实现单元电路面积估算的方法;然后提出以电路面积优化为导向的电路覆盖搜索算法,使得在Library-free映射中,选择有利于电路面积优化的动态单元电路实现电路面积优化.用MCNC电路的测试结果显示,相比于ABC优化工具,该算法在电路面积优化上可以得到更好的结果.     

性能驱动的LUT结构FPGA的工艺映射

提出一个基于性能的针对ＬＵＴ结构ＦＰＧＡ的工艺射算法,该算法的映射的过程中充分利用了网络中节点的属性,通过计算节点的参数,采用线性规划方法给出网络的目标函数和约束条件,把一个电路网络的问题转纯数学的规划问题求解,映射问题转化为节点属性的分配问题,来得到最后的映射结果,与其它算法相比,该算法对面积和时延综合的映射结果较优。     

Dup-Pack:基于CRIS的FPGA装箱方法

设计了一种电路改写指令系统,并在CSPack算法的基础上提出了一种新的FPGA装箱方法Dup-Pack。Dup-Pack只需要改动指令流描述文件,就能实现对不同FPGA芯片的装箱。该方法采用将用户电路网表中的衍生逻辑单元替换为标准逻辑单元,再对标准逻辑单元进行装箱的方式,在实现高级逻辑功能装箱的情况下减少了样本电路总数。实验结果表明Dup-Pack的装箱结果相比较于T-VPack可减少11.26%的面积,在完成相同逻辑功能的情况下,较传统CSPack装箱速度提升2.77倍。     

基于动态标记的FPGA延迟优化算法

DAG－MAP是一个面向延迟优化的FPGA工艺映射算法,其中的标记过程是该算法的核心,文中对原算法中的标记过程进行了研究,提出了一个改进的标记方法,对MCNC标准测试电路所做实验的结果表明,该算法比原算法更为有效,并且算法所用的时间没有明显增加。     

ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs

Technology mapping for Multiplexor (MUX) based field programmable gate arrays (FPGAs) has widely been considered. Here, a new algorithm is proposed that applies techniques from logic synthesis during technology mapping, i.e., the target technology is considered in the minimization process. Binary decision diagrams (BDDs) are used as an underlying data structure combining both structural and functional properties. The algorithm uses local don't cares obtained by a greedy algorithm. To evaluate a netlist, a fast technology mapper is used. Since most of the changes to a netlist are local, re-mapping can also be done locally, allowing a fast but reliable evaluation after each modification. Both area and delay minimization are addressed in this paper. We compare the approach to several previously published algorithms. In most cases these results can be further improved. Compared to SIS, an improvement of 23% for area and 18% for delay can be observed on average.     

TMLNNs：三值／多值逻辑神经元网络

本文提出了具有三值／多值逻辑表达能力的神经元模型,即三值／多值“逻辑与”神经元和三值／多值“逻辑或”神经元,由这种逻辑神经元连接而成的多层神经网络能够实现三值／多值逻辑推理系统。本文还给出了ＴＭＬＮＮｓ的学习算法,从ＴＭＬＮＮｓ网络中容易抽取到三值／多值逻辑规则知识,可以将ＴＭＬＮＮｓ用于三值／多值逻辑规则知识的自动获取,ＴＭＬＮＮｓ模型为神经网络表示逻辑知识提供了理论基础。     

以延时优化为目标的工艺映射驱动的分解方法

逻辑电路的分解影响ＦＰＧＡ工艺映射后目标电路的延迟时间，采用何种分解方式也与映射结果密切相关。为快速有效地缩短电路延时，本文从工艺映射的基础理论出发，提出映射驱动的逻辑分解方法。     

Distributed logic processors trained under constraints usingstochastic approximation techniques

The paper concerns the estimation under constraints of the parameters of distributed logic processors (DLP). This optimization problem under constraints is solved using stochastic approximation techniques. DLPs are fuzzy neural networks capable of representing nonlinear functions. They consist of several logic processors, each of which performs a logical fuzzy mapping. A simulation example, using data collected from an industrial fluidized bed combustor, illustrates the feasibility and the performance of this training algorithm     

Sufficient condition for convergence of a relaxation algorithm inactual single-layer neural networks

Application of the contraction mapping theorem to single-layer feedback neural networks of a gradient-type is discussed. The sufficient condition for stability of a relaxation algorithm in actual continuous-time networks is derived and illustrated with an example. Results showing the stability of a numerical solution obtained with the relaxation algorithm are presented.     

Genetic algorithm design of neural network and fuzzy logic controllers

This paper discusses the design of neural network and fuzzy logic controllers using genetic algorithms, for real-time control of flows in sewerage networks. The soft controllers operate in a critical control range, with a simple set-point strategy governing “easy” cases. The genetic algorithm designs controllers and set-points by repeated application of a simulator. A comparison between neural network, fuzzy logic and benchmark controller performance is presented. Global and local control strategies are compared. Methods to reduce execution time of the genetic algorithm, including the use of a Tabu algorithm for training data selection, are also discussed. The results indicate that local control is superior to global control, and that the genetic algorithm design of soft controllers is feasible even for complex flow systems of a realistic scale. Neural network and fuzzy logic controllers have comparable performance, although neural networks can be successfully optimised more consistently.     

Coverage Optimization for Defect-Tolerance Logic Mapping on Nanoelectronic Crossbar Architectures

Emerging nano-devices with the corresponding nano-architectures are expected to supplement or even replace conventional lithography-based CMOS integrated circuits, while, they are also facing the serious challenge of high defect rates. In this paper, a new weighted coverage is defined as one of the most important evaluation criteria of various defect- tolerance logic mapping algorithms for nanoelectronic crossbar architectures functional design. This new criterion is proved by experiments that it can calculate the number of crossbar modules required by the given logic function more accurately than the previous one presented by Yellambalase et al. Based on the new criterion, a new effective mapping algorithm based on genetic algorithm (GA) is proposed. Compared with the state-of-the-art greedy mapping algorithm, the proposed algorithm shows pretty good effectiveness and robustness in experiments on testing problems of various scales and defect rates, and superior performances are observed on problems of large scales and high defect rates.     

锅炉系统的神经模糊智能控制研究

将神经网络与模糊集相结合形成一类新的智能信息处理方法,利用神经网络的并行运算能力来实现模糊规则的快速推理,并用学习算法在线调整规则。通过在锅炉系统的仿真研究,证明了该系统的良好性能。