The inhomogeneous channel FET: ICFET

Improvement in the operation of field-effect transistors is predicted through the use of various longitudinal inhomogeneous channel resistivity profiles with heavier doping concentration near the source than the drain end of the channel. The inhomogeneous channel field-effect transistor or ICFET is shown to have a marked improvement in cut-off frequency, device gain, output power and gain-bandwidth product regardless of the actual profile providing only that the doping concentration is higher near the source than the drain end of the channel. The various ICFETs analyzed and compared with the homogeneous FET are the following: linear, Gaussian, complementary error function and exponential. Solutions for each of these cases with doping concentration changes of 10 to 1 and 100 to 1 between the source and drain ends were obtained. The linear case with a 100 to 1 change in doping concentration is seen to provide tremendous device operation improvement, i.e. gain or power is improved by a factor of 30·7 and gain bandwidth by a factor of 955.     

DC and analog/RF performance optimisation of source pocket dual work function TFET

We investigate a systematic study of source pocket tunnel field-effect transistor (SP TFET) with dual work function of single gate material by using uniform and Gaussian doping profile in the drain region for ultra-low power high frequency high speed applications. For this, a n⁺ doped region is created near the source/channel junction to decrease the depletion width results in improvement of ON-state current. However, the dual work function of the double gate is used for enhancement of the device performance in terms of DC and analog/RF parameters. Further, to improve the high frequency performance of the device, Gaussian doping profile is considered in the drain region with different characteristic lengths which decreases the gate to drain capacitance and leads to drastic improvement in analog/RF figures of merit. Furthermore, the optimisation is performed with different concentrations for uniform and Gaussian drain doping profile and for various sectional length of lower work function of the gate electrode. Finally, the effect of temperature variation on the device performance is demonstrated.     

Reduction of hot-carrier generation in 0.1-μm recessed channelnMOSFET with laterally graded channel doping profile

To investigate the substrate current characteristics of a recessed channel structure with graded channel doping profile, we have fabricated and simulated the Inverted-Sidewall Recessed-Channel (ISRC) nMOSFET and compared it with a conventional planar nMOSFET. Experimentally, the ISRC nMOSFET shows about 30% reduction of substrate current, even though the drain current is almost the same. At 0.12-μm channel length, the I _SUB/I_DS value of the conventional nMOSFET is measured to be 1.68 times higher than that of the ISRC nMOSFET. Also, using simulation, it is verified that the reduction of electric field at the drain junction of ISRC nMOSFET results from the graded channel doping profile, not from the recessed channel structure     

A laterally graded junctionless transistor

This paper proposes a laterally graded junctionless transistor taking peak doping concentration near the source and drain region, and a gradual decrease in doping concentration towards the center of the channel to improve the I OFF and I ON/I OFF ratio. The decrease of doping concentration in the lateral direction of the channel region depletes a greater number of charge carriers compared to the uniformly doped channel in the OFF-state,which in turn suppresses the OFF state current flowing through the device without greatly affecting the ON state current.     

Graded channel FET's: Improved linearity and noise figure

The characteristics of GaAs field-effect transistors were examined as a function of the channel doping profile in the direction perpendicular to the surface. Theoretical considerations predict that improved device linearity is expected for channel doping profiles with relatively low carrier concentrations near the surface. These predictions are experimentally confirmed by comparison of GaAs FET's fabricated with uniform (flat) and exponentionally varying (graded) carrier concentrations as a function of depth. In addition, the graded devices are observed to exhibit noise figures approximately 1 dB lower than those of uniformly doped devices of the same geometry.     

Hot-hole-induced degradation in depletion-mode n-channel MOSFETs

Injection and trapping of hot holes was studied in n-channel depletion-mode MOSFETs and compared to that in enhancement devices. The rate of device degradation was found to decrease with increasing channel doping. A model is proposed explaining this behaviour from the current transport in the buried channel and from the effect of the channel doping level on the field near the drain.     

倒掺杂沟道MOSFETs的研究

本文研究了一种倒掺杂沟道MOSFET。与传统的MOSFETs不同,这种器件采用沟道表面掺杂浓度低、体内掺杂浓度高的倒掺杂设计。基于Possion方程,建立了线性变掺杂的沟道倒掺杂模型,得出了器件表面电势以及漏极电流的表达式,研究了垂直于沟道方向上倒掺杂的陡峭程度对漏极电流、饱和驱动电流以及表面电势的影响。计算结果与二维仿真软件MEDICI模拟结果相符。     

A model for anomalous short-channel behavior in submicron MOSFETs

Experimental data and simulation results for submicron MOSFETs are reported and used to support a physical explanation for two important anomalies in the dependence of device threshold voltage on channel length. They are the widely observed increase in threshold voltage with decreasing channel length (roll-up), and the more recent observation that the ultimate threshold voltage decrease (roll-off) occurs at a rate which is far in excess of that which can be explained with conventional models of laterally uniform channel doping. A model that attributes roll-up as well as roll-off to lateral redistribution of doping near the source and drain junctions is proposed. This lateral redistribution is caused by crystal defects formed during post-source/drain-implant anneal. The resulting profile consists of an enhancement of background doping adjacent to the junction edge, bounded by a depression of the doping farther into the channel     

On-current modeling of short-channel double-gate (DG) MOSFETs with a vertical Gaussian-like doping profile

An analytic drain current model is presented for doped short-channel double-gate MOSFETs with a Gaussian-like doping profile in the vertical direction of the channel.The present model is valid in linear and saturation regions of device operation.The drain current variation with various device parameters has been demonstrated. The model is made more physical by incorporating the channel length modulation effect.Parameters like transconductance and drain conductance that are important in assessing the analog performance of the device have also been formulated.The model results are validated by numerical simulation results obtained by using the commercially available ATLAS^TM,a two dimensional device simulator from SILVACO.     

A surface potential and quasi-Fermi potential based drain current model for pocket-implanted MOS transistors in subthreshold regime

A subthreshold drain current model for pocket-implanted MOS transistors, incorporating both the drift and diffusion currents, is presented in this paper. In this model, the concept of splitting of the quasi-Fermi energy levels under nonequilibrium condition is used. It is well known that the surface potential based drain current models strongly depend on the potential profile of the channel. For short-channel devices, the end effect at the source and drain ends on the surface potential, and consequently on the drain current, cannot be ignored. The end effect gives rise to a position dependent potential profile, in contrast to a flat 1D profile in a long-channel device; which implies that both the drift and diffusion components are required to be considered for an accurate drain current. The concept of the gradient in the quasi-Fermi level is a convenient way to do so. In this work, a pseudo 2D potential profile which takes into account the vertical field due to the gate and the lateral field due to the source and drain junctions in addition to the difference in the flat-band voltage along the channel is used. Moreover, the mobility and the effective conduction layer depth used are also position dependent since the channel doping varies along the channel. Model predictions are compared with the results predicted by the 2D numerical device simulator DESSIS, and a very good agreement between the two are observed.     

一种非对称双栅应变硅HALO掺杂沟道MOSFET阈值电压解析模型

提出了一种非对称双栅应变硅HALO掺杂沟道金属氧化物半导体场效应管结构.该器件前栅和背栅由两种不同功函数的金属构成,沟道为应变硅HALO掺杂沟道,靠近源区为低掺杂区域,靠近漏区为高掺杂区域.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,分别求解了前背栅表面势、前背栅表面电场及前背栅阈值电压,建立了双栅器件的表面势、表面电场和阈值电压解析模型.详细讨论了物理参数对解析模型的影响.研究结果表明,该器件能够很好的抑制短沟道效应、热载流子效应和漏致势垒降低效应.模型解析结果与DESSIS仿真结果吻合较好,证明了该模型的正确性.     

Investigation of the Electrical and Thermal Performance of SOI MOSFETs with Modified Channel Engineering

In this paper, we present a novel type of channel doping engineering, using a graded doping distribution, that improves the electrical and thermal performance of silicon-on-insulator (SOI) metal–oxide–semiconductor field effect transistors (MOSFETs), according to simulations that we have performed. The results obtained include a reduction in the self-heating effect, a reduction in leakage currents due to the suppression of short-channel effects (SCEs), and a reduction in hot-carrier degradation. We term the proposed structure a modified-channel-doping SOI (MCD-SOI) MOSFET. The main reason for the reduction in the self-heating effect is the use of a lower doping density near the drain region in comparison with conventional SOI MOSFETs with a uniform doping distribution. The most significant reason for the leakage current reduction in the MCD-SOI structure is the high potential barrier near the source region in the weak inversion state. The SCE factors, including the drain-induced barrier lowering, subthreshold swing, and threshold voltage roll-off, are improved. A highly reliable structure is achieved owing to the lower doping density near the drain region, which reduces the peak electric field and the electron temperature.     

Low-Frequency Noise Partition of Asymmetric MOS Transistors Operating in Linear Regime

The low-frequency noise in asymmetric MOS transistors with graded channel doping from the source to the drain can be partitioned by assuming a series connection of two or more transistors along the device's channel length. The partition explains the noise overshoot at gate biases around the threshold voltage of the composite device. Expressions for the input-referred gate noise voltage are obtained and verified.      

Ideal FET doping profile

Using variational calculus it is possible to show, for each MOSFET voltage and device topology, that there exists an ideal drain region doping profile which yields the optimum resistance versus breakdown voltage tradeoff. Because of the inclusion, in the resistance, of the effects of spreading resistance this profile tends to have a higher doping concentration (lower resistivity) at the blocking junction, this point being at or near the point of maximum spreading resistance, a minimum in doping partway into the drain and then asymptotically approach a(1 - X/W)^{-1/2}form as derived by Hu [1] at the edge of the depletion layer. The theory and calculations in this paper compare the Hu profile, a constant profile and our optimum profile for various practical geometries over a range of breakdown voltages. It is shown that the higher the device voltage and the less important the spreading resistance effects, the closer the ideal profile approaches that of Hu. The ideal profile concept applies equally well to other FET or majority carrier (resistive) devices.     

考虑速度过冲效应的亚1／4微米MOSFET器件解析模型

提出了一个考虑速度过冲效应的亚１／４微米ＭＯＳＦＥＴ器件解析模型。亚１／４微米ＭＯＳＦＥＴ靠近源端沟道内电子速度过冲归因于该区域内的强电场。采用源附近电场的弱强阶梯场近似，根据有关弱强阶梯场中速度过冲模拟结果，提出了一个半经验速度过冲因子模型。用此模型和准二维分析方法，得到了解析的漏电流、跨导模型。计算得到的漏电流、跨导与有关实验报导符合较好。速度过冲分析得到的器件速度过冲模型与沟道掺杂浓度的关系得到了有关实验验证。     

非对称HALO-LDD掺杂石墨烯纳米条带场效应管的电学特性研究(英文)

随着器件沟道尺寸的不断缩小,短沟道效应(SCE)和漏致势垒降低效应(DIBL)对常规类MOSFET结构的石墨烯纳米条带场效应管(GNRFET)影响变大,从而引起器件性能下降。文中提出了一种新型采用非对称HALO-LDD掺杂结构的GNRFET,其能够有效抑制器件中SCE和DIBL,改善器件性能。并采用一种量子力学模型研究GNRFET的电学特性,该模型基于二维NEGF(非平衡格林函数)方程和Poisson方程自洽全量子数值解。结合器件的工作原理,研究了GNRFET的电学特性和器件结构尺寸效应,通过与采用其他掺杂结构的GNRFET的电学特性对比分析,发现这种掺杂结构的石墨烯纳米条带场效应管具有更低的泄漏电流、更低的亚阈值斜率和DIBL以     

Graded-junction gate/n- overlapped LDD MOSFET structuresfor high hot-carrier reliability

A newly developed gate/n^- overlapped LDD MOSFET was investigated. The MOSFET was fabricated by an oblique rotating ion implantation technique. A formula for the impurity ion profile was derived to analyze the lowering of substrate current and improvement of the degradation caused by the hot-carrier effect of the MOSFET. It was proved that the impurity ion profile near the drain edge is remarkably graded in the directions along channel and toward substrate even just after the implantation, so that the maximum lateral electric field is relaxed as compared with conventional LDD MOSFETs. Also, the maximum point of the lateral electric field at the drain edge is located apart from the main path of the channel current     

Influence of channel doping-profile on camel-gate field effecttransistors

We report the performance of GaAs camel-gate FETs and its dependence on device parameters. In particular, the performance dependence on the doping-profile of a channel was investigated. In this study, one-step, bi-step, and tri-step doping channels with the same doping-thickness product are employed in camel-gate FETs, while keeping other parameters unchanged, For a one-step doping channel FET, theoretical analysis reveals that a high doping channel would provide a large transconductance which is suitable for logic applications. Decreasing the channel concentration increases the drain current and the barrier height. For a tri-step doping channel FET, it is found that the output drain current and the barrier height remain large and the relatively voltage-independent transconductance is also increased. These are the requirements for the large input signal power amplifiers. A fabricated camel-gate FET with a tri-step doping channel exhibits a large drain current density larger than 750 mA/mm and a potential barrier greater than 1.0 V. Furthermore, the relatively voltage-independent transconductance is as high as 220 mS/mm and the applied gate voltage is up to +1.5 V. A 1.5×100 μm² device is found to have a f_t of 30 GHz with a very low input capacitance     

Nanoscale FinFETs with gate-source/drain underlap

Using two-dimensional numerical device simulations, we show that optimally designed nanoscale FinFETs with undoped bodies require gate-source/drain (G-S/D) underlap that can be effectively achieved via large, doable straggle in the S-D fin-extension doping profile without causing S-D punch-through. The effective underlap significantly relaxes the fin-thickness requirement for control of short-channel effects (SCEs) via a bias-dependent effective channel length (L/sub eff/), which is long in weak inversion and approaches the gate length in strong inversion. Dependence of L/sub eff/ on the S/D doping profile defines a design tradeoff regarding SCEs and S/D series resistance that can be optimized, depending on the fin width, via engineering of the doping profile in the S/D fin-extensions. The noted optimization is exemplified via a well-tempered FinFET design with an 18-nm gate length, showing further that designs with effective underlap yield minimal parasitic capacitance and reduce leakage components such as gate-induced drain leakage current.     

An analytical drain current model for graded channel cylindrical/surrounding gate MOSFET

In the present paper, a comprehensive drain current model incorporating various effects such as drain-induced barrier lowering (DIBL), channel length modulation and impact ionization has been developed for graded channel cylindrical/surrounding gate MOSFET (GC CGT/SGT) and the expressions for transconductance and drain conductance have been obtained. It is shown that GC design leads to drain current enhancement, reduced output conductance and improved breakdown voltage. The effectiveness of GC design was examined by comparing uniformly doped (UD) devices with GC devices of various L₁/L₂ ratios and doping concentrations and it was found that GC devices offer superior characteristics as compared to the UD devices. The results so obtained have been compared with those obtained from 3D device simulator ATLAS and are found to be in good agreement.