Thermo-mechanical finite element analysis in a multichip build up substrate based package design

This paper presents a thermo-mechanical analysis of a multichip module (MCM) package design, with emphasis on the package warpage, thermally induced stress and the second level solder joint reliability. The MCM package contains four flip chips which are mounted on a build up substrate. First, the effect of the positioning of four silicon dice within the MCM package on the warpage of the package is studied. Second, the effect of package dimensions (the heat spreader thickness, the structural adhesive thickness and the substrate thickness) on the maximum residual stress as well as the warpage of the package is performed. Finally, this paper presents a 3D sliced model for solder joint reliability of the MCM assembly. A creep constitutive relation is adopted for the 63Sn/37Pb solder to account for its time and temperature dependence in thermal cycling. The fatigue life of solder joint is estimated by the Darveaux's approach. A series of parametric study is performed by changing the package dimensions. The results show that the largest die tends to experience highest stresses at its corner and has more influence on the warpage of the package than smaller dice. The results also show the most sensitivity factors that affect the package warpage and the second level solder joint reliability are the substrate thickness and the heat spreader thickness. The structural adhesive thickness has no major effect on the package warpage, the maximum von Mises stress of the package and the second level solder joint reliability.     

Thermo-mechanical simulation of PCB with embedded components

In recent years, in order to increase density and performance of electronic boards, components are embedded in internal layers of printed circuit boards (PCBs). The reliability of this new technology has to be investigated to ensure the working of the electronic boards submitted to harsh environment and long mission profiles. To study the thermo-mechanical behavior of these boards, finite element simulations have been performed. It is observed that embedded passive chips are subjected to complex loading during the lamination process, due mostly to shrinkage of the resin, differences in material properties and also because of temperature excursion. The effects of material parameters and of the geometrical configuration are investigated in details. It will be shown that the generated stresses are not critical for the passive chip size considered in the present work.     

Failure analysis and stress simulation in small multichip BGAs

This paper examines one of the common modes of structural failure in multichip ball grid arrays (BGAs), determines its locations within the package structure, relates it to the stresses generated in the reliability tests under which it occurs, and by finite element simulations, determines an explanation for the failure, and finally proposes a method to avoid this failure mechanism. Several designs of multichip BGA substrates were manufactured and production silicon assembled into them. These were all 14 mm×22 mm 119 ball PBGAs. These were subjected to a set of package reliability tests, until some units failed electrical test. The failed units were analyzed and the physical location and shape of the failure was determined in many cases. From this information, the mechanical mode of failure for each unit was determined. In addition there was sufficient information in some of the analyses to provide definite suggestions as to the mechanism of failure. Meanwhile, finite element analysis was performed using simplified representations of the multichip BGAs, in order to find the locations of highest stress, and the expected modes of failure. This data was matched to the failure modes found in the physical analysis. Some novel failure analysis techniques were used to expose the damage in the failed units. A particular failure mode occurred frequently in temperature cycle, and the sites of failure were located by failure analysis. The failure was due to open circuit in the copper tracks in the top layer of the substrate caused by cracking in the solder resist directly underneath the edge of the die attach fillet. Finite element analysis was carried out and the location of the actual failures was found to be a local zone of high tensile stress in the solder resist     

Trench SJ IGBT 的仿真研究

本文对沟槽型超结绝缘栅双极晶体管(trench SJ IGBT)进行了全面的分析,并通过Sentaurus TCAD仿真软件将其与沟槽型场截止绝缘栅双极晶体管(trench FS IGBT)进行了详尽的对比,仿真结果显示,在相同的条件下与trench FS IGBT 相比,trench SJ IGBT 的击穿电压提高了100 V,饱和导通压降降低了0.2 V,关断损耗减少了50%。最后,文章研究了电荷不平衡对trench SJ IGBT 的动静态参数的影响。对各参数和它们对电荷不平衡的灵敏度之间的折中进行了讨论。     

A knowledge-based simulation environment for the early design of multichip modules

A knowledge-based simulation environment is developed to facilitate the early design of Multichip Modules (MCMs). Electrical system performance measures such as module clock frequency, etc. are predicted and analyzed for different interconnect and packaging technologies. Performance-limiting factors such as power dissipation, coupled noise, and simultaneous switching noise are also included in this work. CMOS based MCMs for workstation applications are used to demonstrate the feasibility of the system in development.     

Temperature measurements and thermal modeling of high power IGBT multichip modules for reliability investigations in traction applications

To study the failure mechanisms induced on high power IGBT multichip modules by thermal cycling stress in traction environment, a good knowledge of the temperature distribution and variations on the chips and in the interfaces between the different layers of the packaging is necessary. This paper presents a methodology for contact temperature measurements on chips surface in power cycling conditions and a fast 3D thermal simulation tool for multilayered hybrid or monolithic circuits. The results of static and dynamic thermal simulation of a 1200A–3300V IGBT module are given and compared with the contact temperature measurements results. The investigation has been done within the RAPSDRA (Reliability of Advanced High Power Semiconductor Device for Traction Applications) European project.     

Electrothermal simulation of an IGBT PWM inverter

An electrothermal network simulation methodology is used to analyze the behavior of a full-bridge, pulse-width-modulated (PWM), voltage-source inverter, which uses insulated gate bipolar transistors (IGBTs) as the switching devices. The electrothermal simulations are performed using the Saber circuit simulator and include control logic circuitry, IGBT gate drivers, the physics-based IGBT electrothermal model, and thermal network component models for the power-device silicon chips, packages, and heat sinks. It is shown that the thermal response of the silicon chip determines the IGBT temperature rise during the device switching cycle. The thermal response of the device TO247 package and silicon chip determines the device temperature rise during a single phase of the 60-Hz sinusoidal output. Also, the thermal response of the heat sink determines the device temperature rise during the system startup and after load-impedance changes. It is also shown that the full electrothermal analysis is required to accurately describe the power losses and circuit efficiency     

IGBT模块电流取样电阻模型仿真

绝缘栅双极型晶体管(IGBT)模块作为一款重要的半导体功率开关器件,现已被广泛应用。然而,IGBT在工作中常会因为各种原因导致其失效,如过压、过流、过热等。为了更好的监测IGBT的工作状态,本文采用取样电阻来检测电流,通过对IGBT模块DBC底板集成的分流采样电阻进行建模与仿真,研究取样电阻的测量特性。     

Testing multichip modules

Too complex to be tested as a chip and too packaged to be probed like a board, the multichip module presents a new set of challenges to the test engineer. The author describes how, until dedicated testers are developed, applying board-type tests using an IC tester will prove to be the most effective test methodology     

多芯片组件的检测方法

多芯片组件的测试分三类：基板、ＩＣ裸芯片和组件测试。各类测试都有若干种不同的测试方法，如多层基板的电学测试法，光学测试法；ＩＣ裸芯片的内建自测试法，界面扫描法；组件的全功能测试法，有限功能测试法等。本文对这些方法的优点与不足处，测试设备使用时应注意的事项，适用对象等作了详尽的介绍，还对各种类似方法的功能作了比较。     

Design of multichip modules

The process and pitfalls of multichip module (MCM) design, including the constraints, tradeoffs, figures of merit, and considerations which make MCM design a unique interdisciplinary challenge are discussed. The MCM must provide the proper operating environment for the chips it contains. It must also fit the constraints of the system in which it is contained. It must be manufacturable, testable, and repairable. The many aspects of MCM design are described, starting with system benefits, then system and MCM partitioning, chip environment, system constraints, and infrastructure/manufacturing issues     

Demonstration of RSFQ digitizer on a multichip module

A 1-b slice of a rapid single-flux quantum (RSFQ) digitizer with interchip communications on a multichip module (MCM) has been successfully designed, fabricated using 3-μm Nb technology, and tested. We placed a flash comparator followed by an enable switch and an MCM transmitter circuit on one side of the chip, and an MCM receiver circuit followed by a memory buffer on the other side. The 5 × 5 mm chip was flip-chip mounted on a 10 × 10 mm carrier chip by a solder bump technique. During circuit operation, the comparator output signal and the clock signal left the chip, moved to the carrier chip, and returned back to the chip into the memory buffer. We operated the circuit with a beat frequency technique where the data input frequency was slightly off from the clock frequency by the beat frequency of 10 kHz. The circuit operated correctly up to 10 GHz. The critical circuit operation margin was observed to be the bias current to the SQUID in the MCM receiver circuit and was about ±6% at 10 GHz     

当代多芯片组装技术

与传统的封装技术相比，多芯片组装技术具有更高的封装密度和更优异的性能。多芯片组装技术正在蓬勃发展，归当代的代表性技术。     

Microwave photonic multichip modules

The increasing use of microwave frequencies and gigabit per second transmission rates in optical-fibre systems and the corresponding interest in using optical techniques for microwave systems are spurring the development of microwave photonic circuits. Despite a considerable investment in research and development, monolithic photonic and optoelectronic integrated circuits have not entered into widespread production. The paper illustrates that for the majority of microwave photonic applications, the multichip module approach is better suited in terms not only of performance but also of economy and of ease of manufacture. The advantages of the silicon optical bench for optoelectronic integration are discussed in depth. It is then shown how, with suitable modifications, silicon-based multichip modules can also provide interconnections to microwave devices, thus creating microwave photonic multichip modules     

The use of laminate multichip modules for the packaging of 9-GHzdigital multichip circuits

An investigation of the high-frequency performance of laminate multichip module (MCM-L) technology was undertaken with the goal of demonstrating its appropriateness for the development of digital radar receivers operating in the X band (8 to 12 GHz). A seven-chip circuit using digital components on a Gore MCM-L was successfully tested up to 9.6 GHz. An analog-to-digital converter on an MCM-L was successfully tested up to 6 GHz. An extensive characterization of the MCM-L technology using both simulations and measurements was performed to formulate a set of design guidelines for high-frequency applications. A novel dielectric-encapsulated MCM-to-MCM interconnect scheme was proposed and tested     

微波多芯片模块技术

论述了微波多芯片模块（MMCM）技术的发展历史、应用领域及工艺进展。着重从芯片互连、基板材料及封装设计等方面讨论了该技术的发展前景,并对我国微电子和MMCM封装技术提出几点建议。     

Development of a high density pixel multichip module at Fermilab

At Fermilab, both pixel detector multichip module and sensor hybridization are being developed for the BTeV experiment. The module is composed of three layers. The lowest layer is formed by the readout integrated circuits (ICs). The backs of the ICs are in thermal contact with the supporting structure, while the tops are flip-chip bump bonded to a pixel sensor. A low mass flex-circuit interconnect is glued on the top of this assembly, and the readout IC pads are wire-bonded to the circuit. The BTeV pixel detector is based on a design relying on this hybrid approach. This method offers maximum flexibility in the development process, choice of fabrication technologies, and the choice of sensor material. This paper presents strategies to handle the required data rate and performance characteristics of the pixel module prototypes     

A new equivalent circuit model of IGBT for simulation of current sensors

A new equivalent circuit model for insulated gate bipolar transistor is presented. It takes into account both electron and hole conduction in sensors and is incorporated with SPICE3 for the simulation of three types of current sensors, namely active, bipolar, and MOS sensors. It adopts a multiMOS model to include the doping variation in the MOS body. The results agree well with the current sensing measurements within an average error of 4.4%.     

Polymer dielectrics for multichip module packaging

The polymer dielectrics used to fabricate multichip modules are discussed. Numerous relevant properties of the dielectrics are compared and contrasted. It is shown that the suitability of a specific material is highly dependent on the process chosen to fabricate the structure and the intended application of the module. The material properties of the polymer dielectric must be taken into account when designing the fabrication process in order to exploit the advantages and control the disadvantages that all imperfect materials are bound to have