Characterization of low 1/f noise in MOS transistors

By careful processing MOS transistors have been fabricated with a low value of the interface states density (2 × 10¹⁰/cm²eV). Consequently the1/fnoise in these devices is low and in the same order of magnitude as for junction FETs. The experimental values of the equivalent noise voltage and the equivalent noise current are compared to an expression derived from straight physical arguments. From the comparison it is concluded that the noise equivalent voltage in saturated operation is proportional to the effective gate voltage, the interface state density, and inversely proportional to the gate input capacitance. Moreover, it is concluded that a proper heat treatment not only reduces the number of states but also removes the near bandedge peaks, which usually appear in the trap distribution function.     

Temperature dependence of hot-carrier degradation in silicon-on-insulator dynamic threshold voltage MOS transistors

The authors analyze the influence of temperature on hot-carrier degradation of silicon-on-insulator (SOI) dynamic threshold voltage MOS (DTMOS) devices. Both low and high stress gate voltages are used. The temperature dependence of the hot-carrier effects in DTMOS devices is compared with those in SOI partially depleted (PD) MOSFETs. Possible physical mechanisms to explain the obtained results are suggested. This work shows that even if the stress gate voltage is low, the degradation of DTMOS devices stressed at high temperature could be significant.     

The influence of constructive parameters on the threshold voltage of nanodimensional p-Channel SOI MOS transistors

The influence of the thickness of the silicon film and hole concentration in the p-channel nanodimensional MOS transistor based on the SOI structure is considered. The formulas for the computation of these dependences are derived and graphic dependences are presented.     

1/f noise in n-channel silicon-gate MOS transistors

It is found that equivalent gate noise power for l/f noise in n-channel silicon-gate MOS transistors at near zero drain voltage at room temperature is empirically described by two noise terms, which vary asK_{1}(q/C_{ox}) (V_{G} -V_{T})/f and K_{2}(q/C_{ox})^{2}/f, where V_{G}is gate voltage, VTis threshold Voltage, and Coxis gate-oxide capacitance per unit area. Unification of carrier-density fluctuation (McWhorter's model)and mobility fluctuation (Hooge's model) can account for the experimental data. The comparison between the theory and experiment shows that the carrier fluctuation term K2is proportional to oxide-trap density at Fermi-level. The mobility fluctuation term K1is correlated to K2, being proportional toradic K_{2}. The origin of this correlation is yet to be clarified.     

Hole-induced 1/f noise increase in MOS transistors

This paper presents experimental evidence for hole-generated 1/f noise traps in gate oxides near the MOS interface. To clarify the microscopic nature of noise traps, 1/f noise is measured in Si MOS transistors in which carriers are intentionally injected into the gate oxides. It was found that 1/f noise increases more rapidly after drain avalanche hot-carrier injection than after channel hot-electron injection. A rapid noise increase is also observed after X-ray irradiation. These results show that the increase in 1/f noise is closely related to holes. We propose a model in which the reaction between holes and oxygen vacancies near the interface creates noise traps, i.e., E' centers and fixed positive charges     

Low frequency noise measurements on silicon-on-sapphire (SOS) MOS transistors

Measurements of the equivalent input noise are performed on P-channel silicon-on-saphire, metal-oxide-semiconductor (SOSMOS) transistors as a function of the silicon layer bias voltage with respect to the source. Devices are operated in the ohmic region of the characteristics so that the results are easier to analyse. The results show a high degree of dispersion in the noise characteristics for the different tested devices all originated from the same silicon on sapphire wafer. We conclude that a dispersion of the silicon-sapphire interface properties, such as SRH centers density or fixed positive charge, exists on the wafer. From one specific device, we calculate a fixed positive silicon-sapphire interface charge (about 4 × 10¹¹ cm^?2) and a high density (about 5 × 10¹¹ cm^?2) SRH centers localized near the silicon-sapphire interface.     

Measurement of threshold voltages of thin-film accumulation-modePMOS/SOI transistors

Accumulation-mode PMOS transistors on SOI (silicon on insulator) are characterized by several conduction mechanisms. Measurements of the threshold voltage corresponding to each of them are presented for the first time. An intuitive physical interpretation of their dependence on the front- and back-gate voltages is also given     

Surface states and 1/f noise in MOS transistors

Surface-state density in n-channel MOS transistors operating in the inversion mode has been determined from the channel conductance and related to 1/fnoise in these devices. It has been found that the noise is proportional to the surface-state density at the Fermi level. The surface orientation and temperature affect the noise output only indirectly, through their influence on the surface-state density and the position of the Fermi level at the surface.     

White noise in MOS transistors and resistors

The theoretical and experimental results for white noise in the low-power subthreshold region of operation of an MOS transistor are discussed. It is shown that the measurements are consistent with the theoretical predictions. Measurements of noise in photoreceptors-circuits containing a photodiode and an MOS transistor-that are consistent with theory are reported. The photoreceptor noise measurements illustrate the intimate connection of the equipartition theorem of statistical mechanics with noise calculations     

Low-frequency noise in depletion-mode SIMOX MOS transistors

Low-frequency noise measurements in depletion-mode SIMOX MOSFETs are reported. A simple model provides a reliable interpretation of the low-frequency noise in multi-interface depletion-mode transistors. An experimental procedure to separate noise contributions of front and back interfaces from noise due to bulk carrier fluctuations is described. The noises generated in the thin Si film and at the two Si-SiO₂ interfaces can be identified and characterized independently in terms of bulk properties and interface trap densities. Single-level traps at the back interface and defects in the volume are detected in high-temperature annealed materials     

Improvement of SOI MOS current-mirror performances usingserial-parallel association of transistors

The serial-parallel association of SOI MOSFETs proves to be useful for increasing the breakdown voltage and the early voltage of transistor structures. This permits one to realise current mirrors with an output-to-input current ratio close to unity in the weak, moderate and strong inversion regimes of the MOSFETs     

Increased drain saturation current in ultra-thinsilicon-on-insulator (SOI) MOS transistors

Based on substrate-charge considerations, an increased drain saturation current for MOS transistors in ultrathin silicon-on-insulator (SOI) films is predicted, compared to similar transistors in bulk or thick SOI films. For typical parameters of 200-A gate oxide with a channel doping of 4×10¹⁶ cm^-3, the drain saturation current in ultrathin SOI transistors is predicted to be ~40% larger than that of bulk structures. An increase of ~30% is seen in measurements made on devices in 1000-A SOI films     

Improved subthreshold characteristics of n-channel SOI transistors

It has been found that certain n-channel MOSFET's fabricated on silicon-on-insulator (SOI) substrates formed by oxygen implantation can havelog (I_{d}): V_{gs}, characteristics with very steep slopes in the subthreshold region. In contradiction to normal models for short-channel transistors on bulk silicon, the slope becomes steeper for shorter gate lengths or higher drain voltages. This effect is shown to be related to the kink in the output characteristics of transistors with floating islands.     

A low-frequency noise study of gate-all-around SOI transistors

The low-frequency noise characteristics of both n- and p-type gate-all-around (GAA) SOI MOS transistors are reported and compared with the noise behavior of conventional, partially depleted (PD) SOI transistors. It is shown that the input-referred noise of n-channel GAA transistors is considerably lower than for standard ones, which is related to the higher device transconductance, coupled to the occurrence of volume inversion, P-channel devices have a one order of magnitude lower noise spectral density than n-MOSTs, which is due to the corresponding lower density of interface traps. GAA p-MOSTs tend to have a lower average noise in weak inversion than their standard-SOI counterparts. In strong inversion, the reverse situation is often found. Finally, it is shown that in n-type GAA transistors no kink-related excess noise is observed, which is an additional benefit for using this type of SOI technology     

White noise of MOS transistors operating in weak inversion

A theory is given for the thermal noise of MOS transistors in the weak inversion regime. For MOS transistors with low surface-state density, the relation for the thermal noise in saturation is shown to be the same as a shot noise relation. The theory is compared with measurements and the origin of the white noise in MOST's operating in weak inversion is discussed.     

Two-dimensional dynamic analysis of short-channel thin-film MOS transistors using a minicomputer

A computer program is described for simulating two-dimensional thin-film MOS transistors on a minicomputer. Data are presented showing the variation of internal carrier density with time until a steady-state condition is reached. These data show the formation of a drain-induced back channel whose conduction properties depend on the back-channel length and carrier mobility. For channel length below 2.0 µm, the two-dimensional steady-state drain current is shown to fit the expressionI_{D}/W = frac{micro_{0}C_{0}}{L[1+(micro_{0}/upsilon_{s} V_{D}{L})^{2}]^{1/2}}(V_{G} - V_{T} - V_{D/2})V{D}for values of drain voltage below a specific saturation value (V_{DM}); andI_{D}/W = frac{10^{-8)(V_{G} - V_{T})^{1/2}}{(T_{ox})^{1/2}L}.(V_{D} - V_{DM}) + I_{DM}for drain voltages above the saturation value.     

Theory and experiments of low-frequency generation-recombination noise in MOS transistors

A theoretical model for the generation-recombination (g-r) noise in MOS transistors is presented. This model takes into account the charge induced on all electrodes by the charge fluctuation of the impurity center in the depletion region. The model gives a finite equivalent gate noise resistance at saturation. Gold-doped and no-gold control devices were fabricated to verify the theory experimentally. The drain-voltage dependence of the g-r noise, which is shown to be distinctly different from the 1/f noise and thermal noise, is used to check the theory. Good agreement between theory and experiment is obtained.     

Bipolar transistors with low 1/f noise

Bipolar transistors employing low concentration emitter diffusion were obtained which show no current gain fall-off at low current levels, as well as significantly reduced 1/f noise. These devices may favourably be applied in low noise amplifiers.     

Peculiarities of three-dimensional simulation of SOI MOS transistors with an indirect gate

A methodology for a three-dimensional (3D) simulation of submicron SOI MOS transistors, taking into account a lithographic topology distortion, is presented. The peculiarities of constructing a 3D structure are considered. An efficient method for grid generation is proposed. The results of simulating O-type SOI MOS transistors with and without precorrection of topology are given.