An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation

A distributed DLL (DDLL) with low jitter and high phase accuracy is proposed for the multiphase clock generator. The high-speed multiphase clock generator produces a five-phase clock at a frequency range of 8 to 10 GHz. Additionally, the discrete-time model for the distributed DLL and the analysis about stability and noise are proposed in this work. The measured rms jitter is 293.3 fs and the maximum phase mismatch is 1.4 ps. The proposed architecture can suppress the jitter by 58%. The distributed DLL occupies 0.03 ${hbox{mm}}^{2}$ active area in a 90-nm CMOS technology and consumes 15 mA from a 1.0-V supply.      

A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13- μm CMOS Technology

A 37-38.5-GHz clock generator is presented in this paper. An eight-phase LC voltage-controlled oscillator (VCO) is presented to generate the multiphase outputs. The high-pass characteristic CL ladder topology sustains the high-frequency signals. The split-load divider is presented to extend the input frequency range. The proposed PD improves the static phase error and enhances the gain. To verify the function of each block and modify the operation frequency, two additional testing components-an eight-phase VCO and a split-load frequency divider-are fabricated using 0.13-mum CMOS technology. The measured quadrature-phase outputs of VCO and input sensitivity of the divider are presented. This clock generator has been fabricated with 0.13-mum CMOS technology. The measured rms clock jitter is 0.24 ps at 38 GHz while consuming 51.6 mW without buffers from a 1.2-V supply. The measured phase noise is -97.55 dBc/Hz at 1-MHz offset frequency     

An integrated high resolution CMOS timing generator based on anarray of delay locked loops

This paper describes the architecture and performance of a new high resolution timing generator used as a building block for time-to-digital converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with subgate delay resolution to be implemented in a standard digital CMOS process. The TDC function is implemented by storing the state of the timing generator signals in an asynchronous pipeline buffer when a hit signal is asserted. The clock alignment function is obtained by selecting one of the timing generator signals as an output clock. The proposed timing generator has been mapped into a 1.0 μm CMOS process and an r.m.s. error of the time taps of 48 ps has been measured with a bin size of 0.15 ns. Used as a TDC device, an r.m.s. error of 76 ps has been obtained, A short overview of the basic principles of major TDC and timing generator architectures is given to compare the merits of the proposed scheme to other alternatives     

一种新颖的低非线性全数字多相时钟产生电路

通过对传统的全数字多相位时钟产生电路进行分析和总结,提出一种新颖的延时校准算法。该算法通过优化调整延时单元的顺序,大大改善了全数字多相位时钟产生电路的非线性。整个电路基于全数字延迟锁相环,采用0.13μm CMOS工艺实现,并成功用于时间数字转换器中。输入时钟频率范围在110 MHz到140 MH间,对应的输出相位差为446 ps到568 ps,积分非线性小于0.35 LSB,微分非线性小于0.33 LSB。     

An all-analog multiphase delay-locked loop using a replica delayline for wide-range operation and low-jitter performance

This paper describes an all-analog multiphase delay-locked loop (DLL) architecture that achieves both wide-range operation and low-jitter performance. A replica delay line is attached to a conventional DLL to fully utilize the frequency range of the voltage-controlled delay line. The proposed DLL keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. The DLL incorporates dynamic phase detectors and triply controlled delay cells with cell-level duty-cycle correction capability to generate equally spaced eight-phase clocks. The chip has been fabricated using a 0.35-μm CMOS process. The peak-to peak jitter is less than 30 ps over the operating frequency range of 62.5-250 MHz, At 250 MHz, its jitter supply sensitivity is 0.11 ps/mV. It occupies smaller area (0.2 mm²) and dissipates less power (42 mW) than other wide-range DLL's [2]-[7]     

A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time

A portable clock generator, which solves the duty ratio and jitter problems of the input clock, has been developed. In the proposed clock generator, the complementary delay line generates a series of multiphase clocks. The 0-to-1 transition detector finds the 2 pi phase delayed position among the multiphase clocks produced by the complementary delay line, and then, the select signal generator chooses the proper path to generate the delayed output clock. As a result, the proposed open-loop and full-digital architecture achieves a fast lock time of two clock cycles. Also, it is a simple, robust and portable IP and consumes only 17 mW at an input clock frequency of 1.6 GHz. In addition, a complementary delay line is implemented to achieve high phase resolution over a wide frequency range. The proposed clock generator is implemented in a 0.18-mum CMOS process and, occupies an active area of 170 mum times 120 mum. Also, it operates at various input frequencies ranging from 800 MHz to 1.6 GHz.     

A 0.004-mm2 Portable Multiphase Clock Generator Tile for 1.2-GHz RISC Microprocessor

Portable multiphase clock generators capable of adjusting its clock phase according to input clock frequencies have been developed both in a 0.18-mum and in a 0.13-mum CMOS technologies. They consist of a full-digital CMOS circuit design that leads to a simple, robust, and portable IP. In addition, their open-loop architecture lead to no jitter accumulation and one-cycle lock characteristic that enables clock-on-demand circuit structures. The implemented low power clock generator tile in a 0.13-mum CMOS technology occupies only 0.004 mm ² and operates at variable input frequencies ranging from 625 MHz to 1.2 GHz within a plusmn 2% phase error having one-cycle lock time.     

A 20-MHz to 3-GHz Wide-Range Multiphase Delay-Locked Loop

A 20-MHz to 3-GHz wide-range multiphase delay-locked loop (DLL) has been realized in 90-nm CMOS technology. The proposed delay cell extends the operation frequency range. A scaling circuit is adopted to lower the large delay gain when the frequency of the input clock is low. The core area of this DLL is 0.005 $hbox{mm}^{2}$. The measured power consumption values are 0.4 and 3.6 mW for input clocks of 20 MHz and 3 GHz, respectively. The measured peak-to-peak and root-mean-square jitters are 2.3 and 16 ps at 3 GHz, respectively.      

A Low-Jitter Spread Spectrum Clock Generator Using FDMP

A 1.5 GHz spread spectrum clock generator (SSCG) is realized by a fractional N frequency synthesizer with a third-order delta-sigma modulator and a fractional dual-modulus prescaler (FDMP). This FDMP utilizes a fractional division ratio to have a small phase step to improve the jitter performance. This SSCG has been fabricated in a 0.18 um CMOS process, and it consumes 34.2 mW from a supply of 1.8 V. The measured rms jitter is 5.55 ps and the measured electromagnetic interference reduction amount is 14.77 dB. The measured phase noise is $-97.18$ dBc/Hz at 1 MHz offset.      

An All-Digital Fast-Locking Programmable DLL-Based Clock Generator

An all-digital fast-locking programmable DLL-based clock generator is presented. By resetting the output clock every two input clock periods, the initial minimal delay constraint in the conventional architecture is eliminated. Compared with the previous work, the short locking time is also achieved. The proposed circuit has been fabricated in 0.35-$mu$ m CMOS process and occupies the active area of 0.216 ${hbox {mm}}^{2}$. The clock multiplication ratio is programmed from 2 to 15. The frequency ranges of the input and output clocks are 4 $sim$ 200 MHz and 60 $sim$ 450 MHz, respectively. It dissipates less than 17 mW at all operating frequencies from a 3.3-V supply.      

A 250-622 MHz deskew and jitter-suppressed clock buffer usingtwo-loop architecture

A 250-622 MHz clock buffer has been developed, using a two-loop architecture: a delay-locked loop (DLL) for deskew, and a frequency-locked loop (FLL) for reference frequency supply to the DLL. The DLL incorporates a current-mode phase detector which utilizes a flip-flop metastability to detect a phase difference in the order of 20 ps. A measured jitter is suppressed to less than 40 ps RMS over the operating frequency range. A DLL acquisition time of 150 ns typical is simulated at 400 MHz. A 0.4-μm CMOS technology is used to fabricate the chip     

A time digitizer CMOS gate-array with a 250 ps time resolution

A pipelined time digitizer CMOS gate-array has been developed using 0.5 μm Sea-of-Gate technology. Precise timing signals which are used to sample input signals are generated from 32 taps of an asymmetric ring oscillator. The frequency of the oscillator is controlled by a phase-locked loop (PLL) circuit which runs in the 10-50 MHz frequency range. A test chip has been developed and tested; a time resolution of 250 ps rms at 40 MHz clock was measured. The chip has 4 channels and encoding circuits for both the rising and the falling edges of the input signals. The chip has 128-word dual-port memories, allowing the histories of the input signals to be stored and causing no deadtime for the conversion     

A Low-Power Programmable DLL-Based Clock Generator With Wide-Range Antiharmonic Lock

A delay-locked-loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13-${rm mu}hbox{m}$ CMOS technology. The proposed clock generator can generate a wide range of the multiplied clock signals ranging from 125 MHz to 2 GHz. In addition, owing to the proposed antiharmonic-lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock. The proposed DLL-based clock generator occupies 0.019 $hbox{mm}^{2}$ and consumes 21 mW at 2 GHz. The ratio of power consumption to frequency of the proposed clock generator is smaller than those of conventional ones.      

A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clockgeneration

This paper describes a low-power microprocessor clock generator based upon a phase-locked loop (PLL). This PLL is fully integrated onto a 2.2-million transistors microprocessor in a 0.35-μm triple-metal CMOS process without the need for external components. It operates from a supply voltage down to 1 V at a VCO frequency of 320 MHz. The PLL power consumption is lower than 1.2 mW at 1.35 V for the same frequency. The maximum measured cycle-to-cycle jitter is ±150 ps with a square wave superposed to the supply voltage with a peak-to-peak amplitude of 200 mV and rise/fall time of about 30 ps. The input frequency is 3.68 MHz and the PLL internal frequency ranges from 176 MHz up to 574 MHz, which correspond to a multiplication factor of about 100     

A semidigital dual delay-locked loop

This paper describes a dual delay-locked loop architecture which achieves low jitter, unlimited (modulo 2π) phase shift, and large operating range. The architecture employs a core loop to generate coarsely spaced clocks, which are then used by a peripheral loop to generate the main system clock through phase interpolation. The design of an experimental prototype in a 0.8-μm CMOS technology is described. The prototype achieves an operating range of 80 kHz-400 MHz. At 250 MHz, its peak-to-peak jitter with quiescent supply is 68 ps, and its jitter supply sensitivity is 0.4 ps/mV     

An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line

A wide-range delay-locked loop (DLL) with infinite phase shift and digital-controlled duty cycle is presented. By changing the polarity of the input clock of the voltage-controlled sawtooth delay, this proposed DLL achieves infinite phase shift by only a single loop. The proposed DLL has been fabricated in a 0.18$ mu$m CMOS process and the core area is $hbox{0.45}times {hbox{0.3 mm}}^{2}$. The measurement results show the proposed DLL operates from 50 to 500 MHz. The duty cycle of the output clock can be adjusted from 30% to 60% in the step of 5%. At 500 MHz, the measured rms jitter and peak-to-peak jitter is 1.43 and 11.1 ps, respectively. Its power consumption is 6 mW for a supply of 1.5 V.      

A low jitter, low spur multiphase phase-locked loop for an IR-UWB receiver

A low jitter,low spur multiphase phase-locked loop(PLL) for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator(VCO) is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the l...     

The design of an All-Digital Phase-Locked Loop with low jitter based on ISF analysis

A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.     

A $Delta{-}Sigma$ PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology

A triangular-modulated spread-spectrum clock generator using a$Delta{-}Sigma$-modulated fractional-$N$ phase-locked loop (PLL) is presented. The PLL employs a multiphase divider to implement the modulated fractional counter with increased $Delta{-}Sigma$ operation speed. In addition, the phase mismatching error in the phase-interpolated PLL with multiphase clocks can be randomized, and finer frequency resolution is achievable. With a frequency modulation of 33 kHz, the measured peak power reduction is more than 11.4 dB under a deviation of $pm$0.37%. Without spread-spectrum clocking, the PLL generates 2.4-GHz output with 18.82-ps peak-to-peak jitter. After spread-spectrum operation, the measured up-spread and down-spread jitter can achieve 52.59 and 56.79 ps, respectively. The chip occupies $950times850 {rm mu}{rm m}^{2}$ in 0.18-${rm mu}{rm m}$ CMOS process and consumes 36 mW.      

A wide-range all digital DLL for multiphase clock generation

This paper presents a wide-range all digital delay-locked loop (DLL) for multiphase clock generation. Using the phase compensation circuit (PCC), the large phase difference is compensated in the initial step. Thus, the proposed solution can overcome the false-lock problem in conventional designs, and keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. Furthermore, the proposed all digital multiphase clock generator has wide ranges and is not related to specific process. Thus, it can reduce the design time and design complexity in many different applications. The DLL is implemented in a 0.13 μm CMOS process. The experimental results show that the proposal has a wide frequency range. The peak-to-peak jitter is less than 7.7 ps over the operating frequency range of 200 MHz-1 GHz and the power consumption is 4.8 mW at 1 GHz. The maximum lock time is 20 clock cycles.