Efficient thermal modeling of SOI MOSFETs for fast dynamic operation

An efficient dynamic thermal model has been developed for silicon-on-insulator (SOI) MOSFETs. The model is derived from the variational principle using a thermal functional, and is able to describe extremely fast dynamic thermal behavior in SOI devices subjected to sudden changes in power generation. The developed model is further converted into a thermal circuit with time-varying thermal resistances and capacitances. With the circuit implemented in a circuit simulator, these time-varying thermal resistances and capacitances are able to reasonably capture extremely fast temperature evolution in SOI devices without including a large number of nodes. The developed dynamic thermal model and circuit are verified with the rigorous device simulation including self-heating.     

High-frequency performance of subthreshold SOI MESFETs

Results from silicon-on-insulator (SOI) MESFETs designed for subthreshold operation are presented. The transistors have subthreshold slopes as low as 78 mV/dec and off-state drain currents approaching 1 pA//spl mu/m. Drain current saturation can be achieved with drain voltages of less than 0.5 V and with output impedance>100 M/spl Omega//spl middot//spl mu/m. The cutoff frequency of a 500-nm gate length device exceeds 1 GHz at currents significantly less than 1 /spl mu/A//spl mu/m. These results suggest that subthreshold SOI MESFETs might have useful applications in mixed-signal, micropower circuit design.     

First-order theory of MOSFET hybrid-mode operation

For specified bias conditions, measurements and theory justify the first-order representation of an enhancement-mode MOS transistor operating with forward source-substrate bias (‘hybrid-mode’ operation) as a parallel combination of two non-interacting devices—an MOS transistor with zero source-substrate bias, and a bipolar junction transistor.     

Measurement of substrate current in SOI MOSFETs

A new “Quasi-SOI” MOSFET structure is shown to allow direct measurement of substrate current in a fully-depleted SOI device. The holes generated by impact ionization near the drain are collected at the substrate terminal after they have traversed the source-body barrier and caused bipolar multiplication. By monitoring this hole current, direct characterization of the impact-ionization multiplication factor, M, and the parasitic bipolar gain, β, was performed. It was found that M-1 increases exponentially with V_DS and decreases with V_GS, exhibiting a drain field dependence. The bipolar gain β was found to be as high as 1000 for V_GS-V_T=0 V and V_DS=-2.5 V, but decreases exponentially as V_DS increases. Finally, it was found that β also decreases as V_GS increases     

Monte Carlo Simulation of Nanoscale SOI MOSFETs

A comparative review is presented of the current research on the quantum-mechanical and classical Monte Carlo simulation of SOI MOSFETs. A quantum-mechanical simulation method is proposed whereby the energy of transverse channel quantization is represented by a correction term. A newly developed simulation program, called BALSOI, is outlined. A comparison is made between the results of a 2D classical Monte Carlo simulation and those obtained by the quantum-mechanical method. It is observed that the differences are much smaller than what one might expect. This finding is explained as due to the considerable effect of the space charge, which is mainly governed by the classical, longitudinal motion of carriers through the channel. An analytical formula is derived for the effect of channel quantization on the gate–channel capacitance. The strength of tunneling current through a short-channel transistor in the off state is considered.     

新型多栅全耗尽SOI器件研究进展

随着器件尺寸的不断缩小,对更大驱动电流和更有效抑制短沟道效应器件的研制成为研究的热点,SOI多栅全耗尽器件由于对沟道更好控制能力能够有效地解决尺寸缩小带来的短沟道效应问题[1].本文主要介绍SOI/MOSFET单栅、平面双栅、FinFET、三栅、环绕栅、G4-FET等新型多栅全耗尽SOI器件的研究进展.     

Comparative analysis of SOI and GOI MOSFETs

In this paper, the authors use a full-band particle-based simulator based on the cellular Monte Carlo method to investigate and compare the performance of silicon-on-insulator (SOI) and germanium-on-insulator (GOI) technologies. To this end, p-type GOI and SOI MOSFETs of effective gate lengths ranging from 30 to 110 nm are simulated, and their static and dynamic characteristics are analyzed through simulations. The transconductance, channel conductance, current-voltage (I-V) characteristics, and cutoff frequencies are extracted from the simulation results. The results indicate that drive currents are enhanced up to 25% by replacing Si with Ge. The enhancement is not as significant with respect to the unity gain frequency, which is only increased by 13% in the case of a 50-nm MOSFET. Additionally, the I-V characteristics indicate that GOI MOSFETs are more sensitive to impact ionization than their SOI counterparts, and that the channel conductance is degraded.     

Low-temperature electron mobility in Trigate SOI MOSFETs

Evidence of one-dimensional subband formation is found at low temperature in trigate silicon-on-insulator MOSFETs, resulting in oscillations of the I/sub D/(V/sub G/) characteristics. These oscillations correspond to the filling of energy subbands by electrons as the gate voltage is increased. High mobility, reaching 1200 cm/sup 2//Vs, is measured in the subbands at T=4.4 K. Subband mobility decreases as temperature is increased. Conduction in subbands disappears for temperatures higher than 100 K or for drain voltage values that are significantly larger than kT/q.     

Threshold Voltage Variation in SOI Schottky-Barrier MOSFETs

The inhomogeneity of Schottky-barrier (SB) height Phi_B is found to strongly affect the threshold voltage V_th of SB-MOSFETs fabricated in ultrathin body silicon-on-insulator (SOI). The magnitude of this influence is dependent on gate oxide thickness t_OX and SOI body thickness; the contribution of inhomogeneity to the V_th variation becomes less pronounced with smaller t_OX and/or larger t_si . Moreover, an enhanced V_th variation is observed for devices with dopant segregation used for reduction of the effective Phi_B . Furthermore, a multigate structure is found to help suppress the V_th variation by improving carrier injection through reduction of its sensitivity to the Phi_B inhomogeneity. A new method for extraction of Phi_B from room temperature transfer characteristics is also presented.     

SOI MOSFET自加热效应测试方法

为研究自加热效应对绝缘体上硅(SOI)MOSFET漏电流的影响,开发了一种可同时探测20 ns时瞬态漏源电流-漏源电压(Ids-Vds)特性和80μs时直流静态Ids-Vds特性的超快脉冲I-V测试方法。将被测器件栅漏短接、源体短接后串联接入超快脉冲测试系统,根据示波器在源端采集的电压脉冲的幅值计算漏电流受自加热影响的动态变化过程。选取体硅NMOSFET和SOI NMOSFET进行验证测试,并对被测器件的温度分布进行仿真,证实该方法用于自加热效应的测试是准确有效的,能为建立准确的器件模型提供数据支撑。采用该方法对2μm SOI工艺不同宽长比的NMOSFET进行测试,结果表明栅宽相同的器件,栅长越短,自加热现象越明显。     

Analytical modelling of ultra-thin film depletion-mode SOI MOSFETs

Reliable analytical models for thin and ultra-thin film depletion-mode SOI MOSFETs have been developed. These models are based on the linearly varying potential (LVP) approximation in the Si film. They allow the understanding and optimization of electrical properties of these devices. In particular, the behaviour of the subthreshold swing and the transconductance is discussed and compared successfully with numerical simulation.     

Analysis of conduction in fully depleted SOI MOSFETs

The conduction characteristics of fully depleted SOI MOSFETs studied by theoretical analysis and computer simulation are discussed. In these devices the ideal inverse subthreshold slope of 59.6 mV/decade is obtained if the interface-state capacitances are much smaller than the gate-oxide and silicon-film capacitances. For above-threshold conduction, with decreasing silicon film thickness the inversion charges penetrate more deeply into the film and the transconductance increases because of the decreasing fraction of surface conduction     

Reduction of kink effect in thin-film SOI MOSFETs

Numerical simulation is used to show that potential and electric field distribution within thin, fully depleted SOI devices is quite different from that observed within thicker, partially depleted devices. Reduction of drain electric field and of source potential barrier brings about a dramatic decrease of kink effect     

On the scaling limit of ultrathin SOI MOSFETs

In this paper, a detailed study on the scaling limit of ultrathin silicon-on-insulator (SOI) MOSFETs is presented. Due to the penetration of lateral source/drain fields into standard thick buried oxide, the scale-length theory does not apply to thin SOI MOSFETs. An extensive two-dimensional device simulation shows that for a thin gate insulator, the minimum channel length can be expressed as L/sub min//spl ap/4.5(t/sub Si/+(/spl epsiv//sub Si///spl epsiv//sub I/)t/sub I/), where t/sub Si/ is the silicon thickness, and /spl epsiv//sub I/ and t/sub I/ are the permittivity and thickness of the gate insulator. With t/sub Si/ limited to /spl ges/ 2 nm from quantum mechanical and threshold considerations, a scaling limit of L/sub min/=20 nm is projected for oxides, and L/sub min/=10 nm for high-/spl kappa/ dielectrics. The effect of body doping has also been investigated. It has no significant effect on the scaling limit.     

Observation of mobility enhancement in ultrathin SOI MOSFETs

The mobility in n-channel SOI MOSFETs exhibits a significant increase as the SOI film becomes thinner than 1000 Å. At a 500 Å SOI thickness, the mobility values are distributed in the 700-1100 cm²/Vs range, which are obviously higher than the value in a bulk MOSFET having an identical doping concentration. The observed mobility enhancement has been explained by a decrease in the vertical electric field, associated with the complete depletion of the SOI film     

Modeling of Surface-Roughness Scattering in Ultrathin-Body SOI MOSFETs

A rigorous surface-roughness scattering model for ultrathin-body silicon-on-insulator (SOI) MOSFETs is derived, which reduces to Ando's model in the limit of bulk MOSFETs. The matrix element of the scattering potential reflects the fluctuations of both the wavefunction and the potential energy. The matrix element reflecting the fluctuation of the wavefunction is expressed in an integral form which can be considered as a generalized Prange-Nee term-to which it is equivalent in the limit of an infinitely high insulator-semiconductor barrier-giving more accurate results in the case of a finite barrier height. The matrix element reflecting the fluctuation of the potential energy is due to the Coulomb interactions originating from the roughness-induced fluctuation of the electron charge density, the interface polarization charge, and the image-charge density. The roughness-limited low-field electron mobility in thin-body SOI MOSFETs is obtained using the matrix elements that we have derived. We study its dependence on the silicon body thickness, effective field, and dielectric constant of the insulator.     

Two-dimensional analytic modeling of very thin SOI MOSFETs

An analytic solution of the Poisson's equation for MOSFETs on very thin SOI (silicon on insulator) was developed using an infinite series method. The calculation region includes the thin SOI and the gate and buried oxides. The results of this model were found to agree well with a two-dimensional (PISCES) simulation in the subthreshold region and the linear region with small V_DS. This model is used to study the short-channel behavior of very small MOS transistors on thin SOI. It is found that with very thin SOI, short-channel effects are much reduced compared to bulk MOS transistors and depend on the bulk-substrate bias. The model also shows that it is possible to fabricate submicrometer transistors on very thin SOI even if the channel doping is nearly intrinsic     

Integrated physics-oriented statistical modeling, simulation, andoptimization [MESFETs]

Physics-based modeling of MESFETs is addressed from the point of view of efficient simulation, accurate behavior prediction and robust parameter extraction. A novel integration of a large-signal physics-based model into the harmonic balance equations for simulation of nonlinear circuits, involving an efficient Newton update, is presented and exploited in a gradient-based FAST (feasible adjoint sensitivity technique) circuit optimization technique. For yield-driven MMIC design a relevant physics-based statistical modeling methodology is presented. Quadratic approximation of responses and gradients suitable for yield optimization is discussed. The authors verify their theoretical contributions and exemplify their computational results using built-in and user-programmable modeling capabilities of the CAE systems OSA90/hope and HarPE. Results of device modeling using a field-theoretic nonlinear device simulator are reported     

Investigation of temperature-dependent small-signal performances of TB SOI MOSFETs

This paper investigated the temperature dependence of the cryogenic small-signal ac performances of multi-finger partially depleted (PD) silicon-on-insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs), with T-gate body contact (TB) structure. The measurement results show that the cut-off frequency increases from 78 GHz at 300 K to 120 GHz at 77 K and the maximum oscillation frequency increases from 54 GHz at 300 K to 80 GHz at 77 K, and these are mainly due to the effect of negative temperature dependence of threshold voltage and transconductance. By using a simple equivalent circuit model, the temperature-dependent small-signal parameters are discussed in detail. The understanding of cryogenic small-signal performance is beneficial to develop the PD SOI MOSFETs integrated circuits for ultra-low temperature applications.     

Transient behavior of subthreshold characteristics of fullydepleted SOI MOSFETs

It has been found that the subthreshold currents of fully depleted silicon-on-insulator (SOI) MOSFETs show a transient behavior under certain front-gate and back-gate voltage conditions. The cause of this anomaly is explained, and applications for the phenomenon are pointed out. Particularly, a simple way to measure the silicon film thickness is suggested