Lateral insulated-gate bipolar transistor (LIGBT) with a segmentedanode structure

A novel lateral insulated-gate bipolar transistor (LIGBT) structure, called the segmented anode LIGBT, is presented. In this structure, the anode, which is responsible for the injection of minority carriers for conductivity modulation, is implemented using segments of p ⁺ and n⁺ diffusions along the device width. This segmented design of the anode structure results in higher switching speed and reduction in device size. Depending on the value of the specific ON resistance, experimental results show that the segmented anode LIGBT has from 20% to 250% reduction in turn-off time as compared to the shorted anode LIGBT     

n+/p+ Gate Bulk FinFETs With Locally Separated Channel Structure for Sub-50-nm DRAM Cell Transistors

We proposed a new p⁺/n⁺ poly-Si gate bulk fin-type field-effect transistor that has two channel fins separated locally by a shallow trench filled with oxide or p⁺ polygate. Key device characteristics were investigated by changing the n⁺ poly-Si gate length La, the material filling the trench, and the width and length of the trench at a given gate length L_g. It was shown that the trench filled with p⁺ poly-Si gate should not be contacted with the source/drain diffusion region to achieve an excellent I_on/I_off (> 1010) that is suitable for sub-50-nm dynamic random access memory cell transistors. Based on the aforementioned device structure, we designed reasonable Ls/Lg and channel fin width W_cfin at given L_g 's of 30, 40, and 50 nm.     

The modified structure of the lateral IGBT on the SOI wafer forimproving the dynamic latch-up characteristics

The modified structure of the lateral IGBT(LIGBT) on an SOI wafer for improving the dynamic latch-up characteristics is presented together with its numerical simulations and experimental results. The modified LIGBT structure has a p⁺-emitter layer between the collector and gate regions. The current at which the latch-up occurs during the turn-off transient under an inductive load is estimated in comparison with that of the conventional LIGBT. The dynamic latch-up current at room temperature and 125°C for the modified LIGBT were 350 A/cm² and 290 A/cm², respectively. These results indicate the improvement of about 3.5 times at room temperature and about 5.5 times at 125°C compared with those for the conventional LIGBT. This remarkable improvement in the dynamic latch-up performance is accomplished at the expense of an increase of 0.8 V in the forward voltage drop     

Properties of the transient of avalanche transistor switching atextreme current densities

Avalanche transistor switching at extreme currents is studied under conditions in which the charge of the excess carriers drastically rebuilds the collector field domain, causing fast switching and a low residual voltage across the switched-on device. The dynamic numerical model includes carrier diffusion and considers different dependencies of the velocities and ionization rates for the electrons and holes in the electric field. These dependences determine the principal difference in the switching process between n⁺-p-n₀-n⁺ and p⁺-n-p₀ -p⁺ structures. Reasonably good agreement is found between the simulated and measured temporal dependences of the collector current and voltage drop across the device for a particular type of avalanche transistor. Certain differences in the switching delay can partly be attributed to limitations in the one-dimensional (1-D) approach. It is now certain that collector domain reconstruction defines the transient in a n⁺-p-n₀-n⁺ transistor at high currents, but is not very pronounced in a p⁺ -n-p₀-p⁺ transistor. Some nontrivial features of the device operation are found, depending on the semiconductor structure. In particular, it is shown that the thickness of the low-doped collector region affects mainly the switching delay, and does not significantly effect the current rise time     

Gate Workfunction Engineering in Bulk FinFETs for Sub-50-nm DRAM Cell Transistors

We proposed a new bulk FinFET that has a p⁺/n⁺ poly-Si gate consists of p⁺ region near the source and n⁺ region near the drain and analyzed current-voltage characteristics and electric field profiles of 50-nm devices by changing the n⁺ poly-Si gate length (L_s). For given gate length (L_gles50 nm) and fin body width (W_finles30 nm), L_s was designed to satisfy the I _off requirement (i.e., 1 fA) of DRAM cell. Optimum L_s /L_g of 30-nm device was ~0.4 at a W_fin of 10 nm and ~0.2 at a W_fin of 15 nm     

An isolated MISS regenerative switching device

A new MISS switching device structure was designed and fabricated, which consists of Al/thin thermal oxide/p-n⁺-p-Si layers and is isolated by diffusing n-well to the buried n⁺layer. Furthermore, an N⁺-shield layer which confines the carrier flow to the MIS interface and a p⁺-gate which injects carriers in the n⁺-p junction were successfully implemented. The device reveals that switching and holding voltages Vsand VHboth decrease with increasingA_{0x}, and with decreasingA_{J} and d_{0x}. The fringing effect is minimized due to the isolated structure.     

Distribution of trapped charges in SiO2 film of ap+-gate PMOS structure

To investigate the highly boron-doped SiO₂ film, p⁺ polysilicon-gate PMOSFETs and capacitors were fabricated using the same process as is used for surface-channel-type n⁺-gate devices, except for the gate-type doping. After the application of negatively biased Fowler-Nordheim (FN) stress, it was found that positive charges accumulate near the silicon/SiO₂ interface and electrons accumulate near the polysilicon/SiO₂ interface in p⁺-gate capacitors. DC hot carrier stress was applied to both PMOSFET gate types. The p⁺ gate's stress time dependence of I_sub is smaller than that of the n⁺ gate, and the electric field near the drain in the p⁺ -gate PMOSFET was found to be more severe than that of the n⁺ -gate device. The subthreshold slope of the p⁺-gated PMOSFET was improved and then degraded during the hot carrier stressing, while that of the n⁺-gated device did not significantly change. The actual change of V_th was larger than the value derived from Δ_gm using the channel-shortening concept. The idea of widely spreading and partially compensated electron distribution along with source-drain direction in the SiO₂ film, which assumes the existence of trapped holes in the p⁺-gate PMOSFET, is proposed to explain these phenomena     

Analytical models for n+-p+ double-gate SOIMOSFET's

Previously, we proposed n⁺-p⁺ double-gate SOI MOSFET's, which have n⁺ polysilicon for the back gate and p⁺ polysilicon for the front gate to enable adjustment of the threshold voltage, and demonstrated high speed operation. In this paper, we establish analytical models for this device, This transistor has two threshold voltages related to n⁺ and p⁺ polysilicon gates: V_th1 and V_th2, respectively. V _th1 is a function of the gate oxide thickness t_Ox and SOI thickness t_Si and is about 0.25 V when t_Ox/t_Si=5, while V_th2 is insensitive to t_Ox and t_Si and is about 1 V. We also derive models for conduction charge and drain current and verified their validity by numerical analysis. Furthermore, we establish a scaling theory unique to the device, and show how to design the device parameters with decreasing gate length. We show numerically that we can design sub 0.1 μm gate length devices with an an appropriate threshold voltage and an ideal subthreshold swing     

The effect of substrate doping on the performance of anode-shortedn-channel lateral insulated-gate bipolar transistors

The performance of n-channel lateral-insulated-gate bipolar transistors (n-LIGBTs) with anode shorts on p^- epi/p⁺ substrates is compared to that of anode-shorted n-LIGBTs on p^- substrates, as well as to that of conventional n-LIGBTs on either substrate. It is shown that both forward-voltage drop and turn-off time are better for anode-shorted devices fabricated on p^- epi/p⁺ substrate than for those on p^- substrates, due to a larger percentage component of vertical bipolar current and a lower collector resistance. Forward-voltage drops of 3.05 and 3.3 V at 133 A/cm² and turn-off times of 400 and 750 ns have been measured for devices on p^- epi/p⁺ and p ^- substrates respectively. All the LIGBTs showed current limiting at two to four times the ON-state conduction current during dynamic switching     

A new and improved borderless contact (BLC) structure forhigh-performance Ti-salicide in sub-quarter micron CMOS devices

We demonstrate a new and improved borderless contact (BLC) Ti-salicide process for the fabrication of sub-quarter micron CMOS devices. A low-temperature chemical vapor deposition (CVD) SiO_x N_y film to act as the selective etching stop layer and the additional n⁺ and p⁺ source-drain double implant structure (DIS) are employed in the studied device. The additional n⁺ and p⁺ DIS can reduce the junction leakage current, which is usually enhanced by BLC etching near the edge of shallow trench isolation (STI). The process window is enlarged. Furthermore, the employed low-thermal oxynitride and high deposition rate can improve the salicide thermal stability and avoid the salicide agglomeration     

Improving the response of optical phase modulators in SOI bycomputer simulation

This paper reports on the simulation of a low-loss single-mode optical phase modulator fabricated in silicon-on-insulator (SOI) material. The device operates by injecting free carriers to change the refractive index in the guiding region, and has been modeled using the two-dimensional (2-D) device simulation package SILVACO. SILVACO has been employed to optimize the overlap between the injected free carriers in the intrinsic region and the propagating optical mode. Attention has been paid to both the steady state and transient properties of the device. In order to produce quantitative results, a particular p-i-n device geometry has been employed in the optimization, but the trends in the results are general enough to be of help in the design of many modulator geometries. The specific example device we have used is designed to support a single optical guided mode and is of multimicrometer dimensions thus simplifying fabrication and allowing efficient coupling to-from single-mode fibers (SMF's) or other single-mode devices. The modeling indicates that increased dc device performance results from an increase in the doping concentrations and the contact diffusions of the p⁺ and n⁺ regions. The transient performance of the device in terms of switching times depends on the separation of the p⁺ and n⁺ regions. The optimizations are applicable to large (multimicrometer size) modulators. Phase modulators with low driving currents (<8 mA) and modulators with transient rise times of 39 ns and fall times of 6 ns are predicted     

Double-injection diode as a pulse width modulation element

Double-injection switching devices consist of a p⁺and an n⁺junction for injecting holes and electrons into the high resistivity semiconductor substrate containing compensated (charged) deep traps. These devices show an S-type switching beyond a certain threshold voltage. One possible use of such DI devices is for pulse width modulation. When the device is pulsed with a voltage Vpexceeding VThthe current output of the device appears with increasing pulse width as Vpis increased, for a given input pulse width. An inverse relationship between Vpand the delay with which the pulse appears, has been found experimentally and is being modeled.     

A self-aligned retrograde twin-well structure with buried p+-layer

The retrograde twin wells and buried p⁺ layer are fabricated by a single lithographic step using high-energy ion implantation. The retrograde n-well is self-aligned to the retrograde p-well regions. This simple process allows a scalable CMOS structure for the very tight n⁺-to-p⁺ spacing. It provides latch-up immunity at the 1.5-μm n⁺-to-p⁺ spacing and good isolation characteristics without additional n- and p-channel stops     

A new p-channel MOSFET with large-tilt-angle implanted punchthroughstopper (LATIPS)

A buried-channel p-MOSFET with a large-tile-angle implanted punchthrough stopper (LATIPS) is described. In this device the n⁺ LATIPS region was successfully realized adjacent to the p⁺ source/drain, even without a sidewall spacer, by taking advantage of the n⁺ large-tilt-angle implant. In spite of the relatively deep p⁺ junction of 0.2-μm depth and the low n-well concentration of 1×10¹⁶ cm^-3, the 0.5-μm LATIPS device (with corresponding channel length of 0.3 μm) achieved high punchthrough resistance, e.g. a low subthreshold swing of 95 mV/decade with a high transconductance of 135 mS/mm     

A self-aligned retrograde twin-well structure with buried p+-layer

A self-aligned retrograde twin-well structure with a buried p⁺-layer surrounding the n-well is presented. The retrograde twin well and buried p⁺-layer are fabricated by a single lithographic step using high-energy ion implantation. The retrograde n-well is self-aligned to the retrograde p-well regions, and the channel stop processes are eliminated by using tight spatial distributions of retrograde n- and p-wells. This simple process is compatible with both local oxidation of silicon (LOCOS) and trench isolation processes and allows a scalable CMOS structure for very tight n⁺-to-p⁺ spacing. The present CMOS structure provides high latchup immunity at 1.5-μm n⁺-to-p⁺ spacing and good isolation characteristics without additional n- and p-channel stop dopings     

A self-aligned 1-µm-channel CMOS technology with retrograde n-well and thin epitaxy

A six-mask 1-µm CMOS process with many self-aligned features is described. It uses a thin p-type epitaxial layer on a p⁺substrate and a retrograde n-well. Self-aligned TiSi2is formed on n⁺and p⁺diffusions to reduce the sheet resistance and to make butted source contacts. It is shown that n⁺poly-gated p-channel devices can be properly designed with low threshold magnitudes and good turn-off characteristics. With a 5-V supply, the minimum gate delay of unloaded CMOS ring oscillators is 150 ps/stage. Furthermore, it is demonstrated that this CMOS technology is latchup free since the holding voltage for latchup is higher than 5 V.     

A measurement method of the injection dependence of theconductivity mobility in silicon

A new electrical method to measure the conductivity mobility as a function of the injection level is proposed in this paper. The measurement principle is based on the detection of the voltage drop appearing across a n⁺-n-n⁺ (p⁺-p-p⁺) structure when a current step is forced into it at a given injection level in the intermediate region. This is obtained by using a three-terminal test pattern consisting of p⁺ , n⁺ layers realized on top of a n-n⁺ (p-p ⁺) epitaxial wafer, where the p⁺-n-n⁺ (n⁺-p-p⁺) surface diode is forward biased to monitor the conductivity of the epilayer. The use of separate terminals for injection control and mobility measurement allows this technique to overcome some limitations presented by other electrical methods available in literature, Mobility values measured up to 2·10¹⁷ cm^-3 are in good agreement with those predicted by the Dorkel and Leturcq's model (1981)     

Comparison of high speed DI-LIGBT structures

The performance of the DI segmented collector (SC)-LIGBT is compared to the collector shorted (CS)-LIGBT. The SC-LIGBT allows for adjusting the tradeoff between switching speed and on-state voltage drop by simply changing the P⁺ collector segment width during device layout. In contrast to previously reported junction isolated (JI) devices, the DI SC-LIGBT was observed to have a turnoff speed similar to the CS-LIGBT with a higher forward drop than the conventional LIGBT. The on-state performance of the integral diodes of the SC-LIGBTs was found to be superior to the integral diode of the CS-LIGBT. The integral diodes of both the CS and the SC-LIGBTs were found to have much superior switching characteristics compared to a lateral PiN diode at the expense of a higher on-state voltage drop. Thus, the superior switching characteristics of the integral diode in the SC-LIGBT complements its fast switching behavior making this device attractive for compact, high frequency, high efficient, power ICs.     

Process limitation and device design tradeoffs of self-aligned TiSi2 junction formation in submicrometer CMOS devices

Submicrometer CMOS transistors require shallow junctions to minimize punchthrough and short-channel effects. Salicide technology is a very attractive metallization scheme to solve many CMOS scaling problems. However, to achieve a shallow junction with a salicide structure requires careful optimization for device design tradeoffs. Several proposed techniques to form shallow titanium silicide junctions are critically examined. Boron, BF₂, arsenic, and phosphorus dopants were used to study the process parameters for low-leakage TiSi ₂ p⁺/n and n⁺/p junctions in submicrometer CMOS applications. It is concluded that the dopant drive-out (DDO) from the TiSi₂ layer to form a shallow junction scheme is not an efficient method for titanium salicide structure; poor device performance and unacceptably leaky junctions are obtained by this scheme. The conventional post junction salicide (PJS) scheme can produce shallow n⁺/p and p⁺/n junctions with junction depths of 0.12 to 0.20 μm below the TiSi₂. Deep submicrometer CMOS devices with channel length of 0.40 to 0.45 μm can be fabricated with such junctions     

Formation of 0.05-μm p+-n and n+-pjunctions by very low (<500 eV) ion implantation

The current-voltage (I-V) characteristics of ultrashallow p⁺ -n and n⁺-p diodes, obtained using very-low-energy (<500-eV) implantation of B and As, are presented. the p⁺-n junctions were formed by implanting B⁺ ions into n-type Si (100) at 200 eV and at a dose of 6×10¹⁴ cm^-2, and n⁺-p junctions were obtained by implanting As⁺ ions into p-type (100) Si at 500 eV and at a dose 4×10¹² cm^-2. A rapid thermal annealing (RTA) of 800°C/10 s was performed before I-V measurements. Using secondary ion mass spectrometry (SIMS) on samples in-situ capped with a 20-nm ²⁸Si isotopic layer grown by a low-energy (40 eV) ion-beam deposition (IBD) technique, the depth profiles of these junctions were estimated to be 40 and 20 nm for p⁺-n and n⁺-p junctions, respectively. These are the shallowest junctions reported in the literature. The results show that these diodes exhibit excellent I-V characteristics, with ideality factor of 1.1 and a reverse bias leakage current at -6 V of 8×10^-12 and 2×10^-11 A for p⁺-n and n⁺-p diodes, respectively, using a junction area of 1.96×10^-3 cm²