GaAs MESFET's fabricated on monolithic GaAs/Si substrates

GaAs MESFET's have been fabricated for the first time on monolithic GaAs/Si substrates. The substrates were prepared by growing single-crystal GaAs layers on Si wafers that had been coated with a Ge layer deposited by e-beam evaporation. The MESFET's exhibit good transistor characteristics, with maximum transconductance of 105 mS/mm for a gate length of 2.1 µm.     

Scaled GaAs MESFET's with gate length down to 100 nm

Fully ion-implanted GaAs depletion MESFET's with gate lengths from 1 µm down to 0.1 µm and with closely spaced source and drain contacts have been fabricated with electron-beam lithography. Gate-length dependence of transconductance, capacitance, output conductance, and threshold voltage is presented. Maximum transconductance obtained was 370 mS/mm for 0.1-µm gate length. The experimental data indicate that shallow implants do indeed result in better devices, but further vertical scaling of the devices is mandatory.     

Microwave MESFET's fabricated in GaAs layers grown on SOS Substrates

Device-quality GaAs layers have been grown on silicon-on-sapphire (SOS) substrates by molecular beam epitaxy (MBE). Microwave MESFET's (gate length of ~0.8 µm) with transconductance of 140 mS/ mm,f_{max} = 20GHz, andf_{T} = 8.3GHz have been fabricated in these layers.     

A dc and microwave comparison of GaAs MESFET's on GaAs and Si substrates

In order to assess GaAs on Si technology, we have made a performance comparison of GaAs MESFET's grown and fabricated on Si and GaAs substrates under identical conditions and report the first microwave results. The GaAs MESFET's on Si with 1.2-µm gate length (290-µm width) exhibited transconductances (gm) of 180 mS/mm with good saturation and pinchoff whereas their counterparts on GaAs substrates exhibited gmof 170 mS/mm. A current gain cut-off frequency of 13.5 GHz was obtained, which compares with 12.9 GHz observed in similar-geometry GaAs MESFET's on GaAs substrates. The other circuit parameters determined from S-parameter measurements up to 18 GHz showed that whether the substrate is Si or GaAs does not seem to make a difference. Additionally, the microwave performance of these devices was about the same as that obtained in devices with identical geometry fabricated at Tektronix on GaAs substrates. The side-gating effect has also been measured in both types of devices with less than 10-percent decrease in drain current when 5 V is applied to a pad situated 5 µm away from the source. The magnitude of the sidegating effect was identical to within experimental determination for all side-gate biases in the studied range of 0 to -5 V. The light sensitivity of this effect was also very small with a change in drain current of less that 1 percent between dark and light conditions for a side gate bias of -5 V and a spacing of 5 µm. Carrier saturation velocity depth profiles showed that for both MESFET's on GaAs and Si substrates, the velocity was constant at 1.5 × 10⁷cm/s to within 100-150 Å of the active layer-buffer layer interface.     

A 630-mS/mm GaAs MESFET with Au/WSiN refractory metal gate

GaAs MESFET's with a gate length as low as 0.2 μm have been successfully fabricated with Au/WSiN refractory metal gate n⁺-self-aligned ion-implantation technology. A very thin channel layer with high carrier concentration was realized with 10-keV ion implantation of Si and rapid thermal annealing. Low-energy implantation of the n⁺-contact regions was examined to reduce substrate leakage current. The 0.2-μm gate-length devices exhibited a maximum transconductance of 630 mS/mm and an intrinsic transconductance of 920 mS/mm at a threshold voltage of -0.14 V     

GaAs MESFET ring oscillator on Si substrate

GaAs MESFET ring oscillators were fabricated on a Si substrate and successfully operated. Epitaxial techniques to grow a GaAs layer on a Si substrate were investigated. The device-quality GaAs epitaxial layer was obtained by introducing a Ge layer (by ionized cluster-beam deposition) and alternating GaAs/GaAIAs layers (by MOCVD). The typical transconductance of 140 mS/mm was obtained for the FET with a 0.5 µm × 10 µm gate. The minimum delay time was 66.5 ps/ gate at a power consumption of 2.3 mW/gate.     

Electron-beam fabrication of GaAs low-noise MESFET's using a new trilayer resist technique

A LO/HI/LO resist system has been developed to produce sub-half-micrometer T-shaped cross section metal lines using e-beam lithography. The system provides T-shaped resist cavities with undercut profiles. T-shaped metal lines as narrow as 0.15 µm have been produced. GaAs MESFET's with 0.25-µm T-shaped Ti/Pt/Au gates have also been fabricated on MBE wafers using this resist technique. Measured end-to, end 0.25-µm gate resistance was 80 ω/mm, dc transconductance gmas high as 300 mS/mm was observed. At 18 GHz, a noise figure as low as 1.4 dB with an associated gain of 7.9 dB has also been measured. This is the lowest noise figure ever reported for conventional GaAs MESFET's at this frequency. These superior results are mainly attributed to the high-quality MBE material and the advanced T-gate fabrication technique employing e-beam lithography.     

1.5 nm direct-tunneling gate oxide Si MOSFET's

In this paper, normal operation of a MOSFET with an ultra-thin direct-tunneling gate oxide is reported for the first time. These high current drive n-MOSFET's were fabricated with a 1.5 nm direct-tunneling gate oxide. They operate well at gate lengths of around 0.1 μm, because the gate leakage current falls in proportional to the gate length, while the drain current increases in inverse proportion. A current drive of more than 1.0 mA/μm and a transconductance of more than 1,000 mS/mm were obtained at a gate length of 0.09 μm at room temperature. These are the highest values ever obtained with Si MOSFET's at room temperature. Further, hot-carrier reliability is shown to improve as the thickness of the gate oxide is reduced, even in the 1.5 nm case. This work clarifies that excellent performance-a transconductance of over 1,000 mS/mm at room temperature-can be obtained with Si MOSFET's if a high-capacitance gate insulator is used     

The n-channel SiGe/Si modulation-doped field-effect transistor

At the heterointerface of Si1-xGex/Si the existence of two-dimensional carrier gas has recently been demonstrated. The electrons are confined inside the large-gap material Si. We report the first fabrication of n-channel modulation-doped SiGe/Si hetero field-effect transistors by use of molecular-beam epitaxial growth. Though neither layer sequence nor parasitic resistances were optimized, these first transistors exhibit an extrinsic transconductance of 40 mS/mm for a gate length of 1.6 µm. This value is higher than that of conventional Si MESFET's of comparable carrier concentration. Technological processing steps and device evaluation are described.     

A novel camel diode gate GaAs FET

A novel device utilizing the "camel diode" in place of a Schottky barrier gate has been demonstrated in GaAs grown by molecular beam epitaxy (MBE). The devices have a 7.5 µm channel length, 3 µm gate length, and a 280 µm gate width. The layers from which the devices are fabricated consist of a 0.15 µm GaAs layer doped to a level of 1.5 × 10¹⁷cm^-3to form the channel, and a 100 Å p+GaAs and a 400 Å n+ region to form the gate. Because of the long gate length, the electron velocity does not reach saturation, thus a transconductance of 80 mS/mm is obtained. A simple theory describing the device operation has also been developed.     

MESFET's on a GaAs-on-insulator structure

MESFET's were fabricated on a GaAs-on-insulator structure which was grown by molecular beam epitaxy (MBE) on a GaAs substrate covered with a crystalline insulator film, CaxSr1-xF2. The gmvalue of 71 mS/mm was obtained for an FET with a gate length of 3 µm. Complete isolation of MESFET's by island formation of GaAs on the fluoride films was also attained for the first time using a conventional wet etching process.     

Monolithic integration of GaAs/AlGaAs double-heterostructure LED's and Si MOSFET's

Fully monolithic integration of interconnected GaAs/Al-GaAs double-heterostructure LED's and Si MOSFET's is demonstrated for the first time. The Si MOSFET's, with a gate length of 5 µm and gate width of 1.6 mm, have almost the same characteristics as those of control devices fabricated on a separate Si wafer. The LED output collected by a microscope lens with a numerical aperture of 0.65 is about 6.5 µW at 100- mA dc current. LED modulation rates up to 27 Mbit/s have been achieved by applying a stream of voltage pulses to the MOSFET gate. The modulation rate is limited by the speed of the MOSFET.     

GaAs MESFET's fabricated on InP substrates

This paper reports the first successful MESFET fabrication in GaAs layers grown directly on InP substrates by molecular beam epitaxy (MBE). The fabricated GaAs MESFET's exhibit good I-V curves with complete pinch-off and saturation characteristics. About 100-mS/ mm transconductance was obtained for a 1.2-µm gate length device.     

GaAs LSI-directed MESFET's with self-aligned implantation for n+-layer technology (SAINT)

Self-aligned implantation for n⁺-layer technology (SAINT) has been developed for improvement in normally-off GaAs MESFET's to be used in LSI's. This technology has made it possible to arbitrarily control the spacing between the n⁺-implanted layer and gate contact by a dielectric lift-off process utilizing a multilayer resist with an undercut wall shape. SAINT FET's with a 1-µm gate length have above 200 mS/ mm transconductance in the normally-off region. The K value along the square-lawI - Vfitting has been improved by a factor of 3.4, compared to conventional FET's without the n⁺-layer. Thermal emission for carriers from the source n⁺-layer in the subthreshold region has been experimentally formulated. Threshold-voltage shift due to gate shortening for [011] gate FET's is definitely smaller than that for [011] gate FET's. The threshold-voltage standard deviations for [011] gate FET's with 2- and 1-µm gate lengths, obtained from a 6-mm × 9-mm area, are 9 and 34 mV, respectively. An E/D direct-coupled FET logics (DCFL) 15-stage ring oscillator with a 1-µm gate length shows a high switching speed of 45 ps/gate at a low supply voltage of 0.91 V.     

Ion-implantation and activation behavior of Si in MBE-Grown GaAs on Si substrates for GaAs MESFET's

The suitability of MBE-grown GaAs layers on Si substrates has been studied for ion-implanted GaAs MESFET technology. The undoped as-grown GaAs layers had a carrier concentration below 10¹⁴cm^-3. Uniform Si ion implants into 4-µm-thick GaAs layers on Si were annealed at 900°C for 10 s, using a rapid-thermal-annealing (RTA) system. Both the activation and the doping profile were similar to those obtained in bulk semi-insulating GaAs under similar conditions. The SIMS profiles of Si and As atoms near the GaAs/Si heterointerface were identical before and after the RTA process, indicating negigible interdiffusion during the implant activation. Dual implants of a shallow n+ layer and an n-channel layer were used to fabricate GaAs MESFET's with a recess-gate technology. Selective oxygen ion implantation was used for device isolation. The maximum transconductance obtained was 135 mS/ mm compared to typical values of 150-180 mS/mm obtained in our laboratory on GaAs substrates in similar device structures.     

Subhalf-micrometer p-channel MOSFET's with 3.5-nm gate Oxide fabricated using X-ray lithography

Subhalf-micrometer p-channel MOSFET's with ultra-thin gate oxide (3.5 nm) have been fabricated using X-ray lithography and electron cyclotron resonance (ECR) plasma etching. The fabricated MOSFET's with 0.2-µm channel lengths show long-channel behavior and extremely high (200 mS/mm) transconductance.     

High-transconductance enhancement-mode GaAs MESFET fabrication technology

An improved enhancement-mode GaAs MESFET was fabricated by a high dose Si ion implantation which was used to reduce the source and drain parasitic resistances, and by a Pt buried gate which was used to control the threshold voltage and reduce the interface states of the Schottky gate. 250 mS/mm transconductance has been obtained for 1-µm gate-length enhancement-mode GaAs MESFET.     

In0.53Ga0.47As FET's with insulator-assisted Schottky gates

Schottky-gate FET's have been fabricated on n-type In0.53Ga0.47As using a thin interfacial silicon nitride layer between the metal and the epitaxial layer to reduce the gate leakage current. In0.53Ga0.47As was grown by molecular beam epitaxy on semi-insulating InP substrates and silicon nitride was grown by plasma-enhanced chemical vapor deposition. Devices with 1.2µm gate length and net donor doping in the mid 10¹⁶cm^-3range show dc transconductance of up to 130mS/mm. Both depletion and enhancement mode operation were observed. The effective saturation velocity of electrons in the channel is deduced to be 2.0 ± 0.5 × 10⁷cm/sec, a value 60 to 70% higher than that in GaAs MESFET's. The insulator-assisted gate technology has many advantages in fabrication flexibility and control compared with other approaches to realizing high-speed microwave and logic in FET's in In0.53Ga0.47As.     

Self-aligned half-micrometer Silicon MASFET's with metallic amorphous Silicon gate

Ternary metallic amorphous silicon (a-Si-Ge-B), having a high barrier height feature with crystalline semiconductors is applied to the gate metal of Si MESFET's. A submicrometer gate length is successfully fabricated using a self-aligned technology and a conventional photolithography. A large transconductance above 130 mS/mm under the normally-OFF state and a small standard deviation of threshold voltage less than 11 mV are realized for a 0.5-µm gate-length device across a 4-in-diameter wafer. A minimum delay time of 114 ps/gate with an associated switching energy of 1.6 pJ and a minimum switching energy of 3.3 fJ with a delay time of 26 ns/gate are attained by a 21-stage ring oscillator with E/R direct-coupled FET logic circuits.     

Very short gate-length GaAs MESFET's

GaAs MESFET's with gate lengths ranging from 0.36 µm down to 0.055 µm, the smallest so far reported, have been fabricated using electron-beam lithography. DC output characteristics were obtained from all of the devices tested and transconductances up to 300 mS/mm were measured. However it was observed that there is a maximum drain-source voltage that can be pinched off in these short gate devices. This voltage varies exponentially from 1 V in the 0.055-µm gate devices to 6 V in the 0.36-µm device. It is speculated that this effect is due to current injection into the buffer layer.