Fast-response single-inductor dual-output hysteresis-current-controlled DC–DC buck converter

A fast-response single-inductor dual-output hysteresis-current-controlled DC–DC buck is proposed for enhancing the transient characteristics of switching DC–DC converters and fabricated with TSMC 0.35 μm DPQM CMOS processes. By adopting a hysteresis-current-controlled DC–DC buck converter, it is demonstrated that the hysteresis-current-controlled technique have improved dynamic response of load variations whether the load current is light or heavy. Fast-response structure achieves 5 μs response with load variation which betweens 10 and 110 mA. Also proposed single-inductor dual-output structure is a time-multiplexing circuit to decrease the influence of cross regulation than that of previous designs. With a 3.6 V input power supply, the DC–DC buck converter precisely provides an adjustable power output with a voltage range from 0.9 to 3 V.     

A high efficiency 4-output single inductor DC–DC buck converter with self boosted snubber

This paper presents a single-inductor 4-outputs DC–DC buck converter. In order to independently regulate the four output voltages, a multiple control loop operates on linear combinations of the output voltage errors. An original self-boosted snubber circuit enables load power switches control signals boosting without area and power efficiency penalties. The circuit, fabricated using a 0.5-μm CMOS process, provides four output voltages that can be independently regulated from 0 V to the used supply voltage −500 mV. The supply voltage can range from 2.3 up to 5 V. The overall minimum and maximum output currents are 0.15 and 1.8 A, respectively. The measured maximum cross regulation is 40 mV/V with a peak of power efficiency equal to 85%.     

An ultra-low power CMOS DC–DC buck converter with double-chain digital PWM technique

In present-day integrated digital circuits are become attractive choice for the DC–DC buck converters. This paper proposes a novel approach of CMOS DC–DC buck converter with double-chain digital pulse width modulation (PWM) for ultra-low power applications. The proposed digital PWM architecture consists of double delay lines which is to reduce power consumption and improves ripple voltage with the resolution. An algorithm is proposed that describes the operation of digital PWM. The double chain digital PWM is implemented and analyzed in cadence platform using commercial 180 nm TSMC design kit. The promising results reveals that the power consumption is reduces up to 1.16 µW with occupies less area under the operating frequency of 100 kHz. The DC–DC buck converter with proposed PWM achieves peak efficiency of 92.6% including a load current range of 4–10 mA. This proposed digital PWM method demonstrates its ability to minimize the ripple voltage by 49% and enables to DC–DC converter for compose in a compact chip area as compared to conventional converters. Measured and Simulated power efficiency are made good agreement with each other.     

A DC–DC buck converter with load-regulation improvement using dual-path-feedback techniques

A DC–DC buck converter using dual-path-feedback techniques is proposed in this paper. The proposed converter is fabricated with TSMC 0.35 μm DPQM CMOS process. The structure of the proposed buck converter includes the voltage-feedback and current-feedback design to improve load regulation and achieve high efficiency. The experimental results show the maximum power efficiency is about 94 %. The load regulation is 6.22 (ppm/mA) when the load current changes from 0 to 300 mA. With a 3.6 V input power supply, the proposed buck converter provides an adjustable power output with a voltage range is from 1 to 3 V precisely.     

High efficiency,high switching speed,AlGaAs/GaAs P-HEMT DC–DC converter for integrated power amplifier modules

This paper presents a high efficiency, high switching frequency DC–DC buck converter in AlGaAs/GaAs technology, targeting integrated power amplifier modules for wireless communications. The switch mode, inductor load DC–DC converter adopts an interleaved structure with negatively coupled inductors. Analysis of the effect of negative coupling on the steady state and transient response of the converter is given. The coupling factor is selected to achieve a maximum power efficiency under a given duty cycle with a minimum penalty on the current ripple performance. The DC–DC converter is implemented in 0.5 μm GaAs p-HEMT process and occupies 2 × 2.1 mm² without the output network. An 8.7 nH filter inductor is implemented in 65 μm thick top copper metal layer, and flip chip bonded to the DC–DC converter board. The integrated inductor achieves a quality factor of 26 at 150 MHz. The proposed converter converts 4.5 V input to 3.3 V output for 1 A load current under 150 MHz switching frequency with a measured power efficiency of 84%, which is one of the highest efficiencies reported to date for similar current/voltage ratings.     

Integrated on-chip 0.35 μm BiCMOS current-mode DC–DC buck converter

A current-mode DC–DC buck converter with a fully integrated power module is presented in this article. The converter is implemented using BiCMOS technology in amplifier and power MOSFET in a current sensor. The current sensor is realised by the power lateral double-diffused MOSFET with the aspect ratio much larger than that of a matched p-MOSFET. In addition, BiCMOS technology is applied in the error amplifier for an accurate current sensing and a fast transient response. The DC–DC converter is fabricated with 0.35?µm BiCMOS process. Experimental results show that the fully integrated converter operates at 1.3?MHz switching frequency with a supply voltage of 5?V. The output DC voltage is obtained as expected and the output ripple is controlled to be within 2% with a 30?µH off-chip inductor and 100?µF off-chip capacitor.     

A CMOS micro power switched-capacitor DC–DC step-up converter for indoor light energy harvesting applications

This paper presents a micro power light energy harvesting system for indoor environments. Light energy is collected by amorphous silicon photovoltaic (a-Si:H PV) cells, processed by a switched capacitor (SC) voltage doubler circuit with maximum power point tracking (MPPT), and finally stored in a large capacitor. The MPPT fractional open circuit voltage (V_OC) technique is implemented by an asynchronous state machine (ASM) that creates and dynamically adjusts the clock frequency of the step-up SC circuit, matching the input impedance of the SC circuit to the maximum power point condition of the PV cells. The ASM has a separate local power supply to make it robust against load variations. In order to reduce the area occupied by the SC circuit, while maintaining an acceptable efficiency value, the SC circuit uses MOSFET capacitors with a charge sharing scheme for the bottom plate parasitic capacitors. The circuit occupies an area of 0.31 mm² in a 130 nm CMOS technology. The system was designed in order to work under realistic indoor light intensities. Experimental results show that the proposed system, using PV cells with an area of 14 cm², is capable of starting-up from a 0 V condition, with an irradiance of only 0.32 W/m². After starting-up, the system requires an irradiance of only 0.18 W/m² (18 μW/cm²) to remain operating. The ASM circuit can operate correctly using a local power supply voltage of 453 mV, dissipating only 0.085 μW. These values are, to the best of the authors’ knowledge, the lowest reported in the literature. The maximum efficiency of the SC converter is 70.3 % for an input power of 48 μW, which is comparable with reported values from circuits operating at similar power levels.     

A wide output range voltage-mode buck converter with fast voltage–Tracking speed for RF power amplifiers

A high switching frequency voltage-mode buck converter with fast voltage-tracking speed, wide output range and PWM/PSM control strategy for radio frequency (RF) power amplifiers (PAs) has been proposed. To achieve the fast voltage-tracking speed, the maximum charging and discharging current control method has been used, and the filter inductor and capacitor values are reduced. A novel compensated error amplifier (EA) is presented to realize the wide output range. The investigated converter has been fabricated with GF 0.35 μm CMOS process and can operate at 5 MHz with the output voltage range from 0.6 V to 3.4 V. The experimental results show that the voltage-tracking speed can achieve 8.8 μs/V for up-tracking and 6 μs/V for down-tracking. Besides, the recovery time is less than 8 μs when the load change step is 400 mA.     

A feedback loop regulated bootstrap driver circuit with improved drive capability for high voltage buck DC–DC converter

A novel bootstrap driver circuit applied to high voltage buck DC–DC converter is proposed. The gate driver voltage of the high side switch is regulated by a feedback loop to obtain accurate and stable bootstrapped voltage. The charging current of bootstrap capacitor is provided by the input power of the DC–DC converter directly instead of internal low voltage power source, so larger driver capability of the proposed circuit can be achieved. The bootstrap driver circuit starts to charge the bootstrap capacitor before the switch node SW drop to zero voltage at high-side switch off-time. Thus inadequate bootstrap voltage is avoided. The proposed circuit has been implemented in a high voltage buck DC–DC converter with 0.6 µm 40 V CDMOS process. The experimental results show that the bootstrap driver circuit provides 5 V stable bootstrap voltage with higher drive capability to drive high side switch. The proposed circuit is suitable for high voltage, large current buck DC–DC converter.     

Limitation of soft-switching technique in AC/DC power converter’s efficiency improvement

Soft-switching techniques are attractive to unity-power-factor AC/DC converter in the view of the size reduction and EMI suppression. A soft-switched boost PFC converter has been studied based on its topology analysis, PSIM simulation and circuit experiment. A special limitation of soft-switching techniques has been found in their AC/DC applications. Sponsored by the Scientific Research Foundation for the Returned Overseas Chinese Scholars, Ministry of Education     

A current-mode buck DC–DC controller with adaptive on-time control

A current-mode buck DC–DC controller based on adaptive on-time (AOT) control is presented. The on-time is obtained by the techniques of input feedforward and output feedback,and the adaptive control is achieved by a sample-hold and time-ahead circuit. The AOT current-mode control scheme not only obtains excellent transient response speed,but also achieves the independence of loop stability on output capacitor ESR. In addition,the AOT current-mode control does not have subharmonic oscillation phenomenon seen...     

A single-input dual-output 13.56 MHz CMOS AC–DC converter with comparator-driven rectifiers for implantable devices

A highly efficient single-input, dual-output AC–DC converter for wireless power transfer in implantable devices is implemented using the 0.18-µm CMOS process. The proposed AC–DC converter, consisting of three rectifiers with cross-coupled NMOS transistors and comparator-driven PMOS transistors, achieves up to 79.5% power conversion efficiency at 13.56 MHz operation frequency in order to provide dual outputs of 1.2 V and 2.2 V DC voltages along with 6.2 mA and 22.6 mA of current, respectively, to the implant device from a single RF input. The designed IC consumes a core die area of 0.18 mm².     

Single-stage three-phase boost power factor correction circuit for AC–DC converter

This article presents a single-stage three-phase power factor correction (PFC) circuit for AC-to-DC converter using a single-switch boost regulator, leading to improve the input power factor (PF), reducing the input current harmonics and decreasing the number of required active switches. A novel PFC control strategy which is characterised as a simple and low-cost control circuit was adopted, for achieving a good dynamic performance, unity input PF, and minimising the harmonic contents of the input current, at which it can be applied to low/medium power converters. A detailed analytical, simulation and experimental studies were therefore conducted. The effectiveness of the proposed controller algorithm is validated by the simulation results, which were carried out using MATLAB/SIMULINK environment. The proposed system is built and tested in the laboratory using DSP-DS1104 digital control board for an inductive load. The results revealed that the total harmonic distortion in the supply current was very low. Finally, a good agreement between simulation and experimental results was achieved.     

A voltage mode buck DC–DC converter with automatic PWM/PSM mode switching by detecting the transient inductor current

This paper presents a voltage mode buck DC–DC converter that integrates pulse-width modulation (PWM) and pulse-skipping modulation (PSM) to achieve high efficiency under heavy and light load conditions, respectively. Automatic mode-switching is implemented simply by detecting the voltage drop of high-side power switch when it is on, which indicates the transient current flowing through the inductor. Unlike other methods based on average current sensing, the proposed auto-mode switching scheme is implemented based on voltage comparison and simple control logic circuit. In order to avoid unstable mode switching near the load condition boundary, the mode switching threshold voltage is set differently in PWM and PSM mode. Besides, a 16-cycle counter is also used to ensure correct detection of the change in the load condition and fast response of the converter. In addition, a dual-path error amplifier with clamp circuit is also adopted to realize loop compensation and ensure 100 % duty cycle operation. Fabricated in a 0.18-μm standard CMOS technology, the DC–DC converter is able to operate under supply voltage from 2.8 to 5.5 V with 3-MHz clock frequency. Measurement results show that the converter achieves a peak efficiency of 93 %, and an output voltage ripple of less than 40 mV, while the chip area is 1.02 mm².     

A soft-switching coupled inductor bidirectional DC–DC converter with high-conversion ratio

A soft-switching bidirectional DC–DC converter is presented herein as a way to improve the conversion efficiency of a photovoltaic (PV) system. Adoption of coupled inductors enables the presented converter not only to provide a high-conversion ratio but also to suppress the transient surge voltage via the release of the energy stored in leakage flux of the coupled inductors, and the cost can kept down consequently. A combined use of a switching mechanism and an auxiliary resonant branch enables the converter to successfully perform zero-voltage switching operations on the main switches and improves the efficiency accordingly. It was testified by experiments that our proposed converter works relatively efficiently in full-load working range. Additionally, the framework of the converter intended for testifying has high-conversion ratio. The results of a test, where a generating system using PV module array coupled with batteries as energy storage device was used as the low-voltage input side, and DC link was used as high-voltage side, demonstrated our proposed converter framework with high-conversion ratio on both high-voltage and low-voltage sides.     

A fully integrated switched-capacitor DC–DC converter with hybrid output regulation

In this paper, we propose a fully integrated switched-capacitor (SC) DC–DC converter with hybrid output regulation that allows a predictable switching noise spectrum. The proposed hybrid output regulation method is based on the digital capacitance modulation for fine regulation and the automatic frequency scaling for coarse regulation. The automatic frequency scaler and on-chip current sensor are implemented to adjust the switching frequency at one of the frequencies generated by a binary frequency divider with change in load current. Thus, the switching noise spectrum of the proposed SC DC–DC converter can be predicted over the entire load range. In addition, the bottom-plate losses due to the parasitic capacitances of the flying capacitors and the gate-drive losses due to the gate capacitances of switches are reduced at light load condition since the switching frequency is automatically adjusted. The proposed SC DC–DC converter was implemented in a 0.13 µm CMOS process with 1.5 V devices, and its measurement results show that the peak efficiency and the efficiency at light load condition are 69.2% and higher than 45%, respectively, while maintaining a predictable switching noise spectrum.     

A transient enhanced DVS DC–DC converter based on state trajectory analysis

Dynamic voltage scaling (DVS) can effectively reduce energy consumption by dynamically varying the supply voltage of the system accordingly to the clock frequency. A new DVS-enabled DC–DC converter is presented in this paper. State trajectory is employed to analyze the transient features of PWM and PFM Buck converters. A novel transient enhancement circuit is designed to improve the transient response of the DVS-enabled Buck converter. To further expand the output voltage range of the converter, a current-starved voltage controlled delay line is proposed in the controller of DC–DC converter to obtain an ultra low voltage of 0.5 V. When the input voltage is 3.3 V, the output voltage of the converter can be dynamically regulated from 0.5 to 2.0 V. The output voltage tracking speed is less than 7.5 μs/V and the recovery speed is 33 μs/A for a load current step from 0.6 to 0.2 A at output voltage of 0.5 V. The chip area is 1.75 mm × 1.33 mm in a 0.18 μm standard CMOS process.     

A chlorinated copolymer donor demonstrates a 18.13% power conversion efficiency

The rapid development of low-bandgap(LBG)nonfullerene acceptors and wide-bandgap(WBG)copolymer donors in recent years has boosted the power conversion efficiency(PCE)of organic solar cells(OSCs)to the 18%level[1?21].The commercialization of OSCs is highly expected.However,critical issues like the cost and the stability also determine whether OSCs can enter the market or not[22].     

A contactless power transfer system using a series–series–parallel resonant converter

In this article, a contactless power transfer system using a series–series–parallel resonant converter (SSPRC) is proposed. The proposed converter can improve on or eliminate the disadvantages of the contactless system based on conventional resonant converters, since it independently compensates for a primary side leakage inductance, a secondary side leakage inductance and a magnetising inductance. The proposed converter also reduces the circulating currents and the reactive power by controlling the phase angle difference between the inverter output voltage and the current. In addition, the system design can be simplified, since the voltage gain is determined only by the transformer turns ratio for the overall load range without being affected by the other transformer parameters. The proposed converter is analysed with respect to the gain and current margin. The system design procedure is then described for the proposed circuit based on the circuit analysis. Finally, the experimental results are presented in order to verify the proposed contactless power supply.