Enhanced split-architecture delta–sigma ADCs

A split delta–sigma ADC topology is proposed, which provides enhanced noise shaping by cross-coupling the quantization errors of the two halves of the structure. Unlike the multi-stage noise shaping (MASH) architecture, the new structure is insensitive to mismatch errors, and it does not reduce the stability of the loops. Simulations confirm the effectiveness of the proposed scheme.     

Reliability aware design of low power continuous-time sigma–delta modulator

Circuit reliability has become a major bottleneck due to ageing degradation. In this paper, reliability-aware methodology and ageing analysis of low power sigma–delta (ΣΔ) modulator are presented. HCI and NBTI are considered as the dominating ageing effects. A second order continuous-time (CT) ΣΔ modulator is implemented for medical application. Ageing estimation is performed at both behavioral and transistor level. Results at behavioral level and transistor level show that the feedback loop in CT ΣΔ modulator is more sensitive and less reliable than the analog loop filter. Comparing with HCI, NBTI is the dominating ageing effect in the designed CT ΣΔ modulator.     

Top-down design methodology of a multi-bit continuous-time delta–sigma modulator

Transistor-level simulation of complex systems involving analog and digital parts is a time-consuming task. The growing interaction of analog and digital devices calls for the use of top-down design methodologies, resulting in behavioral modeling at different levels of abstraction. In this article, an advanced design methodology using a combination of behavioral models and transistor-level models is presented. This methodology is very interesting for complex mixed-signal IC design, improving the design flexibility and reducing the simulation time. To validate the proposed methodology, a continuous-time delta–sigma modulator based on a high-speed low-resolution quantizer is modeled, taking into account their nonidealities such as excess loop delay, clock jitter and feedback DAC element mismatch. The main features of the multi-bit quantizer are 3-bit resolution with 4 GHz sampling rate and FOM of about 7 pJ/conv. This modulator samples signals at high-IF, performing directly the analog-to-digital conversion in the modern RF front-end receivers.     

Systematic approach to the synthesis of continuous-time cascaded sigma–delta modulators

This paper deals with a systematic approach to the synthesis of continuous-time cascaded sigma–delta modulators. Based on a system-theoretical model, a detailed derivation of the digital cancelation filters for continuous-time cascaded architectures is presented in order to achieve maximum signal-to-noise ratio together with optimal anti-aliasing performance. By using the same model, an exact equation for the performance loss of any cascaded architecture is derived. The latter is due to the scaling for stability and given relative to an ideal high-pass filter of the overall modulator order. Finally, an analytical calculation of optimal scaling coefficients in between the stages is performed, resulting in a limited search-space for these coefficients. Theoretical results are verified by simulations.     

A low power dissipation high-speed CMOS image sensor with column-parallel sigma–delta ADCs

A 60frames/s CMOS image sensor with column-parallel inverter-based sigma–delta (ΣΔ) ADCs is proposed in this paper. In order to improve the robustness of the inverter, instead of constant power supply, two buffers are designed to provide power supply for inverters. Instead of using of an operational amplifier, an inverter-based switch-capacitor (SC) circuit is adopted to low-voltage low-power ΣΔ modulator. Detailed analysis and design optimization are provided. Due to the use of the inverter-based ΣΔ ADCs, the conversion speed is improved while reducing the area and power consumption. The proposed CMOS image sensor has been fabricated with 0.18 μm CMOS process. The measurement results show that the random noise (RN) is 7e_rms⁻, the pixel conversion gain is 100 μV/e⁻. Since the measured full well capacity of the pixel is 25000e⁻, the CMOS image sensor achieves a 71 dB dynamic range (DR). The total power consumption at 60frame/s is 58.2 mW.     

A 0.5-V 90-dB SNDR 102 dB-SFDR audio-band continuous-time delta–sigma modulator

A 0.5-V high performance continuous-time one-bit delta–sigma modulator is reported for audio applications. High performance under this ultra-low supply is achieved by a feed-forward modulator architecture for reduced integrator swing, a special switched-capacitor-resistor feedback for less sensitivity to jitter noise, and a fast-settling fully differential amplifier. The synthesized modulator also has a high thermal-noise-limited SNR of 91 dB over a 20 kHz bandwidth. The 0.5-V fully-differential gate-input amplifier employs an adaptive common-mode feedback frequency compensation circuit, which leads to a robust modulator performance against process, supply voltage and temperature variations. Fabricated in a standard 0.13 μm CMOS process, the modulator achieves a spurious-free dynamic range (SFDR) of 101.9 dB and a signal-to-noise plus distortion ratio (SNDR) of 90 dB (A-weighted) over a 20-kHz signal bandwidth, with the latter being very close to the thermal noise limit. The modulator operates over a supply range from 0.4 to 0.75 V and a temperature range from −20 to 90°C.     

Compact SC frequency tuning circuit for continuous-time Gm–C filters

A novel automatic frequency tuning circuit for continuous-time filters is presented. Based on the switched-capacitor technique, the circuit offers an advantage in terms of simplicity resulting from the use of only two matched current sources, an operational amplifier with relaxed specifications and a transconductor that is a replica of the filter transconductors. Despite the simplicity of the scheme, the accuracy of the system is less than 1 % of frequency error. The circuit has been designed in a 0.5 μm CMOS technology with a 3.3 V power supply and simulation results confirm the suitability of the proposed approach.     

Low-clock-speed time-interleaved architecture for a polar delta–sigma modulator transmitter

The polar delta–sigma modulator (DSM) transmitter architecture exhibits good coding efficiency and can be used for software-defined radio applications. However, the necessity of high clock speed is one of the major drawbacks of using this transmitter architecture. This study proposes a low-complexity time-interleaved architecture for the polar DSM transmitter baseband part to reduce the clock speed requirement of the polar DSM transmitter using an upsampling technique. Simulations show that using the proposed four-branch time-interleaved polar DSM transmitter baseband part, the clock speed requirement of the transmitter is reduced by four times without degrading the signal-to-noise-and-distortion ratio.     

A study of excess loop delay in tunable continuous-time bandpass delta–sigma modulators using RC-resonators

Excess loop delay is one of the most critical non-idealities of continuous-time delta–sigma modulators as it leads to degradation of the signal-to-noise-ratio or even instability. A comprehensive study of the impact of excess loop delay on tunable continuous-time bandpass delta–sigma modulators using RC-resonators is performed in this paper, both analytically and by simulations. Moreover, a detailed analysis of the conventional compensation techniques for single-band continuous-time bandpass modulators as well as their adaptability to tunable bandpass modulators is performed. The results indicate that only tuning of the scaling coefficients is suitable to compensate for excess loop delay in high-speed tunable bandpass modulators. Based on this result, an approach to the compensation of excess loop delay is proposed which maps the poles of the noise transfer function (NFT) to almost ideal and thus stable positions. Excess loop delay equal to one clock cycle may thus be compensated while the available tuning range of the center frequency depends on the order and the out-of-band-gain of the NFT. A prototype implemented on a printed circuit board proves the feasibility of the proposed approach.     

A sigma–delta interface ASIC for force-feedback micromachined capacitive accelerometer

A single-loop fourth-order sigma?Cdelta (????) interface circuit for micromachined accelerometer is presented in this study. Two additional electronic integrators are cascaded with the micromachine sensing element to form a fourth-order loop filter to eliminate quantization noise. A precise model for the overall system is set up based on nonlinear model of 1-bit quantizer. Three main noise sources affecting the overall system resolution of a ???? accelerometer: mechanical noise, electronic noise and quantization noise are analyzed in more detail. A switched-capacitor charge integrator and correlated double sampling are applied to reduce input-referred electronic noise. The ASIC is fabricated in 0.5???m two-metal two-poly n-well CMOS process, and test results show that the noise density floors of the open-loop and closed-loop modes are 12 and 80???g/Hz^1/2, respectively, the sensitivity is 1.25?V/g, the full measurement range can be achieved from ?2 to +2?g, and the power dissipation is 40?mW.     

Analog sigma–delta modulation with Op-Amp gain compensation for nanometer technologies

A new method that compensates for low DC gain in operational amplifiers (Op-Amps) used in discrete time $\Sigma\Delta$ Σ Δ modulators is described. Measuring and buffering the error at the Op-Amps inverting terminals enables a complete cancellation of the phase error. Nanometer Op-Amps that achieve low gain but very high bandwidth become usable at oversampling rates that still present DC gain limitation. Simulations at behavioral and 65 nm CMOS transistor level implementation verify the effectiveness of the proposed technique.     

Time-based all-digital sigma–delta modulators for nanometer low voltage CMOS data converters

A phase-based delta?Csigma (????) analog-to-digital converter (ADC) is proposed and the idea is demonstrated using two architectures. The first architecture adopts a delay-locked-loop (DLL) mechanism. It is realized by a modification of a DLL using a voltage-controlled delay line (VCDL) based quantizer and a charge pump in the feedback path. The proposed architecture offers both reference jitter shaping and quantization noise shaping. Simulation results show that the proposed ???? ADC achieved 50.5?dB SNDR or 8.09?bits resolution for a 10?MHz signal bandwidth. The second architecture adopts a combination of voltage-controlled and digitally-controlled delay lines (VCDL?CDCDL) as the phase-domain counterparts of an ADC?CDAC in a traditional delta?Csigma modulator. Simulation results of the new modulator achieve a 57.8?dB SNR, or a 9.28 bit over a 10?MHz bandwidth.     

A 0.8-V 816-nW delta–sigma modulator for low-power biomedical applications

This letter discusses the implementation of a low-voltage, low-power delta–sigma modulator as a sensing stage for biomedical applications. A distributed feed-forward structure and bulk-driven operational transconductance amplifier are used in order to achieve efficient operation at a supply voltage of 0.8 V. Instead of conventional low-voltage amplifier architectures, our design uses folded-cascode amplifiers, although they are not used in most low-voltage circuits. A wide input swing is achieved by using the bulk-driven approach, and the drawback of the limited voltage swing of the cascoded output stage is overcome by the distributed feed-forward modulator. The designed modulator has a dynamic range of 49 dB at a 0.8-V supply voltage and consumes only 816 nW of power for the 250-Hz bandwidth. The core chip size of the modulator is 1000 μm × 500 μm by using the 0.18-μm standard CMOS process.     

Reconfigurable bandpass sigma–delta modulator with programmable NTF for low-IF multi-mode receivers

A new reconfigurable bandpass sigma–delta modulator (BPSDM) structure is proposed for low-IF multi-mode wireless systems. The proposed modulator can be reconfigured to operate in different signal bandwidths and at different signal-to-noise ratios by rearranging and optimizing the order of the noise transfer function of the loop while still maintaining stability. Compared with conventional multi-mode BPSDM, employing cascade structures and multi-bit sub-ADCs, the proposed modulator features many attractive advantages, such as (1) avoiding coefficient mismatch between analog and digital components in cascade structures, (2) avoiding DAC non-linearities that are otherwise introduced by commonly used dynamic element matching techniques, and (3) improving and varying the dynamic range performance while meeting the requirements of different wireless standards.     

A low-distortion multi-bit sigma–delta ADC with mismatch-shaping DACs for WLAN applications

A low-distortion feed-forward MASH2_4b-2_4b sigma–delta analog-to-digital converter (ADC) for wireless local area network (WLAN) applications was presented. The converter exhibits improved performances than the ADCs which have been presented to date by adding a feedback factor in the second stage and employing a 2nd-order noise-shaping dynamic element matching (DEM) scheme. The feedback factor induces a zero in the noise transfer function (NTF) and therefore improves the in-band signal to noise and distortion ratio (SNDR) of the modulator. The mismatch-shaping DEM was introduced and applied to the 4-bit DACs in this paper to improve the resolution and linearity of the ADC. Fabricated in a 0.18 μm CMOS process with single 1.8 V supply voltage, the converter achieves a peak SNDR of 85.4 dB over a 10 MHz bandwidth which implies an effective number of bits (ENOB) of 13.90-bit. The spurious free dynamic range (SFDR) is –94 dB for a 1.25 MHz@–6dBFS input signal at 160 MHz sampling frequency. The occupied area is 0.44 mm² and dissipation power 23.4 mW.     

Implementation of THD-reduction stereo audio amplifier using compensators and sigma–delta modulators

This paper presents an integrated stereo audio amplifier that employs sigma?Cdelta (????) modulation techniques with compensators. Traditional closed-loop audio amplifiers adopt pulse-width modulation or ???? modulation techniques. The design method proposed in this study uses a negative feedback closed-loop system with compensator and ???? modulator. This combination of compensator and ???? modulator significantly reduces the noise and total harmonic distortion (THD) compared with a traditional closed-loop system. The proposed negative feedback loop can automatically compensate for external perturbations, improving the precision of the eventual output. The compensator increases the audio-frequency loop gain, and leads to better rejection of audio-frequency disturbances. At a sample rate of 10?MHz, the proposed audio amplifier achieves 0.04% THD and a signal to noise ratio of 87?dB with efficiency above 92%. The proposed audio amplifier was implemented in a TSMC 3.3?V 0.35???m 2P4M CMOS process.     

Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active–passive loop-filters

The design and optimization methodology for CT ΣΔ modulators with hybrid Active–Passive (AP) loop-filters is indicated in this work. From the discussion, by appropriately scaling the passive filter gain and cooperating with a single-bit quantizer, the hybrid AP loop filtering can achieve an approximated noise-shaping function as a fully active ΔΣ modulator with the same order. The ELD effect in the hybrid AP CT ΔΣ modulator which influences the poles and zeros locations of the Noise Transfer Function (NTF) in the modulator is depicted. This paper also investigates the feasibility of applying the ELD compensation techniques that were used to be implemented in the active integrator’s case to the hybrid AP CT ΔΣ modulator; however, some of them cannot be practically applied since the passive loop-filter cannot perform proportional feedback signal summation. After the discussion and analysis, the technique similar to Vadipour et al. (In: Symposium on VLSI circuits digest of technical papers, 2008) can be easily implemented at circuit-level and after applying it, there is one additional zero to compensate the peak in the NTF. With the help of this technique, the maximum quantizer delay tolerance can be a full clock period. The mentioned ELD compensation technique was applied in a 2nd order CT ΔΣ modulator with an active-RC integrator as the 1st stage and a passive RC filter as the 2nd stage, which was verified by transistor-level simulations in 65 nm CMOS. The circuit exhibits either 67.3 dB or 65.3 of SNDR, under the effect of half clock period or one clock period ELD, respectively; by contrast, without compensation, the system is unstable with both half or one clock period ELD effect. The designed hybrid CT ΔΣ modulator achieves 2 MHz signal bandwidth and consumes 2.54 mW of power.     

New current–mode special function continuous-time active filters employing only OTAs and OPAMPs

This paper reports three current mode second order filters, each of which realizes a specific function without any external passive elements. These filters realize low-pass notch (LPN), high-pass notch (HPN) and all-pass (AP) functions. Two OPAMPs, a double output OTA and a single output OTA are employed for each circuit. The filter structures can be easily cascaded since they have high output impedances. This property is especially useful for achieving high-order filters using these LPN and HPN filters as building blocks. The presented theory is verified with macro models in SPICE simulations and, using the SPICE parameters of the layout technology, post layout simulations are carried out, with parasitics extracted from the layouts of the filter chips.     

Design of a hiccup mode over-current protection circuit for DC–DC switching converters

In the paper an improvement hiccup mode over-current protection circuit is proposed and successfully applied in a typical current-mode DC–DC switching converter. It greatly reduces the circuit power consumption in prolonged overload conditions and can provide smooth self-recovery once the overload condition is removed. By reducing the switching frequency and over-current threshold value, it further improves the effect of over-current protection. The power consumption and implementation area are minimized by digital control. By simulation and verification with HSPICE, the output average current is only 16.8% of the conventional over-current mode in continuous over-current conditions. The presented circuits can automatically recover with the maximum load (5 A) when the overload is removed.