A calculus for four-valued sequential logic

We present a complete axiomatisation for four-valued sequential logic. It consists of nine axioms, from which all valid laws can be derived by equational reasoning. These nine axioms are independent of each other.     

一种模糊动态描述逻辑

分析了目前描述逻辑DL的研究现状和存在的问题,特别是动态描述逻辑DDL作为语义Web逻辑基础所存在的问题。针对语义Web需要处理模糊和不精确知识的特点和需求,对DDL进行了模糊化扩充,提出了一种新的描述逻辑,即模糊动态描述逻辑FDDL。给出了FDDL的语法和语义,研究了FDDL的推理机制。与动态描述逻辑DDL相比,该FDDL可以为语义Web提供更为合理的逻辑基础,弥补了DDL作为语义Web逻辑基础的不足。     

基于形式概念分析的粗糙描述逻辑研究

以往的粗糙描述逻辑(RDL)都是基于传统的粗糙集理论。实际上,经常会出现用形式概念表示一个概念的情况,此时一个自然的问题就是如何处理可能出现的不确定概念。把形式概念分析与粗糙集理论联系起来做为基础,给出可定义概念和不可定义概念的定义,并给出不可定义概念的上近似和下近似,这里的近似定义虽然不同于传统的粗糙近似算子形式,但是有很好的实用性。基于新的上下近似定义,把一组近似算子引入到描述逻辑的结构中,形成一种新的粗糙描述逻辑。给出了相应的语法和语义,最后还给出了扩展的Tableau算法,可以用来解决相应的推理问题。     

Inductive situation calculus

Temporal reasoning has always been a major test case for knowledge representation formalisms. In this paper, we develop an inductive variant of the situation calculus in ID-logic, classical logic extended with inductive definitions. This logic has been proposed recently and is an extension of classical logic. It allows for a uniform representation of various forms of definitions, including monotone inductive definitions and non-monotone forms of inductive definitions such as iterated induction and induction over well-founded posets. We show that the role of such complex forms of definitions is not limited to mathematics but extends to commonsense knowledge representation. In the ID-logic axiomatization of the situation calculus, fluents and causality predicates are defined by simultaneous induction on the well-founded poset of situations. The inductive approach allows us to solve the ramification problem for the situation calculus in a uniform and modular way. Our solution is among the most general solutions for the ramification problem in the situation calculus. Using previously developed modularity techniques, we show that the basic variant of the inductive situation calculus without ramification rules is equivalent to Reiter-style situation calculus.     

Time and logic: A calculus of binary events

Conceiving time as a fundamental notion, the relations between time and logic have been studied since antiquity. In constrast, time is here deduced from the notion of causality. First we introduce the notion of a binary event which generates a bit and thereby marks a point of time. Assuming causality between the binary events allows to map a coherent set of binary events into a simultaneity set of a single point of time. This set provides the base for the definition of an algebra over binary events and a logic over time-bound propositions. The calculus allows the functional and operational specification of processing systems, i. e. their complete specification. As is further shown, a complete specification can be decomposed into a set of liveness properties and a set of safety properties. Finally, the superiority of the calculus to temporal logics is substantiated.     

一种基于扩展描述逻辑的事件实例检测方法

针对事件要素之间客观存在的语义关系以及事件与事件类之间的语义关系进行研究,提出了一种基于扩展描述逻辑的事件实例检测方法。该方法利用事件中的时间、动作、环境要素对事件进行语义补充,然后利用扩展描述逻辑中概念的可满足性和概念包含的推理功能对事件实例进行检测,最后通过实验证明该方法可实现文本中的事件实例检测,准确率达到了85．12％。     

A refinement calculus for specifications in Hennessy-Milner logic with recursion

This paper is about specification and verification of processes, modelled as CCS-agents. We show, by means of examples that Hennessy-Milner Logic (HML) with recursion is a suitable language for expressing implicit or partial specifications. By extending this specification language withrefinement operators, i.e. operators that describe the internal structure of a system, we obtain a calculus for stepwise refinement of agents from a specification in HML to a realisation in CCS. The method is demonstrated by proving the alternating-bit protocol under weak assumptions about the unreliable media.This paper has also be presented at the BCS-FACS workshop on Specification and Verification of Concurrent Systems, University of Stirling, July 1988, under the title: Hennessy-Milner logic with recursion as a specification language, and a refinement calculus based on it.     

Temporal logic based hardware description and its verification with Prolog

Techniques of hierarchical specification and verification of hardware with temporal logic and Prolog are presented by example. Both hardware designs in gates and state-diagrams are translated into a relation between the present and the next state, which is represented in Prolog.¹⁾ Specifications are constructed by temporal logic that can express state sequences (e.g. timing diagrams) easily and also are translated into a relation between the present and the next state in Prolog. The verification method is based upon the temporal logic decision procedure in Ref. 2) and, referring to the relation tables between the present state and the next state, the verifier can reason in both directions—forward and backward in temporal sequences. Prolog has very powerful pattern matching, and its automatic backtracking capabilities facilitate easy-to-write verifier programs. It is concluded that a total verification system handling various design levels can be constructed with temporal logic and Prolog.     

基于时序描述逻辑的Web服务本体语言过程模型语义

针对Web服务本体语言(OWL-S)过程模型存在动态交互和时序特征表达能力不足的问题,提出一种基于时序描述逻辑的过程模型形式化方法。通过对OWL-S过程模型的原子过程和组合过程语义进行形式化的描述,得到了OWL-S的过程模型的动态语义,最终实现了对OWL-S过程模型的形式化建模。实例结果验证了所提方法的可行性,为进一步的分析和验证提供了基础。     

Scheduling in the situation calculus: A case study

We illustrate the utility of the situation calculus for representing complex scheduling tasks by axiomatizing a deadline driven scheduler in the language. The actions arising in such a scheduler are examples of natural actions, as investigated in the concurrent situation calculus by Pinto (PhD thesis, 1994), and later by Reiter (Proc. Common Sense 96, 1996). Because the deadline driven scheduler is sequential, we must first suitably modify Reiter's approach to natural actions so it applies to the sequential case. Having done this, we then show how the situation calculus axiomatization of this scheduler yields a very simple simulator in GOLOG, a situation calculus-based logic programming language for dynamic domains. This revised version was published online in June 2006 with corrections to the Cover Date.     

Predicate abstraction in a program logic calculus

Predicate abstraction is a form of abstract interpretation where the abstract domain is constructed from a finite set of predicates over the variables of the program. This paper explores a way to integrate predicate abstraction into a calculus for deductive program verification based on symbolic execution, where it allows us to infer loop invariants automatically that would otherwise have to be given interactively. The approach has been implemented as a part of the KeY verification system.     

基于描述逻辑的组合知识库推理

由于知识库的定义不同,相近领域的知识库不能相互利用已有知识进行推理。为了联合不同的知识库进行推理,通过对描述逻辑的表现形式进行扩展提出一种组合描述逻辑,并基于概念的相似性将不同的领域概念进行关联,给出组合描述逻辑的语法及语义以及相应的Tableau算法。通过实例表明,组合描述逻辑可以利用已有知识进行推理;组合描述逻辑可以将不同的知识库进行结合,为借用不同知识库的知识进行推理提供一条新的途径。     

基于粗糙描述逻辑的不精确时态知识表示研究

在粗糙描述逻辑基础上扩充不精确时态关系,以满足不精确时态知识表示与推理的需要。首先给出了粗糙集及粗糙描述逻辑的相关概念;接着通过定义粗糙时态描述逻辑不精确时态关系,扩展了粗糙描述逻辑中具体域,并给出了可靠性和完备性证明;最后通过实际例子说明粗糙时态描述逻辑的知识表示和应用,结果表明扩展后的粗糙时态描述逻辑可以实现不精确时态知识的表示与推理。     

基于时序逻辑的UML2.0通信图语义研究

UML2.0通信图可以表示对象之间的交互,很适合用于对系统的交互行为建模,但由于UML缺乏精确语义,使得难以对其所表示的系统行为进行分析和验证.XYZ/E是可执行线性时序逻辑语言,既可描述系统的静态语义和动态语义.在定K.UML2.0通信图的形式化语法的基础上,给出了通信图的XYZ/E时序逻辑语义,为进一步的系统分析和验证提供了形式化基础.