A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.     

A 2.4-GHz ISM-Band Sliding-IF Receiver With a 0.5-V Supply

We report an ultra-low-voltage RF receiver for applications in the 2.4 GHz band, designed in a 90 nm CMOS technology. The sliding-IF receiver prototype includes an LNA, an image-reject LC filter with single-ended to differential conversion, an RF mixer, an LC IF filter, a quadrature IF mixer, RF and IF LO buffers, and an I/Q baseband section with a VGA and a low-pass channel-select filter in each path, all integrated on-chip. It has a programmable overall gain of 30 dB, noise figure of 18 dB, out-of-channel IIP3 of -22 dBm. The 3.4 mm² chip consumes 8.5 mW from a 0.5 V supply.     

A direct-conversion receiver IC for WCDMA mobile systems

A prototype design of a 2.7-3.3-V 14.5-mA SiGe direct-conversion receiver IC for use in third-generation wide-band code-division multiple-access (3G WCDMA) mobile cellular systems has been completed and measured. The design includes a bypassable low-noise amplifier (LNA), a quadrature downconverter, a local-oscillator frequency divider and quadrature generator, and variable-gain baseband amplifiers integrated on chip. The design achieves a cascaded, LNA-referred noise figure (including an interstage surface acoustic wave filter) of 4.0 dB, an in-band IIP3 of -18.6 dBm, and local-oscillator leakage at the LNA input of -112 dBm. The static sensitivity performance of the receiver IC is characterized using a software baseband processor to compute link bit-error rate.     

0.18-/spl mu/m CMOS Bluetooth analog receiver with -88-dBm sensitivity

A CMOS Bluetooth analog low-IF receiver that includes a low-noise amplifier, image-rejection mixer, IF bandpass active filter, and programmable gain amplifier (PGA) was fabricated in a 0.18-/spl mu/m bulk CMOS process. In order to achieve good sensitivity and tolerance against blocking signals, operational amplifiers were used in the active filter and PGA, the filter and PGA were interleaved to minimize noise, and an on-chip automatic tuner adjusts the filter frequency. Other features included a feedforward automatic gain control with rapid convergence. When connected to the digital demodulator of a BiCMOS Bluetooth transceiver, -88-dBm sensitivity was measured at 65-mW power dissipation. All blocking signal specifications were also satisfied.     

10 GHz dual-conversion low-IF downconverter with microwave and analogue quadrature generators

A 10 GHz dual-conversion low-IF downconverter using 0.18-mum CMOS technology is demonstrated. The high-frequency quadrature RF and LO₁ signals are generated by broadside-coupled quadrature couplers while a two-section polyphase filter is utilised for the low-frequency LO₂ quadrature signal generation. As a result, the demonstrated downconverter achieves a conversion gain of 7 dB, IP_{1 dB} of -16 dBm, IIP₃ of -5 dBm and noise figure of 26 dB at a 1.8 V supply. The image-rejection ratio of the first/second image signal is 33/42 dB for IF frequency ranging from 10 to 60 MHz, respectively.     

A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications

A 0.13-mum SiGe BiCMOS double-conversion superheterodyne receiver and transmitter chipset for data communications in the 60-GHz band is presented. The receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, IF amplifier strip, quadrature IF-to-baseband mixers, phase-locked loop (PLL), and frequency tripler. It achieves a 6-dB noise figure, -30 dBm IIP3, and consumes 500 mW. The transmitter chip includes a power amplifier, image-reject driver, IF-to-RF upmixer, IF amplifier strip, quadrature baseband-to-IF mixers, PLL, and frequency tripler. It achieves output P_1dB of 10 to 12dBm, P_sat of 15 to 17 dBm, and consumes 800 mW. The chips have been packaged with planar antennas, and a wireless data link at 630 Mb/s over 10 m has been demonstrated     

基于GP2010的移动GPS射频前端设计

对GPS射频前端进行了研究与设计,实现了GPS信号射频到数字中频的转化过程。应用GP2010芯片设计出了符合要求的GPS射频前端,包括前端滤波器、低噪声放大器,以及中频滤波器。介绍测试系统的搭建,对实际制作的电路板进行调试,并得出测试结果,为后期基于FPGA实现GPS基带数字信号处理提供GPS数字中频信号,为自主设计GPS接收机奠定了基础。     

A W-band image-rejection downconverter

The design, fabrication, and evaluation of a W-band image-rejection downconverter based on pseudomorphic InGaAs-GaAs HEMT technology are presented. The image-rejection downconverter consists of a monolithic three-stage low-noise amplifier, a monolithic image-rejection mixer, and a hybrid IF 90° coupler with an IF amplifier. The three-stage amplifier has a measured noise figure of 3.5 dB, with an associated small signal gain of 21 dB at 94 GHz while the image-rejection mixer has a measured conversion loss of 11 dB with +10 dBm LO drive at 94.15 GHz. Measured results of the complete image-rejection downconverter including the hybrid IF 90° coupler and a 10 dB gain amplifier show a conversion gain of more than 18 dB and a noise figure of 4.6 dB at 94.45 GHz     

60-GHz monolithic down- and up-converters utilizing asource-injection concept

This paper deals with the design considerations, fabrication process, and performance of coplanar waveguide (CPW) heterojunction FET (HJFET) down- and up-converter monolithic microwave integrated circuits (MMIC's) for V-band wireless system applications. To realize a mixer featuring a simple structure with inherently isolated ports, and yet permitting independent port matching and low local oscillator (LO) power operation, a “source-injection” concept is utilized by treating the HJFET as a three-port device in which the LO signal is injected through the source terminal, the RF (or IF) signal through the gate terminal, and the IF (or RF) signal is extracted from the drain terminal. The down-converter chip incorporates an image-rejection filter and a source-injection mixer. The up-converter chip incorporates a source-injection mixer and an output RF filter. With an LO power and frequency of 7 dBm and 60.4 GHz, both converters can operate at any IF frequency within 0.5-2 GHz, with a corresponding conversion gain within -7 to -12 dB, primarily dominated by the related filter's insertion loss. Chip size is 3.3 mm×2 mm for the down-converter, and 3.5 mm×1.8 mm for the up-converter     

A 1.2 mW RDS receiver for portable applications

A 0.9 V 1.2 mA fully integrated radio data system (RDS) receiver for the 88-108 MHz FM broadcasting band is presented. Requiring only a few external components (matching network, VCO inductors, loop filter components), the receiver, which has been integrated in a standard digital 0.18 /spl mu/m CMOS technology, achieves a noise figure of 5 dB and a sensitivity of -86dBm. The circuit can be configured and the RDS data retrieved via an I/sup 2/C interface so that it can very simply be used as a peripheral in any portable application. A 250 kHz low-IF architecture has been devised to minimize the power dissipation of the baseband filters and FM demodulator. The frequency synthesizer consumes 250 /spl mu/A, the RF front-end 450 /spl mu/A while providing 40 dB of gain, the baseband filter and limiters 100 /spl mu/A, and the FM and BPSK analog demodulators 300 /spl mu/A. The chip area is 3.6 mm/sup 2/.     

A micropower CMOS, direct-conversion, VLF receiver chip formagnetic-field wireless applications

A micropower CMOS, direct-conversion very low frequency (VLF) receiver is described for receiving low-level magnetic fields from resonant sensors. The single-chip, phase locked loop (PLL)-synthesized receiver covers a frequency range of 10-82 kHz and provides both analog and 9-b digital baseband I and Q outputs. Digital I and Q outputs are accumulated in a companion digital chip which provides baseband signal processing. Emphasis is plated on the receiver micropower RF preamplifier which uses a lateral bipolar input device because of the significant increase in flicker noise illustrated for PMOS devices in weak inversion. Lateral bipolar transistors are also utilized in the mixer and IF stages for low flicker noise and low dc offsets. Special attention is given to isolating the internal local oscillator signals from the low-level RF input (0.3 μV noise floor in 300 Hz BW), and local oscillator feedthrough is indiscernible in the RF preamplifier output noise spectrum. The 100% duty-cycle receiver, intended for miniature, battery-operated wireless applications, operates approximately four months at 80 μA from a 6-V, 220-mA-hr battery     

A 900-MHz dual-conversion low-IF GSM receiver in 0.35-μm CMOS

A low-power fully integrated GSM receiver is developed in 0.35-μm CMOS. This receiver uses dual conversion with a low IF of 140 kHz. This arrangement lessens the impact of the flicker noise. The first IF of 190 MHz best tolerates blocking signals. The receiver includes all of the circuits for analog channel selection, image rejection, and more than 100-dB controllable gain. The receiver alone consumes 22 mA from a 2.5-V supply, to give a noise figure of 5 dB, and input IP3 of -16 dBm. A single frequency synthesizer generates both LO frequencies. The integrated VCO with on-chip resonator and buffers consume another 8 mA, and meets GSM phase-noise specifications     

GaAs MMIC demodulator using a distributed mixing principle forhigh-sensitivity 5 Gbit/s CPFSK receiver

A distributed GaAs MMIC mixer is designed to be employed in an integrated demodulator for a coherent optical CPFSK receiver with an IF bandwidth of 7-14 GHz and a baseband bandwidth of 4 GHz. At 5 Gbit/s a receiver sensitivity of -39.0 dBm is obtained using the demodulator     

Low-power fully integrated and tunable CMOS RF wireless receiver for ISM band consumer applications

A 0.25-/spl mu/m single-chip CMOS single-conversion tunable low intermediate frequency (IF) receiver operated in the 902-928-MHz industrial, scientific, and medical band is proposed. A new 10.7-MHz IF section that contains a limiting amplifier and a frequency modulated/frequency-shift-key demodulator is designed. The frequency to voltage conversion gain of the demodulator is 15 mV/kHz and the dynamic range of the limiting amplifier is around 80 dB. The sensitivity of the IF section including the demodulator and limiting amplifier is -72 dBm. With on-chip tunable components in the low-power low-noise amplifier (LNA) and LC-tank voltage-controlled oscillator circuit, the receiver measures an RF gain of 15 dB at 915 MHz, a sensitivity of -80 dBm at 0.1% bit-error rate, an input referred third-order intercept point of -9 dBm, and a noise figure of 5 dB with a current consumption of 33 mA and a 2450 /spl mu/m/spl times/ 2450 /spl mu/m chip area.     

A superheterodyne receiver front-end with on-chip automatically Q-tuned notch filters

A superheterodyne receiver front-end with on-chip automatically Q-tuned notch filters is proposed. The front-end includes a differential LNA and a Gilbert down-converter, where each block is coupled with an on-chip image-rejection notch filter to get high image-rejection ratio. Each notch filter is formed by one on-chip LC network and one negative-resistance cross-coupled pair to compensate for the loss of the LC network. The current through the cross-coupled pairs is automatically adjusted by an automatic Q tuning circuit so that the loss of the notch filter is perfectly compensated to achieve a deepest notch. The automatic Q tuning circuit is an analog?Cdigital mixed signal circuit, and successive approximation register algorithm is used to search for the optimum current value. The superheterodyne receiver front-end has been implemented in 0.18???m CMOS. Experimental results show that the circuit could achieve an image rejection ratio of 75?dB with 105?MHz IF Frequency. The LNA draws 5.86?mA current, and the down-converter draws 1.27?mA current while two image-rejection filters and the master VCO totally draw 363???A current, all from a 1.8?V power supply.     

Optimum system parameters for multigigabit CPFSK optical heterodynedetection systems

To obtain a multigigabit continuous-phase frequency-shift-keying (CPFSK) system with a high receiver sensitivity, we theoretically and experimentally investigated the optimum modulation index parameter and IF center frequency, considering the modulation and demodulation baseband widths and the IF bandwidth. In a 6-Gb/s CPFSK experiment, we achieved a receiver sensitivity of -41.6 dBm, or 89 photons/bit. To use the 4- to 13-GHz IF band efficiently, we set the IF center frequency f _IF to 8.7 GHz, or 1.45 times the bit rate. To compensate for the insufficient 5-GHz FM-modulation bandwidth in the transmitter, we set the modulation index parameter β to 1.38, that is, a modulation index m of 0.8     

A low-voltage 5.1-5.8-GHz image-reject receiver with wide dynamicrange

A monolithic 5-6-GHz band receiver, consisting of a differential preamplifier, dual doubly balanced mixers, cascaded injection-locked frequency doublers, and a quadrature local oscillator generator and prescaler, realizes over 45 dB of image-rejection in a mature 25-GHz silicon bipolar technology. The measured single sideband (50 Ω) noise figure is 5.1 dB with an IIP3 of -4.5 dBm and 17-dB conversion gain at 5.3 GHz. The 1.9×1.2 mm² IC is packaged in a standard 32-pin ceramic quad flatpack and consumes less than 50 mW from a 2.2-V supply     

A 1.9-GHz silicon receiver with monolithic image filtering

A 1.9-GHz fully monolithic silicon superheterodyne receiver front-end is presented; it consists of a low noise amplifier (LNA), a tunable image reject filter, and a Gilbert cell mixer integrated in one die. The receiver was designed to operate with a 1.9-GHz RF and a 2.2-GHz local oscillator (LO) for a 300-MHz IF. Two chip versions were fabricated on two different fabrication runs using a 0.5-μm bipolar technology with 25 GHz transit frequency (f_T). Measured performance for the receiver front-end version 1, packaged and without input matching, was: conversion gain 33.5 dB, noise figure 4.9 dB, input IP3 -28 dBm, image rejection 53 dB (tuned to reject a 2.5-GHz image frequency), and 15.9 mA current consumption at +3 V. The image rejection was tunable from 2.4-2.63 GHz by means of an on-chip varactor. Version 2 had increased mixer degeneration for improved linearity. Its measured performance for the packaged receiver with its input matched to 50 Ω was: conversion gain 24 dB, noise figure 4.8 dB, input IP3 -19 dBm, and 65 dB image rejection for a 2.5-GHz image with an image tuning range from 2.34-2.55 GHz     

A 60-GHz Phased Array Receiver Front-End in 0.13-$mu {hbox{m}}$ CMOS Technology

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, ag_m-boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g_m-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm². The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.     

An optical FSK heterodyne dual filter detection system for takingadvantage of DFB LD applications

An optimum system configuration for an optical frequency-shift keying (FSK) heterodyne dual-filter detection system with distributed feedback laser diodes (DFB LDs) is investigated, taking into consideration LD phase noise influence. Experimental and theoretical examination show that an IF filter bandwidth greater than 10 times the beat spectral linewidth is necessary to avoid LD phase noise influence. A 301-km long-span transmission experiment has been successfully carried out with an optimum configuration for 34 Mb/s. High receiver sensitivity, -61.8 dBm with more than 10 dB improvement over the direct detection system, has also been achieved. Experimental results at higher bit rates of 140, 200, and 280 Mb/s indicate that a modulation index greater than two is desirable to avoid cross talk between mark and space signals. With sufficient frequency deviations, high receiver sensitivities of -54.7 dBm (140 Mb/s) and -52.5 dBm (200 Mb/s) have been achieved. These represent 9.6- and 9-dB sensitivity improvement, respectively, over direct detection systems. A guide for FSK dual-filter detection system design is derived from the experimental and theoretical results. Potential application regions for a dual-filter detection system with DFB LDs are determined