A Code Set for a Robust 8.25 Mb/s Data Rate for IEEE 802.11b WLANs

In this paper, a code set for an 8.25-Mb/s data rate is proposed for the Institute of Electrical and Electronics Engineers 802.11b system, which can act as a better fallback option than a 5.5-Mb/s data rate when an 11-Mb/s data rate is not sustainable in a large delay-spread channel environment. We present a systematic procedure for the design of the code set. The proposed code set works at significantly higher path loss when compared to an 11-Mb/s data rate in moderate to large delay-spread channel environment. We also discuss the resource requirement for including the proposed data rate in the existing 802.11b transceiver and note that the additional hardware is minimal. Since the current WIreless FIdelity chipsets are enabled with the 802.11g option, we investigated the performance of the proposed data rate and the 6and 9-Mb/s data rates provided by 802.11g, and the results show that the 8.25-Mb/s data rate is a reliable fallback option compared to the 9-Mb/s rate when the 11-Mb/s data rate is not sustainable. The 8.25-Mb/s data rate is shown to work at 1.7 dB higher path loss when compared to the 9-Mb/s rate in a frequently occurring moderate delay-spread channel     

Detection of buried targets via active selection of labeled data: application to sensing subsurface UXO

When sensing subsurface targets, such as landmines and unexploded ordnance (UXO), the target signatures are typically a strong function of environmental and historical circumstances. Consequently, it is difficult to constitute a universal training set for design of detection or classification algorithms. In this paper, we develop an efficient procedure by which information-theoretic concepts are used to design the basis functions and training set, directly from the site-specific measured data. Specifically, assume that measured data (e.g., induction and/or magnetometer) are available from a given site, unlabeled in the sense that it is not known a priori whether a given signature is associated with a target or clutter. For N signatures, the data may be expressed as {x/sub i/,y/sub i/}/sub i=1,N/, where x/sub i/ is the measured data for buried object i, and y/sub i/ is the associated unknown binary label (target/nontarget). Let the N x/sub i/ define the set X. The algorithm works in four steps: 1) the Fisher information matrix is used to select a set of basis functions for the kernel-based algorithm, this step defining a set of n signatures B/sub n//spl sube/X that are most informative in characterizing the signature distribution of the site; 2) the Fisher information matrix is used again to define a small subset X/sub s//spl sube/X, composed of those x/sub i/ for which knowledge of the associated labels y/sub i/ would be most informative in defining the weights for the basis functions in B/sub n/; 3) the buried objects associated with the signatures in X/sub s/ are excavated, yielding the associated labels y/sub i/, represented by the set Y/sub s/; and 4) using B/sub n/,X/sub s/, and Y/sub s/, a kernel-based classifier is designed for use in classifying all remaining buried objects. This framework is discussed in detail, with example results presented for an actual buried-UXO site.     

Multimedia extensions for a 550-MHz RISC microprocessor

This paper describes circuits used to implement the motion video instructions (MVI) in the 550-MHz Alpha 21 164PC Microprocessor. The chip is fabricated in a 0.35-μm CMOS process and is the first implementation of the MVI instruction set in the Alpha architecture. The MVI instruction set, coupled with the high performance of the 550-MHz processor, delivers 30 frames/s digital video disk (DVD) playback with stereo-quality audio, enables video teleconferencing at 30 frames/s, and significantly improves the performance of MPEG encode algorithms     

Very low rate speech coding using temporal decomposition

A method for encoding the spectral characteristics of speech, at rates below 180 bit/s, using hierarchical temporal decomposition (HTD) is proposed. A set of the log-area-ratio (LAR) parameters, extracted from a given block of speech, are approximated through Gaussian interpolation between the most-steady frames detected by the HTD. This results in a smaller set of parameters which are encoded using vector quantisation. It is shown that the same spectral distortion is obtained with the new coder at a rate of 180 bit/s as that using a scalar quantisation, TD-based coder, at 600 bit/s     

Multi-Modal Speech Recognition Using Optical-Flow Analysis for Lip Images

This paper proposes a multi-modal speech recognition method using optical-flow analysis for lip images. Optical flow is defined as the distribution of apparent velocities in the movement of brightness patterns in an image. Since the optical flow is computed without extracting the speaker's lip contours and location, robust visual features can be obtained for lip movements. Our method calculates two kinds of visual feature sets in each frame. The first feature set consists of variances of vertical and horizontal components of optical-flow vectors. These are useful for estimating silence/pause periods in noisy conditions since they represent movement of the speaker's mouth. The second feature set consists of maximum and minimum values of integral of the optical flow. These are expected to be more effective than the first set since this feature set has not only silence/pause information but also open/close status of the speaker's mouth. Each of the feature sets is combined with an acoustic feature set in the framework of HMM-based recognition. Triphone HMMs are trained using the combined parameter sets extracted from clean speech data. Noise-corrupted speech recognition experiments have been carried out using audio-visual data from 11 male speakers uttering connected digits. The following improvements of digit accuracy over the audio-only recognition scheme have been achieved when the visual information was used only for silence HMM: 4% at SNR = 5 dB and 13% at SNR = 10 dB using the integral information of optical flow as the visual feature set.     

An analog front-end chip set employing an electro-optical mixeddesign on SPICE for 5-Gb/s/ch parallel optical interconnection

A chip set composed of a laser-diode driver (LDD) and an optical receiver (RCV), which incorporates a full 2D (reshape, regenerate) function, has been developed by using silicon bipolar technology for a four-channel 5-Gb/s parallel optical transceiver. An electro-optical mixed design on SPICE of the LDD and the LD is accomplished by describing the rate equations of the LD as an electrical circuit. This design accommodates easy connectivity of the LDD chip to the LD in the optical transmitter module without the need for adjustment of the optical waveform. A pseudobalanced transimpedance amplifier (TIA) and feedforward automatic decision threshold control (ATC) in the RCV minimize the number of off-chip bypass capacitors, eliminate the need for any off-chip coupling capacitors, and keep crosstalk less than -50 dB and low cutoff frequency less than 80 kHz. A prototype parallel optical transmitter module and a prototype receiver module, based on the chip set, demonstrated asynchronous four-channel 5-Gb/s operation. The chip set has a throughput of 20 Gb/s with a power dissipation of 1.3 W at a 3.3-V supply     

A 3.5 in 230 Mbytes read-channel chip set for magneto-optical diskdrives

A read-channel chip set for rewritable 3.5 in 230 Mbytes magneto-optical disk drives (MOD) is presented. The front-end chip includes an automatic gain control (AGC) circuit, a programmable six-pole two-zero equiripple filter/equalizer, a DC restore circuit, and pulse detectors. The back-end contains a frequency synthesizer phase-locked loop (PLL) and a data separator PLL with 3:1 operating range to support a constant density recording with 8-24 Mb/s data rate (or code rate of 16 to 48 Mb/s) in (2, 7) run-length limited (RLL) encoding format. The architecture of the chip provides high degree of programmability through a serial microprocessor interface, fast switching (<1 μs) between sector mark and data detector modes, and four levels of power management in a 1.5 μm 4 GHz BiCMOS process. With a nominal power supply of 5 V, the chip set dissipates 600 mW during normal operation and 1 mW during sleep mode     

64 bit monolithic floating point processors

Describes a set of three processor chips capable of performing 32 and 64 bit floating point add/subtract, multiply, and divide operations. The chips can perform over one million scalar floating point operations per second, and over four million vector operations per second. The set is implemented in a four micron CMOS-on-sapphire process. Each chip has between 30000 and 60000 devices, and is about 250 mils on a side. Although asynchronous data paths are used within the chips, their interface to external system buses is synchronous with a maximum data bandwidth of over 70 Mbytes/s. The set has been designed for use in Hewlett-Packard computer and instrument systems.     

Properties and performance of the IEEE 802.11b complementary-code-key signal sets

We describe similarities and differences between complementary-code-key (CCK) modulation and modulation that is derived from biorthogonal signals, and we present performance results and other information that may be useful to those who have applications for CCK modulation that do not require IEEE 802.11b compliance. The properties and performance of the highrate IEEE CCK 802.11b modulation formats are investigated and compared with the properties and performance of alternative modulation formats that are based on biorthogonal signals. Several complementary properties are derived for the full-rate (11 Mb/s) CCK signal set, the half-rate (5.5 Mb/s) CCK signal set, a full-rate signal set obtained from biorthogonal signals, and a half-rate biorthogonal signal set. Each signal set is a complementary set, but each also has stronger complementary properties. We evaluate the performance of IEEE 802.11b standard CCK modulation, CCK with certain modifications that depart from the IEEE standard, and modulation that is derived from biorthogonal signals. Performance comparisons are presented for additive white Gaussian noise (AWGN) channels and for channels with specular multipath. In particular, for AWGN channels, we provide an accurate analytical approximation for the frame error probability for full-rate CCK modulation.     

Digital system for 1/f fluctuation-speed control of asmall-fan motor

To produce a comfortable breeze similar to a natural one, a digital open-loop control system was utilized to control the speed of a small fan motor with 1/f fluctuation. The system was modeled as a first-order lag element with a time constant of 1.1 s. The output was controlled by commands and produced 1/f fluctuations, even though it was an open-loop system when the holding time of the data for 1/f fluctuation was set at more than 2 s     

Design and implementation of an all-CMOS 802.11a wireless LAN chipset

The tremendous growth in wireless LANs has generated interest in technologies that provide higher data rates and greater system capacities. The IEEE 802.11a standard, based on coded OFDM modulation, provides nearly five times the data rate and at least 20 times the overall system capacity compared to the incumbent 802.11b wireless LAN systems. This article describes the design challenges and circuit implementation of a two-chip set that forms a complete 802.11a solution in 0.25 /spl mu/m CMOS technology. Wherever possible, sophisticated digital signal processing techniques are used to compensate for possible analog impairments associated with integrating RF circuitry in a CMOS technology. The analog portion of the chip set implements a 5 GHz transceiver comprising all the necessary RF and analog circuits of the 802.11a standard integrated on a single chip. Some features of this IC include 22 dBm peak transmitted power, 8 dB overall receive-chain noise figure, and -112 dBc/Hz synthesizer phase noise at 1 MHz frequency offset. The digital portion of the chip set, the baseband and MAC processor, contains dual ADCs/DACs and all the digital circuits for synchronization, detection, and 802.11 MAC layer data processing. This IC delivers up to 54 Mb/s in a 20 MHz channel according to the 802.11a standard, and includes proprietary modes supporting up to 108 Mb/s in a 40 MHz channel.     

准线性光传输系统色散管理方案的研究

推导了准线性光传输系统中受信道内四波混频、信道内交叉相位调制等信道内非线性效应影响的非线性传输方程,搭建了可构成多种色散管理方案的仿真传输链路,对10Gb/s、40Gb/s、100Gb/s、160Gb/s等四种不同速率的准线性光传输系统的色散管理方案进行了数值分析,分析了幅度抖动与定时抖动的关系,幅度抖动与系统Q值的关系,以及脉冲初始功率与系统Q值的关系。首次得到了单信道准线性光传输系统的最优色散管理方案与系统传输速率相关,并且随着系统传输速率的增加,前色散补偿部分的比例应逐步减少、后色散补偿部分的比例应逐渐增加并可量化的结论。     

Subjective Evaluation of Several Efficient Speech Coders

The voice quality of several 9.6 - 32 kbit/s coders is determined with an extensive set of subjective listening tests. Single encodings of μ255 PCM, adaptive differential PCM (ADPCM), subband coding (SBC), vocoder-driven adaptive transform coding (ATC), adaptive predictive coding (APC), and time domain harmonic scaling combined with SBC are compared in an idealized situation, that is, no added impairments. It is shown that single encodings of modest complexity 32 kbit/s coders such as ADPCM and SBC and more complex 24 kbit/s coders such as vocoder-driven ATC and APC offer quality nearly equivalent to 64 kbit/s μ255 PCM. However, these conclusions are drawn in the absence of a realistic telephone network where tandem encodings, delay limitations, and nonvoice signals exist. Tandem encodings of 64 kbit/s μ255 PCM, 32 kbit/s ADPCM, 16 kbit/s SBC, and 16 kbit/s APC are also evaluated. These 32 kbit/s and 16 kbit/s coders offer degraded tandem performance as compared to 64 kbit/s PCM, with the exception of synchronous tandeming of 32 kbit/s ADPCM with 64 kbit/s PCM where several encodings are subjectively equivalent to a single encoding of 32 kbit/s ADPCM.     

GaAs MESFET characterization using least squares approximation byrational functions

The authors propose a method of characterizing active devices such as the FET by describing S-parameters with a set of rational functions of angular frequency. The set of rational functions is uniquely determined by only 27 coefficients, while the conventional method using tabulated S-parameters requires eight times the number of sampling points (a typical case might require 404 data points in floating-point notation). This drastically reduces the database size required to give adequate information for circuit design. A method for determining the equivalent circuit is described. Since the equivalent circuit is determined from the set of rational functions, no additional measurements are needed to determine extrinsic elements. In conventional methods, selection of initial values affects the final results. In the present method, reliable initial values are extracted from the rational functions' coefficients. The calculated S-parameters of three GaAs MESFETs having different gate widths agree closely with those measured by wafer-probe     

Vers les 20 kbit/s en transmission décamétrique ionosphérique : une application du traitement d’antenne sur des capteurs colocalisés

This paper presents an operational system of digital transmission within the h.f. frequency range, aiming at a significant increase of the data transfer rate compared with the current standard (4800 bit/s). Therefore, an array processing algorithm performs with a set of collocated sensors, the spatial responses of which are different one from each other. The dependence of the incoming polarization relatively to the direction of arrival induces a significant decorrelation of the received signals though no geometrical phase exists. Signal processing techniques run at the output of the spatial filter resorting for the synchronisation and the filtering (lms algorithm) to classical and well-tested techniques involving training sequences. An experimental radio link with a 250 km range has been set up to test the sensibility of the performances in reception regarding the choice of waveforms. The operational results reach the expected goal as the data transfer rate increases up to 20 kbit/s in a bandwidth of 6 kHz.     

ADSL网络体系结构

ADSL是DSL的一种非对称版本，是目前一种重要的宽带接入方式，ADSL能够向终端用户提供8Mbit/s的下行传输速率和1Mbit/s的上行传输速率，比传统的28．8kbit/s模拟调制解调器快将近200倍。文中讨论了一组能够支持基于PPP／ATM／ADSL接入网体系结构的核心网体系结构，分析了几种不同组网方式的特征与协议栈模型。     

Conflict detection and resolution in two-dimensional prefix router tables

We show that determining the minimum number of resolve filters that need to be added to a set of two-dimensional (2-D) prefix filters so that the filter set can implement a given policy using the first-matching-rule-in-table tie breaker is NP-hard. Additionally, we develop a fast O(nlogn+s) time, where n is the number of filters and s is the number of conflicts, plane-sweep algorithm to detect and report all pairs of conflicting 2-D prefix filters. The space complexity of our algorithm is O(n). On our test set of 15 2-D filter sets, our algorithm runs between 4 and 17 times as fast as the 2-D trie algorithm of A. Hari et al. (2000) and uses between 1/4th and 1/8th the memory used by the algorithm of Hari et al. On the same test set, our algorithm is between 4 and 27 times as fast as the bit-vector algorithm of Baboescu and Varghese (2002) and uses between 1/205 and 1/6 as much memory. We introduce the notion of an essential resolve filter and develop an efficient algorithm to determine the essential resolve filters of a prefix filter set.     

A 1024-channel fast tunable delay line for ultrafast all-optical TDM networks

Based on a passive k-stage feed-forward delay line structure, this letter presents a novel scheme which allows fast tuning among as many as 2/sup k//spl times/2/sup k/ ultrafast time-division multiplexed (TDM) channels in all-optical networks. At a lower speed, a simple selection rule is applied at the input and output of the structure to set the state of the delay. In the experimental demonstration, the delay line can be tuned to any of the 1024 50-Mb/s channels in a 50-Gb/s all-optical TDM network with a five-stage structure and two E/O modulators. The average reconfiguration time is about 20 ns.     

A 20-Gb/s CMOS multichannel transmitter and receiver chip set forultra-high-resolution digital displays

A multichannel transmitter (TX) and receiver (RX) chip set operating at 20 Gb/s (5 Gb/s×4 ch) has been developed by using 0.25-μm CMOS technology. To achieve multichannel data transmission and high-speed operation, the chip set features: (1) circuits for compensating the phase difference between multiple RX chips, which is due to data skew resulting from different lengths of transmission cables, and for compensating the frequency difference between the system clocks of the TX and RX chips; (2) a self-alignment phase detector with parallel output for a high-speed data-recovery circuit; and (3) a fully pipelined 8B10B encoder. At a 2.5-V power supply, the power consumption of the TX chip during 5-Gb/s operation is 500 mW and that of the RX chip is 750 mW. Four of these TX/RX chip sets can provide an aggregate bandwidth of 20 Gb/s