Correlation between infrared transmission spectra and the interface trap density of SiO2 films

This work is an attempt to estimate the electrical properties of SiO₂ thin films by recording and analyzing their infrared transmission spectra. In order to study a big variety of films having different infrared and electrical properties, we studied SiO₂ films prepared by low pressure chemical vapor deposition (LPCVD) from SiH₄ + O₂ mixtures at 425 °C and annealed at 750 °C and 950 °C for 30 min. In addition thermally grown gate quality SiO₂ films of similar thickness were studied in order to compare their infrared and electrical properties with the LPCVD oxides. It was found that all studied SiO₂ films have two groups of Si–O–Si bridges. The first group corresponds to bridges located in the bulk of the film and far away from the interfaces, the grain boundaries and defects and the second group corresponds to all other bridges located near the interfaces, the grain boundaries and defects. The relative population of the bulk over the boundary bridges was found equal to 0.60 for the LPCVD film after deposition and increased to 4.0 for the LPCVD films after annealing at 950 °C. Thermally grown SiO₂ films at 950 °C were found to have a relative population of Si–O–Si bridges equal to 3.9. The interface trap density of the LPCVD film after deposition was found equal to 5.47 × 10¹² eV⁻¹ cm⁻² and decreases to 6.50 × 10¹⁰ eV⁻¹ cm⁻² after annealing at 950 °C for 30 min. The interface trap density of the thermally grown film was found equal to 1.27 × 10¹¹ eV⁻¹ cm⁻² showing that films with similar Si–O–Si bridge populations calculated from the FTIR analysis have similar interface trap densities.     

Electrical characterization of metal-oxide-high-k dielectric-oxide-semiconductor (MOHOS) structures for memory applications

Conventional SONOS (polysilicon-oxide-nitride-oxide-silicon) non-volatile memory devices use silicon nitride as the charge storage layer. In this work, metal-oxide-high-k dielectric-oxide-silicon (MOHOS) structures are fabricated using HfO₂ and Dy₂O₃ high-k dielectrics as the charge storage layer. The Al/SiO₂/Dy₂O₃/SiO₂/Si capacitors have a C–V memory window of 1.88 V and a leakage current density of 10⁻⁸ A/cm². This leakage current is lower than those of Al/SiO₂/HfO₂/SiO₂/Si capacitors and other similar capacitors reported in the literature. A minimum detection window of 0.5 V for MOHOS capacitors can be maintained up to 2 × 10⁸ s using as-deposited Dy₂O₃. The better performance of the Al/SiO₂/Dy₂O₃/SiO₂/Si structure over Al/SiO₂/HfO₂/SiO₂/Si is attributed to the larger conduction band offset at the Dy₂O₃/SiO₂ interface (2.3 eV) versus 1.6 eV at the HfO₂/SiO₂ interface.     

Performance study of n-MOS natural transistor fabricated by low thermal budget process

Natural n-MOS transistor and MOS capacitor test structures have been fabricated by the low temperature process design for better control on device dimensions. Si-SiO₂ interface properties and performance of LPCVD gorwn polysilicon gate natural transistor has been studied through MOS C-V analysis and physical-electrical modeling. Transistor behavior at cryogenic temperatures has also been analysed through MOS C-V characteristics and one dimensional transport equations.     

Charge trapping and interface states in hydrogen annealed HfO2–Si structures

Metal–oxide–semiconductor (MOS) capacitors based on HfO₂ gate stacks with Al and TiN gates are compared to study the effect of the gate electrode material to the properties of insulator–semiconductor interface. The structures under study were shown to contain interface trap densities of around 2 × 10¹¹ cm⁻² eV⁻¹ for Al gate and up to 5.5 × 10¹² cm⁻² eV⁻¹ for TiN gate. The peak in the surface state distribution was found at 0.19 eV above the valence band edge for Al electrode. The respective capture cross-section is 6 × 10⁻¹⁷ cm² at 200 K.The charge injection experiments have revealed the presence of hole traps inside the dielectric layer. The Al-gate structure contains traps with effective capture cross-section of 1 × 10⁻²⁰ cm², and there are two types of traps in the TiN-gate structure with cross-sections of 3.5 × 10⁻¹⁹ and 1 × 10⁻²⁰ cm². Trap concentration in the structure with Al electrode was considerably lower than in the structure with TiN electrode.     

Silicon dioxide deposited by ECR-PECVD for low-temperature Si devices processing

Silicon dioxide films have been deposited at temperatures less than 270 °C in an electron cyclotron resonance (ECR) plasma reactor from a gas phase combination of O₂, SiH₄ and He. The physical characterization of the material was carried out through pinhole density analysis as a function of substrate temperature for different μ-wave power (E_w). Higher E_w at room deposition temperature (RT) shows low defects densities (<7 pinhole/mm²) ensuring low-temperatures process integration on large area. From FTIR analysis and Thermal Desorption Spectroscopy we also evaluated very low hydrogen content if compared to conventional rf-PECVD SiO₂ deposited at 350 °C. Electrical properties have been measured in MOS devices, depositing SiO₂ at RT. No significant charge injection up to fields 6–7 MV/cm and average breakdown electric field >10 MV/cm are observed from ramps I–V. Moreover, from high frequency and quasi-static C–V characteristics we studied interface quality as function of annealing time and annealing temperature in N₂. We found that even for low annealing temperature (200 °C) is possible to reduce considerably the interface state density down to 5 × 10¹¹ cm⁻² eV⁻¹. These results show that a complete low-temperatures process can be achieved for the integration of SiO₂ as gate insulator in polysilicon TFTs on plastic substrates.     

Investigation of strontium tantalate thin films for high-k gate dielectric applications

Strontium tantalate (STO) films were grown by liquid-delivery (LD) metalorganic chemical vapor deposition (MOCVD) using Sr[Ta(OEt)₅(OC₂H₄OMe)]₂ as precursor. The deposition of the films was investigated in dependence on process conditions, such as substrate temperature, pressure, and concentration of the precursor. The growth rate varied from 4 to 300 nm/h and the highest rates were observed at the higher process temperature, pressure, and concentration of the precursor. The films were annealed at temperatures ranging from 600 to 1000 °C. Transmission electron microscopy (TEM), X-ray diffraction (XRD), and ellipsometry indicated that the as-deposited and the annealed films were uniform and amorphous and a thin (>2 nm) SiO₂ interlayer was found. Crystallization took place at temperatures of about 1000 °C. Annealing at moderate temperatures was found to improve the electrical characteristics despite different film thickness (effective dielectric constant up to 40, the leakage current up to 6×10⁻⁸ A/cm², and lowest midgap density value of 8×10¹⁰ eV⁻¹ cm⁻²) and did not change the uniformity of the STO films, while annealing at higher temperatures (1000 °C) created voids in the film and enhanced the SiO₂ interlayer thickness, which made the electrical properties worse. Thus, annealing temperatures of about 800 °C resulted in an optimum of the electrical properties of the STO films for gate dielectric applications.     

Co gamma irradiation effects on electrical characteristics of Al/Y2O3/n-Si/Al capacitors

Al/Y₂O₃/n-Si/Al capacitors were irradiated by using a ⁶⁰Co gamma ray source and a maximum dose up to 8.4 kGy. The effect of an annealing treatment performed at 600 or 900 °C on the yttrium oxide (Y₂O₃) films was investigated by XRD and Raman spectroscopy. High-frequency capacitance-voltage (C-V) and conductance-voltage (G-V) measurements as well as quasi-static measurements of the MOS structures were analysed. The annealing improves the crystalline state of the Y₂O₃ thin film material and decreases the values of the flat-band voltage and of the interface trap level density indicating an improvement of the electrical properties of the interface thin film-substrate. But at this interface, the formation of an yttrium-silicate layer was also evidenced. After gamma irradiation, the values of the flat-band voltage and of the interface trap level density related to the Al/Y₂O₃/n-Si/Al structure increase and especially for the structure made with the materials annealed at 900 °C for 1 h. In that case, the structure is very sensitive to a gamma irradiation dose up to 8.4 kGy.     

Influence of laser recrystallization and hydrogen annealing on electrical characteristics of polysilicon

 Asenic ions are implanted with doses of 5×10~(11)—5×10~(15)/cm~2 into LPCVD polysilicon films on SiO_2 isolating substrate.The polysilicon films have been recrystallized with CW Ar~+ laser before implantation.Electrical measurements show that the resistivity is lowered and the mobility is increased significantly at low doping concentration(～10~(17)As~+/cm~3).Plasma hydrogen annealing is performed on laser-recrystallized samples.The electrical characteristics of plasma hydrogen annealed samples are close to that of single crystalline silicon.It is found that the resistivity decreases from 1.2 Ω.cm to 0.45 Ω.cm,the mobility rises from 62 cm~2/V.s to 271 cm~2/V.s,the electrical activation energy reduces from 0.03 eV to -0.007 eV and the trapping state density at the grain boundary drops from 3.7×10~(11)/cm~2 to 1.7×10~(11)/cm~2.Based on the existing theoretical models for conduction in polysilicon, a new formula for large grain polysilicon has been proposed,with the help of which,a good agreement between theory and experimental results is achieved within the doping concentration range from 10~(16)/cm~3 to 10~(20)/cm~3.     

Characteristics of RF reactive sputter-deposited Pt/SiO2/n-InGaN MOS Schottky diodes

All RF sputtering-deposited Pt/SiO₂/n-type indium gallium nitride (n-InGaN) metal–oxide–semiconductor (MOS) diodes were investigated before and after annealing at 400 °C. By scanning electron microscopy (SEM), the thickness of Pt, SiO_2, n-InGaN layer was measured to be ~250, 70, and 800 nm, respectively. AFM results also show that the grains become a little bigger after annealing, the surface topography of the as-deposited film was smoother with the rms roughness of 1.67 nm and had the slight increase of 1.92 nm for annealed sample. Electrical properties of MOS diodes have been determined by using the current–voltage (I–V) and capacitance–voltage (C–V) measurements. The results showed that Schottky barrier height (SBH) increased slightly to 0.69 eV (I–V) and 0.82 eV (C–V) after annealing at 400 °C for 15 min in N₂ ambient, compared to that of 0.67 eV (I–V) and 0.79 eV (C–V) for the as-deposited sample. There was the considerable improvement in the leakage current, dropped from 6.5×10⁻⁷ A for the as-deposited to 1.4×10⁻⁷ A for the 400 °C-annealed one. The annealed MOS Schottky diode had shown the higher SBH, lower leakage current, smaller ideality factor (n), and denser microstructure. In addition to the SBH, n, and series resistance (R_s) determined by Cheungs׳ and Norde methods, other parameters for MOS diodes tested at room temperature were also calculated by C–V measurement.     

Research of SiO2/InP structure prepared by photo-CVD

The SiO₂ film as an insulator in InP MOS structure was grown by mercury-sensitized photo induced chemical-vapor deposition (photo-CVD) utilizing gaseous mixture of monosilane (SiH₄) and nitrous oxide (N₄O) under 253.7 nm ultraviolet light irradiation. The PHOTOX SiO₂ film (i.e., SiO₂ film prepared by photo-CVD system) deposited at 250° C has a refractive index of 1.46 and breakdown field strength of 7.0 MV/cm. The 1 MHz capacitance-voltage characteristics of the InP MOS diode was measured to study the interface state densities. The minimum value is 1.2 × 10¹¹ cm⁻²eV⁻¹ for the sample prepared at a substrate temperature of 250° C.     

Electron states at the (1 0 0)Ge/HfO2 Interface

The energy distribution of extended and localized electron states at the Ge/HfO₂ interface is determined by combining the internal photoemission of electrons and holes from Ge into the Hf oxide and AC capacitance/conductance measurements. The inferred offsets of the conduction and valence band at the interface, i.e., 2.0 ± 0.1 and 3.0 ± 0.1 eV, respectively, suggest the possibility to apply the deposited HfO₂ layer as a suitable insulator on Ge. The post-deposition annealing of the Ge/HfO₂ structures in oxygen results in 1 eV reduction of the valence band offset, which is attributed to the growth of a GeO₂ interlayer. However, this treatment enables one to substantially reduce the density of Ge/HfO₂ interface traps, approaching ≈1×10¹² cm⁻² eV⁻¹ near the Ge midgap.     

Electrical properties of oxidized polycrystalline silicon as a gate insulator for n-type 4H-SiC MOS devices

MOS capacitors were produced on n-type 4H-SiC using oxidized polycrystalline silicon (polyoxide). The polyoxide samples grown by dry oxidation without an anneal had a high interface state density (D_it) of 1.8 × 10¹² cm⁻² eV⁻¹ and the polyoxide samples grown by wet oxidation had a lower D_it of 1.2 × 10¹² cm⁻² eV⁻¹ (both at 0.5 eV below the conduction band). After 1 h Ar annealing, the D_it of wet polyoxide was reduced significantly to 2.6 × 10¹¹ cm⁻² eV⁻¹ (at 0.5 eV below the conduction band). Dry polyoxide exhibits higher breakdown electric fields than wet polyoxide. The interface quality and breakdown characteristics of polyoxide are comparable to published results of low-temperature CVD deposited oxides.     

Electrical properties of silicon dioxide films fabricated at 700°C. II: Low pressure hydride deposition

We have investigated the effects of different annealing treatments on silicon dioxide films produced from the reaction of dichlorosilane and nitrous oxide at 700° C. The electrical quality of these LPCVD films was evaluated by measuring oxide charge and interface trap densities on metal oxide semiconductor (MOS) capacitors. These densities were measured before and after avalanche injection of electron currents into the oxide films. The results of these studies were as follows. (1) The LPCVD oxide films required a post deposition anneal at 1000° C to produce as-grown charge densities similar to those of a standarddry thermal oxide grown and annealed at 1000° C. (2) Post-injection charge densities of LPCVD films given a post deposition anneal at 1000°C were an order of magnitude greater than those of the standard dry thermal oxide. (3) Different annealing treatments produced a series of dominant electron trapping centers in the oxide bulk₁₇ with capture cross sections ranging from 10⁻¹⁴ cm² to 10⁻¹⁷ cm². (4) The electron traps in the LPCVD oxides films were similar to those previously observed in standardwet thermal oxides grown and annealed above 1000° C.     

Optical and electrical properties of epitaxial (Mg,Cd)xZn1−xO, ZnO, and ZnO:(Ga,Al) thin films on c-plane sapphire grown by pulsed laser deposition

A consistent set of epitaxial, n-type conducting ZnO thin films, nominally undoped, doped with Ga or Al, or alloyed with Mg or Cd, was grown by pulsed laser deposition (PLD) on single-crystalline c-plane sapphire (0 0 0 1) substrates, and characterized by Hall measurement, and UV/VIS optical transmission spectroscopy.The optical band gap of undoped ZnO films at nearly 3.28 eV was shifted by alloying with Mg up to 4.5 eV and by alloying with Cd down to 3.18 eV, dependent on the alloy composition. In addition, highly doped ZnO:Al films show a blue-shifted optical absorption edge due to filling of electronic states in the conduction band.The Hall transport data of the PLD (Mg,Zn,Cd)O:(Ga,Al) thin films span a carrier concentration range of six orders of magnitude from 3 × 10¹⁴ to 3 × 10²⁰ cm⁻³, which corresponds to a resistivity from 5 × 10⁻⁴ to 3 × 10³ Ω cm. Structurally optimized, nominally undoped ZnO films grown with ZnO nucleation and top layer reached an electron mobility of 155 cm²/V s (300 K), which is among the largest values reported for heteroepitaxial ZnO thin films so far.Finally, we succeeded in combining the low resistivity of ZnO:Ga and the band gap shift of MgZnO in MgZnO:Ga thin films. This results demonstrate the unique tunability of the optical and electrical properties of the ZnO-based wide-band gap material for future electronic devices.     

Interface traps effect on the charge transport mechanisms in metal oxide semiconductor structures based on silicon nanocrystals

The transport phenomena in Metal-Oxide-Semiconductor (MOS) structures having silicon nanocrystals (Si-NCs) inside the dielectric layer has been investigated by high frequency Capacitance-Voltage (C-V) method and the Deep-Level Transient Spectroscopy (DLTS). For the reference samples without Si-NCs, we observe a slow electron trap for a large temperature range, which is probably a response of a series electron traps having a very close energy levels. A clear series of electron traps are evidenced in DLTS spectrum for MOS samples with Si-NCs. Their activation energies are comprised between 0.28 eV and 0.45 eV. Moreover, we observe in this DLTS spectrum, a single peak that appears at low temperature which we attributed to Si-NCs response. In MOS structure without Si-NCs, the conduction mechanism is dominated by the thermionic fast emission/capture of charge carriers from the highly doped polysilicon layer to Si-substrate through interface trap-states. However, at low temperature, the tunneling of charge carriers from highly Poly-Si to Si-substrate trough the trapping/detrapping mechanism in the Si-NCs contributed to the conduction mechanism for MOS with Si-NCs. These results are helpful to understand the principle of charge transport of MOS structures having a Si-NCs in the SiO_x = 1.5 oxide matrix.     

Low-temperature conductance measurements of surface states in HfO2–Si structures with different gate materials

Metal-oxide-semiconductor capacitors based on HfO₂ gate stack with different metal and metal compound gates (Al, TiN, NiSi and NiAlN) are compared to study the effect of the gate electrode material on the trap density at the insulator–semiconductor interface.C–V and G–ω measurements were made in the frequency range from 1 kHz to 1 MHz in the temperature range 180–300 K. From the maximum of the plot G/ω vs. ln(ω) the density of interface states was calculated, and from its position on the frequency axis the trap cross-section was found. Reducing temperature makes it possible to decrease leakage current through the dielectric and to investigate the states located closer to the band edge.The structures under study were shown to contain significant interface trap densities located near the valence band edge (around 2×10¹¹ cm⁻²eV⁻¹ for Al and up to (3.5–5.5)×10¹² cm⁻² eV⁻¹ for other gate materials). The peak in the surface state distribution is situated at 0.18 eV above the valence band edge for Al electrode. The capture cross-section is 5.8×10⁻¹⁷ cm² at 200 K for Al–HfO₂–Si structure.     

Low temperature processed hafnium oxide: Structural and electrical properties

In this work hafnium oxide (HfO₂) was deposited by r.f. magnetron sputtering at room temperature and then annealed at 200 °C in forming gas (N₂+H₂) and oxygen atmospheres, respectively for 2, 5 and 10 h. After 2 h annealing in forming gas an improvement in the interface properties occurs with the associated flat band voltage changing from −2.23 to −1.28 V. This means a reduction in the oxide charge density from 1.33×10¹² to 7.62×10¹¹ cm⁻². After 5 h annealing only the dielectric constant improves due to densification of the film. Finally, after 10 h annealing we notice a degradation of the electrical film's properties, with the flat band voltage and fixed charge density being −2.96 V and 1.64×10¹² cm⁻², respectively. Besides that, the leakage current also increases due to crystallization. On the other hand, by depositing the films at 200 °C or annealing it in an oxidizing atmosphere no improvements are observed when comparing these data to the ones obtained by annealing the films in forming gas. Here the flat band voltage is more negative and the hysteresis on the C–V plot is larger than the one recorded on films annealed in forming gas, meaning a degradation of the interfacial properties.     

Hot carrier effect—model, mechanism and effects on C-V and I-V characteristics in MOS structures

The effects of hot carrier injection on C-V and I-V characteristics in MOS structures are discussed. The charge trapping and generation of interface states caused by the hot carrier effect lead to C-V characteristic curve distortion, flatband voltage shift and, under a constant voltage, SiO₂ leakage current shift with time. The mechanisms of these shifts are dealt with. The tⁿ physical models of shifts are put forward. The phenomenon observed in experiments is well explained.     

Influence of fluorine contamination on reliability of thin gate oxides

We analyze diffusion and segregation kinetics of fluorine atoms in poly-Si / SiO₂ / Si structures with gate oxides of 5 nm by means of secondary ion mass spectroscopy. Well defined doses of fluorine were introduced by ion implantation. Our results indicate fluorine segregation at interfaces to the gate oxide. This segregation is diffusion limited with an effective activation energy of 1.4 eV. The accumulation of fluorine influences the intrinsic reliability of thin oxides. The breakdown behavior was studied using constant voltage, constant current, and stepwise increasing constant current stress, respectively. Weibull plots before and after the heat treatments were analyzed. At low fluorine concentrations up to doses of 5 × 10¹⁵ cm⁻² fluorine segregation is beneficial, improving, for example the tails of the Weibull plots and slightly increasing the breakdown voltage. For fluorine doses higher than 1 × 10¹⁶ cm⁻², detrimental consequences were found, degrading the charge to breakdown values by about a factor of 5 after long - term thermal treatments.     

The correlation of γ-irradiation,particle size and their effects on physical properties of AgInSe2 nanostructure thin films

In this work the effect of γ-irradiation on the optical and electrical properties of near stoichiometric AgInSe₂ nanostructure thin films have been characterized. The XRD pattern of ingot AgInSe₂ powder prepared by solid state reaction showed tetragonal polycrystalline single-phase structure. The thin films of thickness 75 nm were prepared by inert gas condensation (IGC) technique at using constant Ar flow and substrate temperature of 300 K.Thin films were exposed to annealing process at 473 K for 2 h in vacuum of 10⁻² Torr. The amorphous and tetragonal nanocrystalline structures were detected for as-deposited and annealed films respectively by grazing incident in-plane X-ray diffraction (GIIXD) technique. The structure and average particle size of annealed irradiated films by different γ-doses from 0 to 4 Mrad were determined using high resolution transmission electron microscope (HRTEM). Optical transmission, reflection and absorption spectra were studied for both annealed unirradiated and irradiated films. Two optical transitions for each annealed unirradiated and film exposed to γ-irradiation doses from 0 to 4 Mrad were observed. The evaluated E_g1 due to 1^st transition have decreased from 1.52 to 1.44 eV and E_g2 due to 2^nd transition have decreased from 2.83 to 2.30 eV as the particle size increased from 7.3 to 9.5 nm by raising the irradiation dose up to 1 Mrad. The behavior of d.c. electrical conductivity with temperature that measured under vacuum was examined for all films under investigation. The evaluated activation energies due to irradiation doses are ranging from 0.58 to 0.68 eV.