AD总线多次复用型PCI接口芯片

基于PCI IP软核,本文设计了一款内置64KB OTP ROM的PCI接口芯片.为缩小芯片面积,进而降低芯片的设计成本,文章在研究PCI AD双向总线及PCI总线读时序特性的基础上,提出了一种PCI AD总线多次复用的方法.该方法实现了PCI AD总线与芯片外接E2PROM/Flash ROM地址总线和数据总线的复用.     

一种低复杂度DDFS的设计与ASIC实现

提出了一种基于ROM结构的直接数字频率综合器(DDFS)的实现算法和实现结构.采用三角函数分解法,降低了其对ROM的需求;并对电路进行优化设计,采用简单的移位相加,节省了乘法器,从而降低了整个电路的复杂度.用标准Verilog HDL实现整个DDFS;采用SMIC 0.18μm CMOS工艺库进行设计和实现.经仿真测试,该方法输出的频谱杂散大于60 dBc,仅需344位的ROM,工作频率可达100 MHz.整个DDFS的芯片面积为300μm×350μm.可满足大多数无线通信系统的要求.     

一种适用于数字视频编码器的高性能直接数字频率合成器

提出了一种适用于数字视频编码器的直接数字频率合成器DDFS(DirectDigitalFrequencySynthesizer)新结构.通过采用相位截断噪声整形技术,使所需要的ROM面积下降为传统结构的1/8.同时采用了其它优化策略进一步减少了ROM的面积,整个DDFS仅需要1152bit的ROM.DDFS输出在PAL制式下信噪比为69dB,NTSC制式下为70.7dB.     

MBE生长的InP DHBT的性能

报道了一种自对准InP/InGaAs 双异质结双极晶体管的器件性能.成功制作了U型发射极尺寸为2μm×12μm的器件,其峰值共射直流增益超过300,残余电压约为0.16V,膝点电压仅为0.6V,而击穿电压约为6V.器件的截至频率达到80GHz,最大震荡频率为40GHz.这些特性使此类器件更适合于低压、低功耗及高频方面的应用.     

MBE生长的InP DHBT的性能

报道了一种自对准InP/InGaAs 双异质结双极晶体管的器件性能.成功制作了U型发射极尺寸为2μm×12μm的器件,其峰值共射直流增益超过300,残余电压约为0.16V,膝点电压仅为0.6V,而击穿电压约为6V.器件的截至频率达到80GHz,最大震荡频率为40GHz.这些特性使此类器件更适合于低压、低功耗及高频方面的应用.     

一种适用于数字视频编码器的高性能直接数字频率合成器

提出了一种适用于数字视频编码器的直接数字频率合成器 DDFS(Direct Digital Frequency Synthesizer)新结构 .通过采用相位截断噪声整形技术 ,使所需要的 ROM面积下降为传统结构的 1/ 8.同时采用了其它优化策略进一步减少了 ROM的面积 ,整个 DDFS仅需要 115 2 bit的 ROM.DDFS输出在 PAL 制式下信噪比为 6 9d B,NTSC制式下为 70 .7d B     

新型双异质结双平面掺杂功率PHEMT

设计并制作了双异质结双平面掺杂的Al0.24Ga0.76As/In0.22Ga0.78As/Al0.24Ga0.76As功率PHEMT器件,采用双选择腐蚀栅槽结构,有效提高了PHEMT器件的输出电流和击穿电压.对于1μm栅长的器件,最大输出电流为500mA/mm,跨导为275mS/mm,阈值电压为-1.4V,最大栅漏反向击穿电压达到了33V.研究结果表明,在栅源间距一定时,栅漏间距对于器件的输出电流、跨导和击穿电压有很大关系,是设计功率PHEMT的关键之一.     

双波段/双视场红外光学系统设计

研究了双波段/双视场红外光学系统的设计,设计了双波段/双视场红外光学系统,引入衍射光学实现双波段成像,采用移动单个透镜实现视场切换.结果表明,该系统可以实现焦距为37mm/100mm,工作波段为3.7～4.3μm/8 12μm的双波段/双视场光学系统,F数为1.2,在空间频率201p/mm处的光学传递函数值＞0.5.应用结果表明,该系统结构简单,像质好.     

双腔并联式无阀压电微泵的设计及制作

为了实现微流控芯片的小型化、集成化,设计并制作了一种可定量连续输送微量液体的无阀压电微泵.该微泵采用双腔并联式结构,利用微机电系统(MEMS)技术在硅基片上制作了具有扩散口/喷口无阀结构的出入水口,采用压电双晶片作为驱动部件,以聚二甲基硅氧烷(PDMS)作为泵膜.测试结果表明,泵膜的厚度、工作频率和电压对微泵的输出流速均有明显的影响,在频率1100 Hz及电压80 V时,双腔体并联式无阀压电微泵的最大流速为210μL/min,约为相同结构单腔体微泵流速的1.5倍.     

一种电荷泵锁相环频率合成器的设计

基于SMIC的0.25μm工艺设计了一种输出频率范围为0.32～1.6GHz的电荷泵锁相环频率合成器电路.该电路采用了一种快速鉴频鉴相器和含有双交叉耦合结构的环形振荡器,同时根据电荷泵泵电流匹配的原则改进了电荷泵电路.HSIM仿真显示,锁相环频率合成器的锁定时间为1.3μz,功耗为28mW,锁定范围为5～20MHz,最大周对周抖动仅为50ps(0.8GHz).     

A 256K ROM fabricated using n-well CMOS process technology

A 256K bit CMOS ROM with a speed-power product of 0.085 pJ/bit has been developed. The excellent speed-power product and the high packing density have been achieved by using n-well CMOS technology and a serial-parallel ROM cell structure. The concept and characteristics of a serial-parallel ROM cell structure are discussed and compared to conventional ROM cell structures. The serial-parallel ROM cell structure gives more flexibility for ROM matrix design. The chip size and memory cell size of the 256K CMOS ROM are 5.98/spl times/6.00 mm and 7.0/spl times/7.0 /spl mu/m, respectively. Access time is 370 ns. The power supply currents in active and quiescent modes are 12 mA and less than 0.1 /spl mu/A at +5 V, respectively.     

An 80 ns 1 Mbit MASK ROM with a new memory cell

A high-speed 1-Mb MASK ROM incorporating a new through-hole programmed memory cell, named THOLE CELL, and a full CMOS static sense amplifier is described. The ROM has been fabricated using a double-polysilicon p-well CMOS technology. As a result of achieving a compact ROM cell that is as small as 5.2-/spl times/6.4 /spl mu/m/SUP 2/, even with relatively conservative 2.0 /spl mu/m design rules, a small die size of 7.08/spl times/7.7 mm/SUP 2/ is realized. The ROM organization is 128K/spl times/8 bit and has a typical access time of 80 ns. A typical active current of 8 mA is achieved, in spite of the fully static system. This ROM offers high speed and low power characteristics, while achieving small die size and short turnaround time.     

A composite CMOS gate array with 4K RAM and 128K ROM

A unique gate array structure, called a composite gate array, incorporating a RAM and a ROM along with ordinary gate arrays, is described. The composite gate array consists of a 128K ROM, a 4K RAM, and a 6K gate array, and is developed using 1.6-/spl mu/m CMOS technology. The RAM and ROM are partitioned into four 1K and eight 16K blocks for increasing flexibility of memory configuration. A distributed arrangement of memory blocks is used to permit completely automatic writing using fewer channels. In circuit performance, gate delay time is 1.0 ns, RAM access time is 25 ns, and ROM access time is 30 ns. A communication control processor for personal computer networks is successfully designed to demonstrate the feasibility of the gate array.     

一款异步256kB SRAM的设计

在集成电路设计制造水平不断提高的今天,SRAM存储器不断朝着大容量、高速度、低功耗的方向发展。文章提出了一款异步256kB(256k×1)SRAM的设计,该存储器采用了六管CMOS存储单元、锁存器型灵敏放大器、ATD电路,采用0.5μm体硅CMOS工艺,数据存取时间为12ns。     

Two new low-power Full Adders based on majority-not gates

Two novel low-power 1-bit Full Adder cells are proposed in this paper. Both of them are based on majority-not gates, which are designed with new methods in each cell. The first cell is only composed of input capacitors and CMOS inverters, and the second one also takes advantage of a high-performance CMOS bridge circuit. These kinds of designs enjoy low power consumption, a high degree of regularity, and simplicity. Low power consumption is targeted in implementation of our designs. Eight state-of-the-art 1-bit Full Adders and two proposed Full Adders are simulated using 0.18 μm CMOS technology at many supply voltages. Simulation results demonstrate improvement in terms of power consumption and power-delay product (PDP).     

Design techniques of low-power embedded EEPROM for passive RFID tag

This paper presents an optimized embedded EEPROM design approach which has reduced the power significantly in a short-range passive RFID tag. The proposed array control circuit employs an improved structure to minimize the leakage of memory bit cells. With the proposed array circuit design, the passive RFID tag can operate drawing a low quiescent current. The RFID tag with the proposed EEPROM was fabricated in a standard 0.35-μm four-metal two-poly CMOS process. Measurement results show that the erasing/writing current is 45 μA, and reading current consumption is 3 μA with a supply voltage of 3.3 V. The data read time is 300 ns/bit.     

Novel circuits for high speed ROMs

Novel approaches in circuit design, such as overlap timing without precharge, complementary ROM cells with two access lines, and overall chain-delay optimization, greatly increase the operational speed of ROMs. The innovative circuits fabricated with an advanced CMOS/SOS process resulted in an experimental 18-kbit (2K/spl times/9) look-up ROM performing a cycle time of 4 ns, a silicon area of 7.2 kmil/SUP 2/ and a radiation hardness of >10/SUP 5/ rad(Si). The overlap timing can multiply the address and data change rate without reducing the overall chain delay. The utilization of complementary ROM cells increases data processing speed, noise margin, and radiation hardness. The overall chain delay is greatly reduced by finding the minimum of a device size dependent time function. The complementary cell features a size of 12/spl times/17.2 /spl mu/m, shared contacts, and tantalum polycide access lines. The circuits discussed here can be used for any high-speed memory design, although the demonstration vehicle is a CMOS/SOS ROM.     

High-density CMOS ROM arrays

A single transistor cell and a precharge signal are used to reduce the memory cell area in bulk CMOS ROM arrays to 1.12 mil/SUP 2//bit. Use of SOS/CMOS technology further reduces the memory cell area to 0.38 mil/SUP 2//bit and makes possible CMOS ROMs of up to 32768 bits. Operation of both the array and the decoders is controlled by a precharge signal which is generated internally in a way which is transparent to the user. The CMOS ROMs thus produced are competitive with NMOS ROMs in both density and speed, yet retain all of the advantages of static CMOS circuits such as 1-/spl mu/W power dissipation, full 2.8-15 V voltage operating range, and full -55/spl deg/C-125/spl deg/C temperature range.     

一种电流自校准14位、50Msample/s CMOS DAC

文章介绍一种14位、50Msample/s的电流驱动型CMOS DAC.该电路的核心由31个温度计编码的高5位电流源、15个温度计编码的中间4位电流源和5个二进制编码的低5位电流源构成.为了达到更高的静态线性度,一种新颖的电流自校准技术被提出,用来对最高5位的电流源进行自校准.这种自校准完全是在后台操作的,并不需要一个替代电流源去替代正在被校准的那一路电流源.该芯片采用0.25μm标准CMOS工艺制造,芯片面积为3.54mm².测试结果显示芯片的静态分辨率达到12位.     

An experimental DRAM with a NAND-structured cell

An experimental 256-Mb dynamic random access memory using a NAND-structured cell (NAND DRAM) has been fabricated. The NAND-structured cell has four memory cells connected in series, which reduces the area of isolation between the adjacent cells and also reduces the bit-line contact area. The cell area per bit measures 0.962 μm², using 0.4-μm CMOS technology, which is 63% in comparison with the conventional cell. In order to reduce the die size, time division multiplex sense-amplifier (TMS) architecture, in which a sense amplifier is shared by four bit lines, has been newly introduced. The chip area is 464 mm², which is 68% compared with the DRAM using the current cell structure. The data can be accessed by a fast-block-access mode up to 512 bytes as well as a random access mode. Typical 112-ns access time of the first data in a block and 30-ns serial cycle time are achieved