A two-dimensional analytical threshold voltage model for MOSFET's with arbitrarily doped substrates

A threshold voltage model is presented which is valid for short- and long-channel MOSFET's with a nonuniform substrate doping profile. The model is based upon an approximate two-dimensional analytical solution of Poisson's equation for a MOSFET of arbitrary substrate doping profile which takes into account the effect of curved junctions of finite depth. The analytical model is compared to MINIMOS simulations showing that it can accurately predict short-channel threshold voltage falloff and threshold voltages in this vicinity without the use of fitting parameters.     

Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study

The novel features of an asymmetric double gate single halo (DG-SH) doped SOI MOSFET are explored theoretically and compared with a conventional asymmetric DG SOI MOSFET. The two-dimensional numerical simulation studies demonstrate that the application of single halo to the double gate structure results in threshold voltage roll-up, reduced DIBL, high drain output resistance, kink free output characteristics and increase in the breakdown voltage when compared with a conventional DG structure. For the first time, we show that the presence of single halo on the source side results in a step function in the surface potential, which screens the source side of the structure from the drain voltage variations. This work illustrates the benefits of high performance DG-SH SOI MOS devices over conventional DG MOSFET and provides an incentive for further experimental exploration.     

Evaluation of graded-channel SOI MOSFET operation at high temperatures

This paper presents a comparative analysis between graded-channel (GC) and conventional fully depleted SOI MOSFETs devices operating at high temperatures (up to 300 °C). The electrical characteristics such as threshold voltage and subthreshold slope were obtained experimentally and by two-dimensional numerical simulations. The results indicated that GC transistors present nearly the same behavior as the conventional SOI MOSFET devices with similar channel length. Experimental analysis of the g_m/I_DS ratio and Early voltage demonstrated that in GC devices the low-frequency open-loop gain is significantly improved in comparison to conventional SOI devices at room and at high-temperature due to the Early voltage increase. The multiplication factor and parasitic bipolar transistor gain obtained by two-dimensional numerical simulations allowed the analysis of the breakdown voltage, which was demonstrated to be improved in the GC as compared to conventional SOI transistors in thin silicon layer devices in the whole temperature range under analysis.     

A simple theory to predict the threshold voltage of short-channel IGFET's

A simple expression for the threshold voltage of an IGFET is derived from a charge conservation principle which geometrically takes into account two-dimensional edge effects. The expression is derived for zero drain voltage and is valid for short and long-channel lengths. The dependence of the threshold voltage on the source and drain diffusion depth, r_j, and channel length, L, is explicitly given. In the limit, L/r_j → ∞, the threshold voltage equation reduces to the familiar expression for the long-channel case.The theory is compared with the measured threshold voltages on IGFET's fabricated with 1·4, 3·8 and 7·4 μm channel lengths. The dependence of the threshold voltage under backgate bias voltages ranging from zero to breakdown agrees closely with the theory.     

Two-dimensional analytical modeling of threshold voltages of short-channel MOSFET's

We present an analytical model of the threshold voltage of a short-channel MOSFET based on an explicit solution of two-dimensional Poisson's equation in the depletion region under the gate. This model predicts an exponential dependence on channel length (L), a linear dependence on drain voltage (VD), and an inverse dependence on oxide capacitance (εox/tox). An attractive feature of this model is that it provides an analytical closed-form expression for the threshold voltage as a function of material and device parameters (tox, VD, L, substrate bias, and substrate doping concentration) without making premature approximations. Also, this expression reduces to the corresponding expression for long-channel devices.     

Simple model for threshold voltage in a short-channel IGFET

The threshold voltage of a short-channel IGFET can be expressed, in relation to that for a long-channel device, asV_{T} = V_{TLC} - alpha - betaV_{DS}. This behavior is deduced from a charge injection model and is verified both by two-dimensional numerical simulations and by actual threshold data.     

A new long-channel MOSFET model

A new highly accurate long-channel MOSFET model which is valid both in the linear and saturation regions by taking into account two-dimensional effects over the whole channel is presented in this paper. The calculated results are in excellent agreement with the experimental data. Compared with three other long-channel MOSFET models, the double integral model, the charge-sheet model and the single-integral model, our model has some advantages. The results demonstrate that two-dimensional effects are important in the current continuity near the drain end of the channel and cannot be neglected when the MOSFET is operating in saturation.     

Comparative study of leakage power in CNTFET over MOSFET device

A comparison of the CNTFET device with the MOSFET device in the nanometer regime is reported.The characteristics of both devices are observed as varying the oxide thickness.Thereafter,we have analyzed the effect of the chiral vector and the temperature on the threshold voltage of the CNTFET device.After simulation on the HSPICE tool,we observed that the high threshold voltage can be achieved at a low chiral vector pair.It is also observed that the effect of temperature on the threshold voltage of the CNTFET is negligibly small.After that,we have analyzed the channel length variation and their impact on the threshold voltage of the CNTFET as well as MOSFET devices.We found an anomalous effect from our simulation result that the threshold voltage increases with decreasing the channel length in CNTFET devices; this is contrary to the well known short channel effect.It is observed that at below the 10 nm channel length,the threshold voltage is increased rapidly in the case of the CNTFET device,whereas in the case of the MOSFET device,the threshold voltage decreases drastically.     

Compact charge and capacitance modeling of undoped ultra-thin body (UTB) SOI MOSFETs

We present an analytic, explicit and continuous charge model for a long-channel UTB (ultra-thin body) SOI (silicon-on-insulator) MOSFET, from which analytical expressions of the total capacitances are obtained. Our model is valid from below to well above threshold, without suffering from discontinuities between the regimes. It is based on a unified charge control model derived from Poisson’s equation. The drain-current, charge and capacitances expressions result in continuous explicit functions of the applied bias.The calculated capacitance characteristics are validated by 2D numerical simulations showing a very good agreement for different silicon film thicknesses.     

Single-event burnout hardening of planar power MOSFET with partially widened trench source

We present a single-event burnout (SEB) hardened planar power MOSFET with partially widened trench sources by three-dimensional (3D) numerical simulation.The advantage of the proposed structure is that the work of the parasitic bipolar transistor inherited in the power MOSFET is suppressed effectively due to the elimination of the most sensitive region (P-well region below the N+ source).The simulation result shows that the proposed structure can enhance the SEB survivability significantly.The critical value of linear energy transfer (LET),which indicates the maximum deposited energy on the device without SEB behavior,increases from 0.06 to 0.7 pC/μm.The SEB threshold voltage increases to 120 V,which is 80％ of the rated breakdown voltage.Meanwhile,the main parameter characteristics of the proposed structure remain similar with those of the conventional planar structure.Therefore,this structure offers a potential optimization path to planar power MOSFET with high SEB survivability for space and atmospheric applications.     

凹槽栅MOSFET凹槽拐角的作用与影响研究

短沟道效应是小尺寸ＭＯＳＦＥＴ中很重要的物理效应之一，凹槽栅ＭＯＳＦＥＴ对短沟道效应有很强的抑制能力，通过对凹槽栅ＭＯＳＦＥＴ结构，特性的研究，发现凹槽拐角对凹槽栅ＭＯＳＦＥＴ的阈值电压及特性有着显著的影响，凹槽拐角处的阈值电压决定着整个凹槽栅ＭＯＳＦＥＴ的阈值电压，凹槽拐角的曲率半径凹槽ＭＯＳＦＥＴ一个重要的结构参数，通过对凹槽拐角的曲率半径，源漏结深及沟道掺杂浓度进行优化设计，可使凹槽栅ＭＯＳ     

A numerical model of avalanche breakdown in MOSFET's

An accurate numerical model of avalanche breakdown in MOSFET's is presented. Features of this model are a) use of an accurate electric-field distribution calculated by a two-dimensional numerical analysis, b) introduction of multiplication factors for a high-field path and the channel current path, and c) incorporation of the feedback effect of the excess substrate current induced by impact ionization into the two-dimensional calculation. This model is applied to normal breakdown observed in p-MOSFET's and to negative-resistance breakdown (snap-back or switchback breakdown) observed in short-channel n-MOSFET's. Excess substrate current generated from channel current by impact ionization causes a significant voltage drop across the substrate resistance in short-channel n-MOSFET's. This voltage forward-biases the source-substrate junction and increases channel current causing a positive feedback effect. This results in a decrease of the breakdown voltage and leads to negative-resistance characteristics. Current-voltage characteristics calculated by the present model agree very well with experimental results. Another model, highly simplified and convenient for device design, is also presented. It predicts some advantages of p-MOSFET's over n-MOSFET's from the standpoint of avalanche breakdown voltage, particularly in the submicrometer channel-length range.     

Characteristics of enhancement/depletion (E/D) gate MOSFET fabricated using ion implantation

The E/D gate MOSFET, which has an enhancement and depletion mode region under the same gate, is fabricated by using ion implantation as a tool for shifting threshold voltage. Threshold voltage, transconductance and drain breakdown voltage are studied as functions of implantation dose up to 12 × 10¹² cm^?2.It is found that, at an appropriate dose, the transconductance of this device is determined solely by the channel length of the enhancement mode region, and is larger than that of a short channel MOSFET with a standard structure but with the same drain breakdown voltage. Moreover, the dependence of threshold voltage on substrate bias measured in this device is found less sensitive to the transconductance than that in the standard short channel MOSFET.     

Simulation of hot-electron trapping and aging of nMOSFETs

An analysis of the degradation of 1-μm-gate-length nMOSFET operating under normal biasing conditions at room temperature is reported. A physical model of hot-electron trapping in SiO₂ is developed and is used with a two-dimensional device simulator (PISCES) to simulate the aging of the device under normal biasing conditions. The initial degradation takes place near the high-field drain region and spreads over a long time toward the source. The degraded I-V characteristics of the MOSFET exhibit a shift of the pinchoff voltage and a compression of the transconductance, for forward and reverse operation, respectively. The simulated degradation qualitatively agrees with reported experimental data. Large shifts of the MOSFET threshold voltage for small drain voltages result as the degradation is spreading toward the source. An inflection point arises for low gate and drain voltages in the drain I-V characteristics of the MOSFET. This inflection point originates when the pinchoff of the channel-induced trapped-electron charge is overcome by the drain voltage; the drain acts as a second gate (short-channel effect). The estimation of the device's lifetime by simulated aging is proposed     

An analytic and accurate model for the threshold voltage of short channel MOSFETs in VLSI

Based on the two-dimensional Poisson equation, the surface potential distribution along the surface channel of a MOSFET has been analytically derived by assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage. The existence of a minimum surface potential point along the channel of a MOSFET under an applied drain bias is consistent with the numerical results of the two-dimensional analysis. The effects of finite source and drain junction depths have been elegantly included by modifying the depletion capacitance under the gate and the resulted threshold voltage model has been compared to the results of the two-dimensional numerical analysis. It has been shown that excellent agreement between these results has been obtained for wide ranges of substrate doping, gate oxide thickness, channel length (< 1 μm), substrate bias, and drain voltage. Moreover, comparisons between the developed model and the existing experimental data have been made and good agreement has been obtained. The major advantages of the developed model are that no iterations and no adjustable fitting parameters are required. Therefore, this simple and accurate threshold voltage model will become a useful design tool for ultra short channel MOSFETs in future VLSI implementation.     

Threshold voltage model for deep-submicrometer fully depleted SOIMOSFET's

The threshold voltage, V_th, of fully depleted silicon-on-insulator (FDSOI) MOSFET with effective channel lengths down to the deep-submicrometer range has been investigated. We use a simple quasi-two-dimensional model to describe the V_th roll-off and drain voltage dependence. The shift in threshold voltage is similar to that in the bulk. However, threshold voltage roll-off in FDSOI is less than that in the bulk for the same effective channel length, as predicted by a shorter characteristic length l in FDSOI. Furthermore, ΔV_th is independent of back-gate bias in FDSOI MOSFET. The proposed model retains accuracy because it does not assume a priori charge partitioning or constant surface potential. Also it is simple in functional form and hence computationally efficient. Using our model, V _th design space for Deep-Submicrometer FDSOI MOSFET is obtained. Excellent correlation between the predicted V_th design space and previously reported two-dimensional numerical simulations using MINIMOS5 is obtained     

Numerical Simulation of BJMOSFET on Current-Voltage Characteristics

A new power MOSFET Structure with a pn junction--Bipolar Junction MOSFET (BJMOSFET) has been proposed. The device has the advantages of both BJT and FET. The numerical model of the I-V characteristics of BJMOSFET has been obtained on the basis of both numerical and analytical methods. With the software package of Mathematic, we firstly calculate the gain factor, and then simulate the voltage tranmission, voltage output and voltage transfer's characteristic graphs of the BJMOSFET. The simulation result indicates that BJMOSFET has the current density, which is about 25% larger than the power MOSFET, under the same operating conditions and with the same structure parameters, except that the threshold voltage increase a little.     

A new method for extracting the counter-implanted channel profileof enhancement-mode p-MOSFETs

A new methodology is proposed to extract the nonuniform channel doping profile of enhancement mode p-MOSFETs with counter implantation, based on the relationship between device threshold voltage and substrate bias. A selfconsistent mathematical analysis is developed to calculate the threshold voltage and the surface potential of counter-implanted long-channel p-MOSFET at the onset of heavy inversion. Comparisons between analytic calculation and two-dimensional (2-D) numerical analysis have been made and the accuracy of the developed analytic model has been verified. Based on the developed analytic model, an automated extraction technique has been successfully implemented to extract the channel doping profile. With the aid of a 2-D numerical simulator, the subthreshold current can be obtained by the extracted channel doping profile. Good agreements have been found with measured subthreshold characteristics for both long- and short-channel devices. This new extraction methodology can be used for precise process monitoring and device optimization purposes     

Subthreshold conduction in MOSFET's

The dependence of channel current in subthreshold operation upon drain, gate, and substrate voltages is formulated in terms of a simple model. The basic results are consistent with earlier approaches for long-channel devices. For short-channel devices, the variation of current with drain voltage up to the punch-through voltage is accurately described. The threshold voltage of a short-channel device as a function of applied voltages follows as a natural result of the derivation. Results are presented which confirm the theory over a wide range of drain and gate voltages. With the application of substrate bias it is concluded from the data and the theory that two-dimensional effects can cause dramatic increases in the drain conductance.     

全耗尽异质栅单Halo SOI MOSFET二维模型

为了抑制深亚微米SOI MOSFET的短沟道效应,并提高电流驱动能力,提出了异质栅单Halo SOI MOSFET器件结构,其栅极由具有不同功函数的两种材料拼接而成,并在沟道源端一侧引入Halo技术.采用分区的抛物线电势近似法和通用边界条件求解二维Poisson方程,为新结构器件建立了全耗尽条件下的表面势及阈值电压二维解析模型.对新结构器件与常规SOI MOSFET性能进行了对比研究.结果表明,新结构器件能有效抑制阈值电压漂移、热载流子效应和漏致势垒降低效应,并显著提高载流子通过沟道的输运速度.解析模型与器件数值模拟软件MEDICI所得结果高度吻合.