Models for subthreshold and above-threshold currents in 0.1-μmpocket n-MOSFETs for low-voltage applications

We present a model for subthreshold current in deep-submicrometer pocket n-MOSFETs based on the diffusion current transport equation, the quasi-two-dimensional (2-D) Poisson equation and a doping-density-dependent mobility model, and a model for above-threshold current in deep-submicrometer pocket n-MOSFETs based on the drift-diffusion current transport equation for nonuniformly doped MOSFETs, the charge-sheet approximation, a solution of the one-dimensional (1-D) Poisson equation, a quasi-2-D model for the velocity saturation region, longitudinal- and transverse-field-dependent mobility models. The analytic models for subthreshold and above-threshold currents are used to efficiently construct viable design spaces locating well-designed 0.1-μm pocket n-MOSFETs that meet all the device design specifications of off-state (leakage) current, on-state (drive) current, and power-supply voltage. The model for subthreshold current correctly predicts an increase in off-state current in sub-100 nm pocket n-MOSFETs. The model for above-threshold current generates I_D-V_DS characteristics of a variety of deep-submicrometer pocket n-MOSFETs     

Analytical subthreshold surface potential model for pocket n-MOSFETs

A correct and improved analytical subthreshold surface potential model for pocket n-MOSFETs is proposed. The model is based on solutions of the quasi-two-dimensional (quasi-2-D) Poisson's equation, which satisfy rigorously the boundary conditions of continuity of potential and electric field in the lateral direction along the surface of pocket devices. The closed-form model equations without any fitting empirical formulas efficiently and correctly generate surface potential profiles between the source and drain of deep-submicrometer as well as long-channel pocket n-MOSFETs. Drain-induced barrier lowering (DIBL) effect of deep-submicrometer pocket n-MOSFETs is also predicted by the potential model. The subthreshold surface potential model is applied to off-state current and threshold voltage of deep-submicrometer or sub-100-nm pocket n-MOSFETs.     

Optimization of sub-0.1-μm offset Γ-shaped gate MHEMTs for millimeter-wave applications

We examine the effects of device scaling in both vertical and lateral dimensions for the metamorphic high electron mobility transistors (MHEMTs) on the DC and millimeter-wave electrical performances by using a hydrodynamic transport model. The well-calibrated hydrodynamic simulation for the sub-0.1-μm offset Γ-gate In_0.53Ga_0.47As/In_0.52Al_0.48As MHEMTs shows a reasonable agreement with the electrical characteristics measured from the fabricated 0.1 μm devices. We have calibrated all the parameters using the measurement data with various physical considerations to take into account the sophisticated carrier transport physics in sub-0.1-μm devices. Being simulated with these calibrated parameters, the optimum device performance is obtained at a source-drain spacing of 2 μm, a gate length of 0.05 μm, a barrier thickness of 10 nm and a channel thickness of 12 nm.     

The enhancement of gate-induced-drain-leakage (GIDL) current inshort-channel SOI MOSFET and its application in measuring lateralbipolar current gain β

An off-state leakage current unique for short-channel SOI MOSFETs is reported. This off-state leakage is the amplification of gate-induced-drain-leakage current by the lateral bipolar transistor in an SOI device due to the floating body. The leakage current can be enhanced by as much as 100 times for 1/4 μm SOI devices. This can pose severe constraints in future 0.1 μm SOI device design. A novel technique was developed based on this mechanism to measure the lateral bipolar transistor current gain β of SOI devices without using a body contact     

Effect of gate length on DC performance of AlGaN/GaN HEMTs grown by MBE

The DC performance of AlGaN/GaN high electron mobility transistors grown by plasma-assisted molecular beam epitaxy was investigated for gate lengths in the range 0.1–1.2 μm. On 0.25 μm gate length devices we obtained 40 V_DS operation with >50 mA peak I_D. The peak drain current density was 0.44 A/mm for 100 μm gate width devices with 1.2 μm gate lengths. The extrinsic transconductance (g_m) decreased with both gate length and gate width and was 75 mS/mm for all gate widths for 0.25 μm devices. E-beam written gates typically produced a slightly lower Schottky barrier height than optically patterned gates.     

An experimentally validated analytical model for gate line-edgeroughness (LER) effects on technology scaling

This letter introduces an analytical model to represent line-edge roughness (LER) effects on both off-state leakage and drive current for sub-100-nm devices. The model partitions a given device into small unit cells along its width, each unit cell assumes a constant gate length (i.e., cell's width is small compared to LER spatial frequency). An analytical model is used to represent saturated threshold voltage dependency on the unit cell's gate length. Using this technique, an efficient and accurate model for LER effects (through V_ts variations) on off-state leakage and drive current is proposed and experimentally validated using 193 and 248 nm lithography for devices with 80-nm nominal gate lengths. Assuming that the deviation from the ideal 0-LER case remains constant from generation to generation, the model predicts that 3 nm or less LER is required for 50-60-nm state-of-the-art devices in the 0.1-μm technology node. Based on data presented, we suggest that the LER requirement for this technology node is attainable with an alternated phase-shift type of patterning process     

Hot-carrier-induced degradation in ultra-thin-film fully-depleted SOI MOSFETs

The charge-pumping measurement technique was successfully applied to submicron (L_eff = 0.35 μm) n-MOSFETs on ultra-thin (50 nm) SOI film. The hot-carrier-induced degradation is studied by examining the damages to both gate-oxide and buried-oxide (BOX) interfaces. We found that when stressed at maximum substrate current, interface-trap generation is still the primary cause for hot-carrier-induced degradation. Even for ultra-thin-film SOI devices, the hot-carrier-induced damage is locally confined to the gate-oxide interface and only minor damage is observed at the buried-oxide interface. The buried-oxide interface charging contributes less than 5% of the overall drain current degradation.     

Submicron-meter tunneling field-effect poly-Si thin-film transistors with a thinned channel layer

Submicron-meter poly-Si tunneling-effect thin-film transistor (TFT) devices with a thinned channel layer have been investigated. With reducing the gate length to be shorter than 1 μm, the poly-Si TFT device with conventional MOSFET structure is considerably degraded. The tunneling field-effect transistor (TFET) structure can be employed to alleviate the short channel effect, thus largely suppressing the off-state leakage. However, for a poly-Si channel layer of 100 nm thickness, the TFET structure causes a small on-state current, which may not provide well sufficient driving current. By reducing the channel layer thickness to be 20 nm, the on-state current for the TFET structure can be largely increased, due to the enhanced bending of energy band for a thinned channel layer. As a result, for the TFET poly-Si TFTs at a gate bias of 5 V and a drain bias of 3 V, a 20-nm channel layer leads to an on-state current of about 1 order larger than that by a 100-nm channel layer, while still keeping an off-state leakage smaller than 0.1 pA/μm. Accordingly, the submicron-meter TFET poly-Si TFT devices with a thinned channel layer would show good feasibility for implementing high packing density of poly-Si TFT devices.     

A study on hot carrier effects on N-MOSFETs under high substrate impurity concentration

A systematic investigation of the influences of high substrate doping on the hot carrier characteristics of small geometry n-MOSFETs down to 0.1 /spl mu/m has been carried out. Results indicate that the dependence of substrate current and impact ionization rate on substrate impurity concentration is reversed in long channel and short channel devices. In the long channel case, both increase with rising substrate impurity concentration, while they decrease in the case of short channel devices. An explanation for this phenomenon based on the lucky electron model has been developed. The dependence of other characteristics on impurity concentration has also been studied. The dependence of off-leakage current has been found to fall as the gate oxide is reduced in thickness. Regarding the dependence of hot carrier degradations, the degradation of drain currents becomes smaller as the substrate impurity concentration increases in the case of short channel devices. Further, in the extremely high impurity doping region, a new hot carrier degradation mode was found, in which the maximum transconductance values of n-MOSFETs increase after hot carrier stress. This new degradation mode can be explained in terms of effective channel length shortening caused by electron trapping.<>     

Dynamic surface temperature measurements in SiC epitaxial power diodes performed under single-pulse self-heating conditions

Semiconductor devices development, design and optimization require the use of computer simulation tools able to predict the entire device safe operating area (SOA), something that it is not always possible due to limitations in some of the physical models in predicting certain properties of device operation under extreme conditions (i.e. high carrier injection levels and high temperature). In order to improve our understanding of device operation under these extreme conditions experimental data of the dynamic IV characteristics and temperature time evolution and space distribution are required. The experimental data obtained are then used in the development of improved physical models and simulation tools.

In this work, dynamic surface temperature measurements as a function of current pulse peak density and length were performed on SiC-PiN epitaxial power diodes. The measurements were carried out using an infrared (IR) microscope developed in our lab capable of measuring space and time surface temperature distributions in semiconductor devices operating under self-heating conditions [Solid State Electron 2001;45(12):2057]. The minimum detected spot size is 15 μm, while the signal raising time is detector limited to about 1 μs. The lowest detectable temperature increment is at least 10 °C over room temperature.

Using this instrument, dynamic thermal phenomena in 4.5 kV SiC-PiN epitaxial power diodes [Mater Sci Forum 2001;353–356:727] subjected to 1 ms long 100–6000 A/cm² and 0.1–5 ms long 3000 A/cm² current pulses have been studied. The possibility of obtaining dynamic surface temperature information from SiC electronic devices operating under self-heating conditions with time constants in the order of ms is demonstrated.     

Gate length scalability of n-MOSFETs down to 30 nm: Comparisonbetween LDD and non-LDD structures

Gate length scalability of LDD and non-LDD n-MOSFETs are investigated in terms of resistance to short-channel effects. Extremely small gate electrodes are delineated using electron beam direct writing and highly selective dry-etching techniques. An LDD MOSFET with As-implanted 15-nm-deep junctions shows a superior scalability down to 30 nm. In contrast, in the case of a non-LDD MOSFET having Sb-δ-doped 18-nm-deep junctions, the drain induced barrier lowering (DIBL) mechanism limits the minimum gate length to around 80 nm, at which favorable device operation is achieved. The difference between built in potential of source/drain junctions (around 0.1 eV) of LDD and non-LDD devices is found to remarkably affect short channel characteristics in the sub-0.1-μm region     

High-temperature off-state characteristics of thin-SOI powerdevices

High-temperature off-state characteristics of thin-SOI RESURF LDMOS transistors were studied experimentally and theoretically and compared with off-state characteristics of junction-isolated bulk-Si power devices. At 200°C, the off-state leakage current in the SOI devices was approximately 200 times lower than in the bulk-Si devices with a comparable breakdown voltage and on-resistance. At 300°C, well beyond the operating range of the bulk devices, the off-state leakage current in the SOI devices was only 1.5 nA/μm. The leakage current appears to scale with the thickness of the SOI layer. The results of this study indicate that LDMOS transistors fabricated in thin SOI layers are well suited for high-temperature power IC applications     

Impact of transport noise enhancement in scaled-down MOSFET

This paper describes a theoretical approach to understanding the impact of carrier-density-fluctuation-induced high-frequency transport noise in scaled-down MOSFETs. A theoretical expression is formulated on the basis of the charge-density conservation equation and current continuity condition. The relation between drain current noise and carrier-density fluctuation is also discussed. As scaling level is increased, the high-frequency component of normalized carrier-density fluctuation power is enhanced because the averaging effect of fluctuation power is suppressed. It is shown that the high-frequency component of drain current noise in a 0.1-μm-channel device is more significant than that in a 1-μm-channel device.     

热载流子应力下n-MOSFET线性漏电流的退化

研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。     

Study of the leakage current suppression for hybrid-Schottky/ohmic drain AlGaN/GaN HEMT

The leakage current suppression mechanism in AlGaN/GaN High Electron Mobility Transistors (HEMTs) is investigated. It is known that leakage current can cause severe reliability problems for HEMT devices and conventional AlGaN/GaN HEMT devices suffer from detrimental off-state drain leakage current issues, especially under high off-state drain bias. Therefore, a leakage current suppression technique featuring hybrid-Schottky/ohmic-drain contact is discussed. Through the 2-zones leakage current suppression mechanism by the hybrid-Schottky/drain metal including the shielding effect of the rough ohmic-drain metal morphology and the drain side electric field modulation, AlGaN/GaN HEMT featuring this novel technique can significantly enhance the leakage current suppression capability and improve the breakdown voltage. An analytical method using loop-voltage-scanning is proposed to illustrate the optimization procedure of the hybrid-Schottky/ohmic drain metallization on leakage current suppression. Through the comparison of the loop leakage current hysteresis of conventional ohmic drain HEMT and hybrid-Schottky/ohmic drain, the leakage current suppression mechanism is verified through the leakage current considering surface acceptor-like trap charging/discharging model. Device featuring the hybrid-Schottky/ohmic drain technique shows an improvement in breakdown voltage from 450 V (with no Schottky drain metal) to 855 V with a total drift region length of 9 μm, indicating enhanced off-state reliability characteristics for the AlGaN/GaN HEMT devices.     

Dependence of hot-carrier immunity on channel length and channelwidth in MOSFETs with N2O-grown gate oxides

The authors report on the channel length (0.5-5 μm) and width (0.6-10 μm) dependence of hot-carrier immunity in n-MOSFETs with N ₂O-grown gate oxides (~85 Å). While channel hot-carrier-induced degradation has a strong dependence on channel geometry in control devices, the degradation and its channel geometric dependences are greatly suppressed in devices with N₂O-gate oxides. Under Fowler-Nordheim injection stress, the control device shows an enhanced degradation with decreasing channel length and increasing channel width, whereas N₂O device exhibits a less dependence on channel geometry     

Effects of hot carriers in offset gated polysilicon thin-film transistors

The effects of hot carriers on the characteristics of intrinsic offset gated n-channel polysilicon thin-film transistors (TFTs), with channel length L = 10 μm, have been studied in relation to the offset length ΔL. From the evolution of the transfer and output characteristics during stress, the degree of the device degradation is deduced. In devices with ΔL = 0.5 and 1 μm, the on-state current is substantially reduced, whereas the subthreshold region remains almost unaffected. In devices with ΔL = 2 μm, the transfer characteristics are shifted first positively after short stressing time and then negatively, the on-state current is still substantially reduced and well-defined kink is formed in the subthreshold region. The device degradation is found to become more pronounced as the gate offset length increases. A model explaining the post-stress performance of offset gated devices is presented.     

A simulation study to evaluate the feasibility of midgap workfunction metal gates in 25 nm bulk CMOS

The performance of 25 nm metallurgical channel length bulk MOSFETs with midgap workfunction metal gates has been compared with conventional polysilicon gates and bandedge workfunction metal gates. Device design using pocket halo implants was implemented to achieve the required off-state leakage specification. Highly accurate, full device simulations have been performed with a linear chain of inverters taking quantum effects into consideration. Drain induced barrier lowering (DIBL) was used as an indicator of short channel effects, and the stage delay of a linear chain of inverters and the on state drive current (I/sub on/) have been identified as metrics for performance. Compared to bandedge metal gates, midgap gates suffer from lower drive currents for both NMOS and PMOS devices. On the other hand, midgap devices were comparable in their performance to N/sup +/ polysilicon gated devices and exceeded that of P/sup +/ polysilicon devices. This high performance was attributed to a lack of poly depletion in midgap metal devices and a higher degree of DIBL which resulted in a lower V/sub t/ under high drain bias providing high drive current. Conclusions have been drawn on the feasibility of using midgap metal gates to simplify process integration in future generation CMOS devices.     

Pre-alloying implants with indium as an enabling technology to extend titanium salicide towards 0.1-μm linewidths

Pre-amorphisation implants (PAI) are the most promising technique to extend the use of TiSi₂ towards 0.1 μm. We report an implant strategy using indium, employing its favourable alloying properties towards silicon, titanium and the dopants. Its implementation in a 0.18-μm CMOS technology gave full C54–TiSi₂ transformation on poly lines. Additionally the NMOS contact resistances were found to be largely reduced. Data on unpatterned monitor wafers show indium to reduce the C54–TiSi₂ transformation temperature by at least 50°C, whereas the reduction found when using arsenic as implant species is 25°C.     

Comparative analysis of hot electron injection and induced devicedegradation in scaled 0.1 μm SOI n-MOSFETs using Monte Carlosimulation

A self-consistent Monte Carlo (MC) simulator is employed to investigate and compare hot electron phenomena in three competing design strategies for 0.1 μm SOI n-MOSFETs operating under low voltage conditions, i.e., V_d considerably less than the Si-SiO₂ injection barrier height φ_b. Simulations of these designs reveal that non-local carrier transport effects and two-dimensional current how play a significant role in determining the relative rate and location of hot electron injection into both the front and back oxides. Specifically, simulations indicate that electron-electron interactions near the drain edge are a main source of electron energies exceeding φ_b. The hot electron injection distributions are then coupled with an empirical model to generate interface state distributions at both the front and back oxide interfaces. These interface states are incorporated into a drift-diffusion simulator to examine relative hot-electron-induced device degradation for the three 0.1 μm SOI designs. Simulations suggest that both the Si layer thickness and doping distribution affect device sensitivity to hot-electron-induced interface states. In particular, the simulations show that a decrease in the channel doping results in increased sensitivity to back oxide charge. In the comparison of the heavily-doped designs, the design with a thinner T_Si experiences significantly more hot-electron-induced oxide damage in the back oxide and more degradation from the charged states at the back interface