A wafer-level 3D packaging structure with Benzocyclobutene as a dielectric for multichip module fabrication

A new wafer-level 3D packaging structure with Benzocyclobutene (BCB) as interlayer dielectrics (ELDs) for multichip module fabrication is proposed for application in the Ku-band wave. The packaging structure consists of two layers of BCB films and three layers of metallized films, in which the monolithic microwave IC (MMIC), thin film resistors, striplines and microstrip lines are integrated. Wet etched cavities fabricated on the silicon substrate are used for mounting active and passive components. BCB layers cover the components and serve as ILDs for interconnections. Gold bumps are used as electric interconnections between different layers, which eliminates the need to prepare vias by costly dry etching and deposition processes. In order to get high-quality BCB films for the subsequent chemical mechanical planarization (CMP) and multilayer metallization processes, the BCB curing profile is optimized and the roughness of the BCB film after the CMP process is kept lower than 10 nm. The thermal, mechanical and electrical properties of the packaging structure are investigated. The thermal resistance can be controlled below 2 ℃/W. The average shear strength of the gold bumps on the BCB surface is around 70 N/mm~2. The performances of MMIC and interconnection structure at high frequencies are optimized and tested. The 5 -parameters curves of the packaged MMIC shift slightly showing perfect transmission character. The insertion loss change after the packaging process is less than 1 dB range at the operating frequency and the return loss is less than -8 dB from 10 to 15 GHz.     

Plasma Etching for Sub-45-nm TaN Metal Gates on High-k Dielectrics

Etching of TaN gates on high-k dielectrics (HfO₂ or HfAlO) is investigated using HBr/Cl₂ chemistry in a decoupled plasma source (DPS). The patterning sequence includes 248-nm lithography, plasma photoresist trimming, etching of a SiN-SiO₂ hard mask, and photoresist stripping, followed by TaN etching. TaN etching is studied by design of experiment (DOE) with four variables using a linear model with interactions. It is found that at a fixed substrate temperature and wafer chuck power, etch critical dimensions (CD) gain decreases with decreasing HBr/Cl₂ flow rate ratio and pressure and with increasing source power and total gas flow rate. Based on these DOE findings, subsequent optimization is performed and a three-step etching process is developed; a main feature of the process is progressively increasing HBr/Cl₂ flow rate ratio. The optimized process provides etch CD gain within 2 nm and gate profile close to vertical and reliable etch-stop on high-k dielectric. This process is successfully applied to the fabrication of the 40-nm HfAlO/TaN gate stack p-MOSFETs with good electrical parameters     

Integration and characterization of amorphous silicon thin-filmtransistor and Mo-tips for active-matrix cathodes

We have designed and monolithically integrated amorphous silicon thin-film transistor (a-Si TFT) with Mo-tip field emitter arrays (FEAs) on glass substrate for active-matrix cathodes (AMCs) in field-emission display (FED) application. In our AMCs, a light shield layer of metal was introduced to reduce the photo leakage and back channel currents of a-Si TFT. The light shield was designed to have the role of focusing grid to focus emitted electron beams from the AMC on the corresponding anode pixel by forming it around the Mo-tip FEAs as well as above the a-Si TFT. The thin film depositions in a-Si TFTs were performed at a high temperature of above 360°C to guarantee the postvacuum packaging process of cathode and anode plates in FED. Also, a novel wet etching process was developed for n⁺-doped-a-Si etching with high etch selectivity to intrinsic a-Si and good etch controllability and was used in the fabrication of inverted stagger TFT with a very thin active layer. The developed a-Si TFTs had good enough performance to be used as control devices for AMCs with Mo-tip emitters. The fabricated AMCs exhibited very effective aging process for field emitters     

On the electrical resistivity and chemical etching of TiSi2 thin films sputtered from a composite target

The electrical resistivity of TiSi₂ thin films sputtered onto an oxidised Si substrate using a composite alloy target is studied. It is found that the as-deposited films show high resistivity. Annealing the films at an elevated temperature leads to a significant fall in the resistivity. An optimum sheet resistance of 2om tq⁻¹ is obtained after annealing at 800°C for 30 min in argon ambient. The effect of annealing temperature on resistivity is studied. The sheet resistance is also found to be affected by the magnitude of the substrate bias during film deposition. The data are given. The patterning of TiSi₂ thin films by wet chemical etching for device applications is described.     

Unidirectional Bistability in AlGaInAs Microring and Microdisk Semiconductor Lasers

We report on room-temperature continuous-wave operation and single-mode lasing of microdisk and microring lasers with radii as small as 7 mum. The waveguide sidewall roughness was minimized by an optimized fabrication process using hydrogen silsesquioxane e-beam resist and Cl ₂-CH ₃-H ₂ inductively coupled plasma etching. The devices show unidirectional bistability between the counterpropagating modes for radii larger than 30 mu m and a strong hybrid output polarization for radii smaller than 15 mum with a transverse-magnetic component of approximately 30%.     

Microfabrication of ultra-long reinforced silicon neural electrodes

The authors describe a simple dry-etch silicon microfabrication process to develop an array of electrodes with multiple recording sites suitable for neural recording applications. This new high-yield fabrication process uses commercially available ultra-thin silicon wafers as substrate material. A xenon difluoride system is used to etch the silicon substrate to form the electrode structures. The novel concept of structural reinforcement to produce elongated and reliable probe electrodes is introduced. The authors demonstrate recording silicon electrodes that can reach lengths longer than 10 mm having only 50 μm thicknesses and an 100 μm average width. This new microfabrication process illustrates a simple, cost-effective and mass-producible method for developing ultralong silicon probes for deep brain implantation and neural recording.     

Direct bonding of GaAs films on silicon circuits by epitaxial liftoff

Epitaxial liftoff has emerged as a viable technique to integrate GaAs with silicon. The technique relies on the separation of a thin epi-GaAs film from its substrate followed by direct bonding of the thin film to a silicon substrate. The silicon substrate has to meet certain planarity and smoothness conditions in order to obtain high quality bonding. Unfortunately, processed silicon IC chips do not satisfy these conditions. In this paper, we report on the results of two different planarization techniques, plasma etch back and chemical-mechanical polishing, to integrate GaAs LEDs with silicon circuits using epitaxial liftoff. 4 by 8 arrays of GaAs LEDs have been integrated with silicon driver circuits using plasma etch back. We also have lifted off areas as large as 500 mm² and bonded them on 5″ device wafers by chemical-mechanical polishing. This can be essential for mass production of optoelectronic devices based on epitaxial liftoff.     

Selectively deposited nickel film for via filling

A selective deposition process is used to fill vias in VLSI multilevel interconnection. Ni film is chosen as the via-filling material because of its compatibility with the underlying Al film. The vias are filled with a thin Pd film first and a thick Ni film. The deposited Ni film is uniform and smooth in the via regions. This film is not attacked by the plasma etch used in subsequent Al patterning; therefore, the design rule of overlapping the second metal on vias can be relaxed. The specific via resistance of this process is 4×10 ^-9Ω-cm². The via resistance increases about 30% after an exposure to 450°C for 8 h     

Modeling magnetically enhanced RIE of aluminum alloy films usingneural networks

Aluminum (Al) and its alloy films are widely used for fabricating VLSI interconnections. The discharge behavior of a magnetically enhanced reactive ion etching (MERIE) of Al(Si) has been modeled using neural networks. A 2^6-1 fractional factorial experiment was employed to characterize etch variations with RF power, pressure, magnetic field and gas mixtures of Cl₂, BCl₃, and N₂. Responses of an Al(Si) film etched in a chlorine-based plasma include etch rate, selectivity to oxide, anisotropy and bias of critical dimension (CD). The generalization accuracy of the models, measured by the root-mean squared error (RMS) on a test set, are 285 Å/min for etch rate, 5.58 for oxide selectivity, 0.08 for anisotropy, and 3.82 Å/min for CD bias. Al(Si) etch rate was found to be chlorine-dependent with significantly affected by magnetic field variations. For the other etch responses, RF power was dominant. Gas additives such as BCl₃ and N₂ were seen to have conflicting effects on etch outputs. Predicted Al(Si) etch behaviors from neural process models were in qualitative good agreement with reported experimental results     

Integration of 0/1-Level Packaged RF-MEMS Devices on MCM-D at Millimeter-Wave Frequencies

This paper reports on the development and optimization of 0/1-level packaged coplanar waveguide (CPW) lines and radio-frequency microelectromechanical systems (RF-MEMS) switches up to millimeter-wave frequencies. The 0-level package consists of an on-chip cavity obtained by flip-chip mounting a capping chip over the RF-MEMS device using BenzoCyclobutene (BCB) as the bonding and sealing material. The 0-level coplanar RF feedthroughs are implemented using BCB as the dielectric; gold stud-bumps and thermocompression are used for realizing the 1-level package. The 0-level packaged switches have been flip-chip mounted on a multilayer thin-film interconnect substrate using a high-resistivity Si carrier with embedded passives and substrate cavities. The insertion loss of a single 0/1-level transition is below -0.15 dB at 50 GHz. The measured return loss of a 0/1-level packaged 50-Omega CPW line remains better than -19 dB up to 71 GHz and better than -15 dB up to 90 GHz. It is shown that the leak rate of BCB sealed cavities depends on the BCB width, and leak rates as low as 10^-11 mbar.l/s are measured for large BCB widths (> 800 mum), dropping to 10^-8 mbar.l/s for BCB widths of around 100 mum. Depending on the bonding conditions, shear strengths as high as 150 MPa are achieved.     

Polymer residue chemical composition analysis and its effect on via contact resistance in dual damascene copper interconnects process integration

During via and trench plasma etching in dual damascene copper interconnects process integration, polymer residues and copper damage were created as by-products of the dry-etch process. The polymer residue chemical composition and copper damage were analyzed by Auger electron spectroscopy. Analysis result indicated that besides copper, carbon, oxygen, and nitrogen and trace amounts of chlorine and sulphur were also observed. The polymer residue and copper damage are the important reasons of cause higher via contact resistance and lower via yield. It could be reduced and eliminated effectively using optimized plasma etch recipe, improved polymer residue removal methods and improved pre-treatment before metal deposition and so on.     

Low open-area endpoint detection using a PCA-based T2statistic and Q statistic on optical emission spectroscopy measurements

Examines an approach for automatically identifying endpoint (the completion in etch of a thin film) during plasma etching of low open area wafers. Because many end-pointing techniques use a few manually selected wavelengths or simply time the etch, the resulting endpoint detection determination may only be valid for a very short number of runs before process drift and noise render them ineffective. Only recently have researchers begun to examine methods to automatically select and weight spectral channels for estimation and diagnosis of process behavior. This paper will explore the use of principal component analysis (PCA)-based T² formulation to filter out noisy spectral channels and characterize spectral variation of optical emission spectroscopy (OES) correlated with endpoint. This approach is applied and demonstrated for patterned contact and via etching using digital semiconductor's CMOS6 (0.35-μm) production process     

Patterning of transparent conducting oxide thin films by wet etching for a-Si:H TFT-LCDs

The patterning characteristics of the indium tin oxide (ITO) thin films having different microstructures were investigated. Several etching solutions (HC1, HBr, and their mixtures with HNO₃) were used in this study. We have found that ITO films containing a larger volume fraction of the amorphous phase show higher etch rates than those containing a larger volume fraction of the crystalline phase. Also, the crystalline ITO films have shown a very good uniformity in patterning, and following the etching no ITO residue (unetched ITO) formation has been observed. In contrast, ITO residues were found after the etching of the films containing both amorphous and crystalline phases. We have also developed a process for the fabrication of the ITO with a tapered edge profile. The taper angle can be controlled by varying the ratio of HNO₃ to the HC1 in the etching solutions. Finally, ITO films have been found to be chemically unstable in a hydrogen containing plasma environment. On the contrary, aluminum doped zinc oxide (AZO) films, having an optical transmittance and electrical resistivity comparable to ITO films, are very stable in the same hydrogen containing plasma environment. In addition, a high etch rate, no etching residue formation, and a uniform etching have been found for the AZO films, which make them suitable for a-Si:H TFT-LCD applications.     

Scalability of dry-etch processing for small unit-cell HgCdTe focal-plane arrays

A combination of mechanical experiments and fabrication of very-long-wavelength infrared (VLWIR) HgCdTe-infrared detectors has been used to investigate the interaction between various unit-cell design and dry-etch process variables on final unit-cell dimensions and detector performance. Etch rate, which determines the process time required to achieve a specified etch depth, was found to be a function of both the trench width opening used to delineate an individual detector element in a focal-plane array (FPA) and the mesa profile observed during etching. Current-voltage (I-V) probe data at 78 K demonstrated the successful fabrication of 30 μm unit-cell, VLWIR-HgCdTe diodes with mesa delineation performed by dry etching. The breakdown performance of these diodes is sensitive to trench width and dry-etch process time.     

Advantages of plasma etch modeling using neural networks overstatistical techniques

Due to the inherent complexity of the plasma etch process, approaches to modeling this critical integrated circuit fabrication step have met with varying degrees of success. Recently, a new adaptive learning approach involving neural networks has been applied to the modeling of polysilicon film growth by low-pressure chemical vapor deposition (LPCVD). In this paper, neural network modeling is applied to the removal of polysilicon films by plasma etching. The plasma etch process under investigation was previously modeled using the empirical response surface approach. However, in comparing neural network methods with the statistical techniques, it is shown that the neural network models exhibit superior accuracy and require fewer training experiments. Furthermore, the results of this study indicate that the predictive capabilities of the neural models are superior to that of their statistical counterparts for the same experimental data     

Excimer laser patterning of high-Tcsuperconducting thin films of YBCO

The patterning by excimer laser ablative etching of thin superconducting films of YBCO on MgO and fused silica substrates which were fabricated by laser sputtering is discussed. The etch rate as a function of laser fluence, wavelength, and number of pulses has been investigated. Although etched film surfaces were found to be considerably smoother than annealed films, the laser etching itself was found not to be a totally thermal process     

1-µm MOS process using anisotropic dry etching

Anisotropic and selective etching of silicon has been obtained using a planar-reactive sputter-etching system and CCl3F gas. The Si to SiO2etch-rate ratio was 5 : 1. This etch process in CCl3F was interpreted as mainly involving physical reaction as opposed to etching in SF6. The influence of reactive sputter etching on junction leakage and threshold voltage shift, in comparison with a conventional wetetch process, could not be observed in the electrical characteristics of polysilicon gate MOS devices. An all dry-etched MOS process, consisting of an anisotropic etching for Si3N4, polysilicon, SiO2, and aluminum, was applied to the fabrication of a 1-kbit static RAM with 1-µm minimum geometry. It was confirmed that this anisotropic etching technology was useful for very fine-geometry patterning and could be applied to a 1-µm MOSLSI manufacturing process.     

ICP技术在化合物半导体器件制备中的应用

介绍了ICP刻蚀工艺技术原理和在化合物半导体器件制备中的应用,包括ICP刻蚀技术中的低温等离子体的形成机理、等离子体与固体表面的相互作用等,并对影响ICP刻蚀结果的因素进行了分析.研究了不同的工艺气体配比、腔体工作压力、ICP源功率和射频源功率对刻蚀的影响,并初步得到了一种稳定、刻蚀表面清洁光滑、图形轮廓良好、均匀性较好和刻蚀速率较高的干法刻蚀工艺.     

High-density plasma etch selectivity for the III–V nitrides

High-density plasma etching has been an effective patterning technique for the group-III nitrides due to ion fluxes which are 2–4 orders of magnitude higher than more conventional reactive ion etch (RIE) systems. GaN etch rates exceeding 0.68 μm/min have been reported in Cl₂/H₂/Ar inductively coupled plasmas (ICP) at −280 V dc-bias. Under these conditions, the etch mechanism is dominated by ion bombardment energies which can induce damage and minimize etch selectivity. High selectivity etch processes are often necessary for heterostructure devices which are becoming more prominent as growth techniques improve. In this study, we will report high-density ICP etch rates and selectivities for GaN, AlN, and InN as a function of plasma chemistry, cathode rf-power, ICP-source power, and chamber pressure. GaN:AlN selectivities >8:1 were observed in a Cl₂/Ar plasma at 10 mTorr pressure, 500 W ICP-source power, and 130 W cathode rf-power, while the GaN:InN selectivity was optimized at 6.5:1 at 5 mTorr, 500 W ICP-source power, and 130 W cathode rf-power.     

微观结构对PZT薄膜反应离子刻蚀的影响

随着锫钛酸铅（PZT）薄膜在铁电微器件中的广泛应用，薄膜微图形化和刻蚀的研究也日益受到重视。研究表明在薄膜的刻蚀过程中，薄膜表面的微观结构和等离子体都对刻蚀有很大的影响。该文研究了具有不同微观结构的薄膜的反应离子刻蚀特性。分别用X-射线衍射图、原子力间力显微镜和X-射线光电子能谱对薄膜表面的微观结构、形貌及刻蚀特性进行测量。结果表明，随着薄膜最终热处理温度升高，薄膜表面越来越致密，刻蚀速率也随之降低。当薄膜处于无定形态结构时薄膜的刻蚀速率较高，最高可达13m／min。