Software reliability how it affects system reliability

This paper suggests that there is an additional measurable attribute, system “structuredness” which contributes to system reliability. It examines the effect of the structure of software on the integrity of a system. It shows how intuition fails us, when we accept a less hierarchally structured system and expect it to behave as reliably. “Structuredness”, can be used together with the system availability figure to provide a realistic measure of system integrity. The results of implementing structured programming techniques to increase software reliability are briefly discussed.     

Wafer level reliability: Process control for reliability

Wafer Level Reliability test techniques can be used to provide fast feedback process control information regarding the reliability of the product of a semiconductor process. The purpose of wafer level reliability (WLR) tests is the measurement of variation in the materials comprising the semiconductor device. They are not intended as modeling tools for the quantification of the effect of stress on these materials. As such, WLR tests must provide a repeatable stress, independent of normal process variation. The results of these tests will be a measurement of the “rate of degradation” of the basic circuit elements caused by a standard stress.     

H-MOS reliability

H-MOS is a new high-performance n-channel technology with a 1-pJ speed power product. This technology is the result of scaling MOS device dimensions. The effect of thinner oxide integrity and hot electron injection are investigated. A screening technique for thin oxides using high-voltage stressing is presented. Threshold shifts due to hot electron injection were observed to be less than 1 mV. Operating lifetest data predict a failure rate of 0.017 percent/1000 h on 4K static RAM's built on H-MOS.     

DRAM reliability

Dynamic random access memory (DRAM) reliability is investigated for future DRAMs where small geometrical devices are used together with new materials and novel process technologies. Among the several items of DRAM reliability, the most important aspect to consider for DRAM reliability is infant mortality which is caused by process-induced defects including random defects. Since the process-induced defects are strongly dependent on process technology, it is inevitable to minimize process-induced defects by developing new process technology. However, whenever new process technology is introduced, new screening techniques or methods are necessary for suppressing infant mortality. The degradation of pMOSFET due to buried-channel pMOSFET during burn-in stress and soft error rate due to α-particle and cosmic ray irradiation become concerns as device dimension shrinks. However, it cannot be limitations of DRAM reliability because pMOSFET degradation due to hot electron induced puchthrough can be suppressed by new layout of pMOSFET, and the soft error events can be overcome by soft error resistant device structure and proper material choices. From these considerations, it can be expected that the advances of DRAM technology generation not only improve the device performance but also enhance the reliability.     

VMOS reliability

Whenever a new technology such as VMOS emerges, one key element to its success is the reliability of the products manufactured in that technology. The results of a reliability study to examine the fundamental VMOS device stability, high-temperature operating life (HTOL) failure rates, and electrostatic protection are presented for the VMOS technology. Experimental data for more than five (5) million device-hours of HTOL predict a reliability failure rate of less than 0.01 percent/1000 h at 70°C for products fabricated in the VMOS technology. In addition, an electrostatic protection capability greater than 1800 V is possible with specially designed VMOS input protection devices.     

Empirical formulas and global reliability evaluation of reliability graphs

Some formulas have been reported, in terms of elements and nodes, to calculate the number of reliability graphs of identical elements in series-parallel configurations. A simple and efficient algorithm has been proposed for enumeration of spanning trees using an incidence matrix which is used for global reliability evaluation of a graph. An example demonstrates the effectiveness of the algorithm.     

Diagnostic technique for projecting gate oxide reliability and device reliability

This study presents a diagnostic technique for projecting gate oxide reliability and device reliability from the correlation among four kinds of lifetime prediction methods which are experimentally characterized by TDDB, F-N degradation, SILC and hot carrier degradation. It has been found that there exists close correlation between gate oxide degradation and device degradation. Therefore, this technique can be used to evaluate how much the process induced degradation of gate oxide effects on the device degradation.     

Sequential evaluation of terminal pair reliability in a reliability network

For a non-series-parallel reliability network, the terminal pair reliability is evaluated sequentially and the model is extended to consider the possibility of improving the reliability of a link by a parallel duplication.     

Prolog representation of reliability networks and evaluation of system reliability

The suitabilities of Prolog to represent reliability networks are discussed in this paper. The capabilities of Prolog are illustrated by relevant examples in various reliability network configurations. The network reliability has been estimated by using the recursive nature of Prolog.     

Software reliability measurement

The measurement and analysis aspects of software reliability are described with the aim of providing software engineers and managers a sense of where and how software reliability measurements can be applied to their projects. Some background for understanding software reliability measurement is provided, and activities associated with measuring and analyzing software reliability are discussed in the context of the software product life cycle. The focus is on failures and the rate at which they occur. The thrust of reliability measurement and analysis is to specify what the customer needs in terms of reliability before a software product is built, to validate that these needs are met before delivery of the product to the customer, and to make sure that the customer's needs continue to be met after delivery     

Model-based reliability analysis

Testing has typically been a key means of detecting anomalous performance and of providing a foundation for estimating reliability for weapon systems. The objective of model-based reliability analysis (MBRA) is to identify ways to capitalize on the insights gained from physical-response modeling both to supplement the information obtained from testing and to better-understand test results. Five general MBRA processes are identified which can capitalize on physical response modeling results to make both quantitative and qualitative statements about product reliability. A case study that explores 1 of these 5 processes was completed and is described in detail. It had the benefits: MBRA can be used to determine a performance baseline against which current and future test results can be compared; during the design process, MBRA can provide tradeoff studies such that development time and required test assets can be reduced; MBRA can be used to evaluate the impact of production and part changes, as well as aging degradation, if they arise during the product life cycle; and MBRA lays the foundation to evaluate anomalies that are observed in a test program. Typically it has been challenging to determine how anomalous behavior can manifest itself under different-but still valid-conditions. One can use modeling to inject hypothesized behaviors under different conditions and observe the consequences     

Memory LSI reliability

Large-scale integrated (LSI) memory circuit reliability is reviewed. Reliability of large-scale integrated memory circuits is discussed. The major physical mechanisms for failures in memory LSIs and measures to counter these failures are reviewed. Fault-tolerant techniques, divided into the spare row/column line substitution. (SLS) technique and the on-chip error-correcting code (ECC) technique, developed to overcome hard and soft failures are described. Design approaches for realizing high performance and high reliability are also discussed     

GaN HEMT reliability

This paper reviews the experimental evidence behind a new failure mechanism recently identified in GaN high-electron mobility transistors subject to electrical stress. Under high voltage, it has been found that electrically active defects are generated in the AlGaN barrier or at its surface in the vicinity of the gate edge. These defects reduce the drain current, increase the parasitic resistance and provide a path for excess gate current. There is mounting evidence for the role of the inverse piezoelectric effect in introducing mechanical stress in the AlGaN barrier layer and eventually producing these defects. The key signature of this mechanism is a sudden and non-reversible increase in the gate leakage current of several orders of magnitude. This degradation mechanism is voltage driven and characterized by a critical voltage below which degradation does not occur. This hypothesis suggests several paths to enhance the electrical reliability of GaN HEMTs which are borne out by experiments.     

A heuristic method of link reliability assignment for maximal reliability

Link reliability assignment is the problem of determining the reliability values to be assigned to the various links of a given network from a given set of link reliability values in order to achieve maximum reliability for the given network. Reliability to be maximized may be the s-t reliability or global reliability. The methods available for assigning reliability values to various links require the knowledge of the network reliability function and its several evaluations. The proposed method, which is heuristic in nature, does not require the reliability function and its evaluations; it only needs the network s-t paths (or trees for global reliability). Frequencies of occurrence of various links in paths of different cardinalities (or trees for global reliability) are found. An index, termed the importance index, which is a function of frequency of occurrence, number of paths and cardinalities of paths, is defined and determined for each link. Links are assigned reliability values in the same order as the order of importance index values. The proposed criterion has been tried on several networks. The network reliability obtained is maximal.     

Engineering reliability management

This paper reviews the history and the pertinent areas of reliability and maintainability management. A list of selective references on the subject is presented.     

要对元件可靠性说再见吗?

设计师们现在都把基础元件的可靠性不当一回事。当你使用一个电子元件时,它在规定的工作条件下发生参数值偏离到最小和最大规定值之外或出现失效的情况是很少见的。同样,设计和制造得当的印制电路板是装有大量有源器件和无源元件的可靠的长期性载体。这种满意的结果并不是偶然或侥幸发生的,而是元件工程师、材料科学家和生产专家多年的日     

Measuring software reliability

The component concepts of the term `reliability' are examined to clarify why its measurement is difficult. Two approaches to measuring the reliability of finished code are described. The first, a developer-based view, focuses on software faults; if the developer has grounds for believing that the system is relatively fault-free, then the system is assumed to be reliable. The second, a user-based view more in keeping with the standard IEEE/ANSI definition, emphasizes the functions of the system and how often they fail. The advantages of the failure-based approach are discussed, and various techniques are described. The issues that require further exploration and definition before reliability measurement becomes a straightforward for software as for hardware are identified