The TEOS oxide deposited on phosphorus in-situ/POCl3doped polysilicon with rapid thermal annealing in N2O

This work presents a TEOS oxide deposited on the phosphorus-in-situ doped polysilicon with rapid thermal N₂O annealing. The oxide exhibits good electron trapping characteristics with a charge-to-breakdown (Q_bd) up to 110 C/cm². It is due to the good polysilicon/oxide interface morphology obtained by replacing POCl₃ doping with in-situ doping and the rapid thermal annealing in N₂O. In addition, the N₂O annealing densifies the deposited oxide and incorporates nitrogen into the oxide and at the polysilicon/oxide interface, thus improving the electrical characteristics     

Thin titanium oxide films deposited by e-beam evaporation with additional rapid thermal oxidation and annealing for ISFET applications

Titanium oxide (TiO₂) has been extensively applied in the medical area due to its proved biocompatibility with human cells [1]. This work presents the characterization of titanium oxide thin films as a potential dielectric to be applied in ion sensitive field-effect transistors. The films were obtained by rapid thermal oxidation and annealing (at 300, 600, 960 and 1200 °C) of thin titanium films of different thicknesses (5 nm, 10 nm and 20 nm) deposited by e-beam evaporation on silicon wafers. These films were analyzed as-deposited and after annealing in forming gas for 25 min by Ellipsometry, Fourier Transform Infrared Spectroscopy (FTIR), Raman Spectroscopy (RAMAN), Atomic Force Microscopy (AFM), Rutherford Backscattering Spectroscopy (RBS) and Ti-K edge X-ray Absorption Near Edge Structure (XANES). Thin film thickness, roughness, surface grain sizes, refractive indexes and oxygen concentration depend on the oxidation and annealing temperature. Structural characterization showed mainly presence of the crystalline rutile phase, however, other oxides such Ti₂O₃, an interfacial SiO₂ layer between the dielectric and the substrate and the anatase crystalline phase of TiO₂ films were also identified. Electrical characteristics were obtained by means of I-V and C-V measured curves of Al/Si/TiO_x/Al capacitors. These curves showed that the films had high dielectric constants between 12 and 33, interface charge density of about 10¹⁰/cm² and leakage current density between 1 and 10⁻⁴ A/cm². Field-effect transistors were fabricated in order to analyze I_D x V_DS and log I_D × Bias curves. Early voltage value of −1629 V, R_OUT value of 215 MΩ and slope of 100 mV/dec were determined for the 20 nm TiO_x film thermally treated at 960 °C.     

Effects of rapid thermal annealing on nitrided gate oxide grown on 4H-SiC

The electrical characteristics of thermally nitrided gate oxides on n-type 4H-SiC, with and without rapid thermal annealing processes, have been investigated and compared in this paper. The effects of annealing time (isothermal annealing) and annealing temperature (isochronal annealing) on the gate oxide quality have also been systematically investigated. After rapid isothermal and isochronal annealings, there has been a significant increase in positive oxide-charge density and in oxide-breakdown time. A correlation between the density of the positive oxide charge and the oxide breakdown reliability has been established. We proposed that the improvement in the oxide-breakdown reliability, tested at electric field of 11 MV/cm, is attributed to trapping of injected electron by the positive oxide charge and not solely due to reduction of SiC-SiO₂ interface-trap density.     

Flat band voltage shift and oxide properties after rapid thermal annealing

The flat band voltage (V_fb) shift observed for MOS samples exposed to rapid thermal annealing (RTA) (N₂, 20 s, 1040°C) is examined for (1 0 0), (1 1 0) and (1 1 1) orientation-silicon substrates. Using a mercury gate C–V system, the V_fb shift can be attributed to changes in the electronic properties of the oxide layer and not polysilicon gate effects, as had previously been suggested. In addition, this work indicates that the flat band voltage shift results from a reduction of interface and fixed oxide charge due to the RTA process. The interface and oxide charge densities are related to the density of available bonds for each surface orientation, both before and after an RTA step. Based on these results, we argue that the V_fb shift following RTA is primarily due to a reduction of fixed positive charge in the oxide, and to a lesser degree, to a reduction of negative interface charge. The net effect is that the RTA step reduces the total oxide charge density.     

Silicon-to-steel bonding using rapid thermal annealing

This paper presents the rapid, low-temperature bonding between silicon and steel using the rapid thermal annealing process. Three different thin-film adhesion layer systems including silver, gold, and nickel were utilized as the intermediate bonding material to assist the eutectic Pb/Sn bonding between silicon and steel. The bonding temperature was set at 220/spl deg/C for 20 s, with a 20-s ramp-up time. Five experiments were conducted to determine the strength of the bond, including static tensile and compressive four-point bend tests, axial extension tests, tensile bending fatigue tests, and corrosion resistance tests. The test results have shown that the gold adhesion layer is the most robust, demonstrating minimal creep during fatigue tests, no delamination during the tensile or compressive four-point bend tests, and acceptable strength during the axial extension tests. Additionally, all adhesion layers have withstood four months of submersion in various high-temperature solutions and lubricants without failure. Simulations of the axial stresses and strains that developed during the four-point bend and axial extension tests were performed and showed that the presence of the silicon die provides a local reinforcement of the bond as observed in the experimental tests.     

Electrical characterization of the hafnium oxide prepared by direct sputtering of Hf in oxygen with rapid thermal annealing

Electrical characterization of the hafnium oxide (HfO₂) gate dielectric films prepared by Hf sputtering in oxygen was conducted. By measuring the current–voltage (I–V) characteristics at temperature ranging from 300 to 500 K, several abnormalities in the I–V characteristics are recorded. For temperatures below 400 K, the current–voltage characteristics in high field region can be plotted with the Fowler–Nordheim law but a stronger temperature dependence was observed. Large flatband voltage shifts in the Al/HfO₂/Si capacitor were observed. The capacitance–voltage characteristics and flatband shifts are found to depend strongly on the post-deposition annealing temperature and duration. To study the reliability against high electric field, constant voltage stressing on the samples was conducted. We found that the trap energy levels are shallow and the oxide traps can be readily filled and detrapped at a low bias voltage.     

Effect of rapid thermal annealing on pentacene-based thin-film transistors

The bottom contact pentacene-based thin-film transistor is fabricated, and it is treated by rapid thermal annealing (RTA) with the annealed temperature up to 240 °C for 2 min in the vacuum of 1.3 × 10⁻² torr. The morphology and structure for the pentacene films of OTFTs were examined by scanning electron microscopy and X-ray diffraction technique. The thin-film phase and a very small fraction of single-crystal phase were found in the as-deposited pentacene films. While the annealing temperature increases to 60 °C, the pentacene molecular ordering was significantly improved though the grain size only slightly increased. The device annealed at temperature of 120 °C has optimal electrical properties, being consistent with the experimental results of XRD. The post-annealing treatment results in the enhancement of field-effect mobility in pentacene-based thin-film transistors. The field-effect mobility increases from 0.243 cm²/V s to 0.62 cm²/V s. Besides, the threshold voltage of device shifts from −7 V to −3.88 V and the on/off current ratio increases from 4.0 × 10³ to 8.7 × 10³.     

Comparison between CVD and thermal oxide dielectric integrity

Low-pressure chemical vapor deposited (CVD) oxide and thermal oxide of identical thickness (360 A) are compared. CVD oxide exhibits much lower incidence of breakdown at the electric fields below 8 MV/cm, in agreement with the notion that the breakdown is largely due to the incorporation of impurities in the silicon substrate into the oxide during thermal oxidation. Furthermore, CVD oxide shows identical IV characteristics as thermal oxide and significantly lower rates of electron and hole trapping. Based on these results, CVD oxide may be an intriguing candidate for thin dielectric applications.     

Direct silicidation of Co on Si by rapid thermal annealing

Rapid thermal annealing is used to form cobalt silicide directly on unimplanted as well as B-, As-, and P-implanted wafers. The films are characterized by sheet resistance, X-ray diffraction, SEM, TEM, SIMS, and contact resistance measurements. The direct silicidation of Co on Si by rapid thermal annealing yields smooth low-resistivity films with minimal dopant redistribution.     

Ultra high temperature rapid thermal annealing of GaN

All of the major acceptor (Mg, C, Be) and donor (Si, S, Se and Te) dopants have been implanted into GaN films grown on Al₂O₃ substrates. Annealing was performed at 1100–1500°C, using AlN encapsulation. Activation percentages of ≥90% were obtained for Si⁺ implantation annealed at 1400°C, while higher temperatures led to a decrease in both carrier concentration and electron mobility. No measurable redistribution of any of the implanted dopants was observed at 1450°C.     

High-sensitivity porous silicon photodetectors fabricated throughrapid thermal oxidation and rapid thermal annealing

The sensitivity of a porous silicon Schottky barrier photodetector is much improved through rapid thermal oxidation and rapid thermal annealing processes. Under our optimum preparation conditions, photocurrent can reach about 21 mA (under 22.4 mW/cm² tungsten lamp illumination) and dark current is about 5.4 μA (at reverse bias of 10 V). The quantum efficiencies are about 90% at wavelengths shorter than 750 nm and 80%-70% in the wavelength range 750-1050 nm     

Effect of rapid thermal annealing on deep level defects in the Si-doped GaN

Rapid thermal annealing effects on deep level defects in the n-type GaN layer grown by metalorganic chemical vapor deposition (MOCVD) have been characterized using deep level transient spectroscopy (DLTS) technique. The samples were first characterized by current-voltage (I-V) and capacitance-voltage (C-V) measurements. The measurements showed that the barrier height of the as-grown sample to be 0.74 eV (I-V) and 0.95 eV (C-V) respectively. However, the Schottky barrier height of the sample annealed at 800 °C increased to 0.84 eV (I-V) and 0.99 eV (C-V) respectively in nitrogen atmosphere for 1 min. Further, it was observed that the Schottky barrier height slightly decreased after annealing at 900 °C. DLTS results showed that the two deep levels are identified in as-grown sample (E1 and E3), which have activation energies of 0.19 ± 0.01 eV and 0.80 ± 0.01 eV with capture cross-sections 2.06 × 10⁻¹⁷ cm² and 7.68 × 10⁻¹⁸ cm², which can be related to point defects. After annealing at 700 °C, the appearance of one new peak (E2) at activation energy of 0.49 ± 0.02 eV with capture-cross section σ_n = 5.43 × 10⁻¹⁷ cm², suggest that E2 level is most probably associated with the nitrogen antisites. Thermal annealing at 800 °C caused the E1 and E3 levels to be annealed out, which suggest that they are most probably associated with the point defects. After annealing at 900 °C the same (E1 and E3) deep levels are identified, which were identified in as-grown n-GaN layer.     

The effects of point defects on the electrical activation ofSi-implanted GaAs during rapid thermal annealing

The effects of point defects on the electrical activation of Si-implanted GaAs during rapid thermal annealing were investigated using slow positron beam, cross-sectional transmission electron microscopy, and Hall measurements. The increase of the Ga vacancy concentration in the GaAs substrate induced by the SiO₂ cap layer on the substrate during annealing was observed to decrease the activation efficiency and the number of extrinsic stacking faults via the recombination of interstitials with vacancies. It was found that the efficiency of the carrier creation is not dependent upon the Ga vacancy concentration during the rapid thermal annealing of Si-implanted GaAs. Hence, it is proposed that the electrical activation of Si-implanted GaAs is not due to implantation-induced vacancies but to the self-exchange of interstitial Si atoms with the host Ga substitutional atoms     

Manufacturability issues related to transient thermal annealing oftitanium silicide films in a rapid thermal processor

Transient thermal annealing of sputtered titanium films in a rapid thermal processor (RTP) is critically evaluated from the viewpoint of manufacturability-related considerations. In particular, the thin-film properties of the resulting titanium silicide on polysilicon and silicon, process uniformity, and unit step wafer yield of high-density scaled device structures are investigated. The experimental results suggest that RTP silicides show good thin-film properties for manufacturability on planar wafer surfaces. Transient thermal gradients in an RTP system are shown to cause substantial variations in the electrical and structural properties of TiSi_x films formed on silicon substrates with varying substrate thicknesses. Closed-loop temperature control in an RTP reactor provided stoichiometrically identical TiSi_x films with negligible substrate thickness dependence. The experimental results also suggest that careful wafer surface temperature control is needed when forming titanium silicide films on nonplanar silicon surfaces, silicon trenches, and process monitor wafers without predetermined wafer thicknesses     

The behavior of Ni/Au contacts under rapid thermal annealing in GaN device structures

The effect of rapid thermal annealing (RTA) on Ni/Au contacts on P-type GaN was investigated in terms of surface morphology and diffusion depth of metallic species. Ni/Au contacts were evaporated on the P-type 0.5 μm thick top layer of a GaN P/N homojunction. Optical micrographs revealed that the contact morphology degrades when annealed above 800°C for 1 min. At the same time, both Ni and Au atoms strongly diffuse in the P-type layer and even can reach the junction for a 1 min long annealing at 900°C, therefore making the junction structure unoperable. This behavior was evidenced using the Auger voltage contrast (AVC) technique.     

Effect of radiation shield angle on temperature and stress profilesduring rapid thermal annealing

The effects of radiation shield angle and oven-temperature ramping rates on the temperature and thermal stress profiles in a gallium arsenide wafer undergoing rapid thermal annealing are studied. The numerical model of the heat transfer in a cylindrical oven considers conduction in the wafer radiative heat transfer from all oven and shield surfaces to the wafer. All simulations show that at some location in the wafer the induced thermal stress exceeds the critical stress. These results indicate that at high temperatures (T>750°C) it is very difficult to maintain a sufficiently flat temperature profile such that the induced thermal stress is maintained below the critical stress throughout the wafer. Possible ways to minimize the induced thermal stress during the annealing process using a radiation shield and specific oven-temperature ramping rates are discussed     

Patterning by rapid thermal annealing of GaAs layers grown on diluted nitride QWs

The structural characterization of hole patterns on GaAs cap layers grown on GaInNAs quantum wells (QWs) created by rapid thermal annealing is shown in this work. The effect of annealing temperature on the hole size, as well as the impact of the ion density present during the growth of the QW on the formation of this hole pattern, is presented. Structural (atomic force, scanning electron and transmission electron microscopy) and optical characterization (cathodoluminescence) of the samples is presented. The structure of the planes forming the walls and base of these holes is proposed.     

Effects of rapid thermal annealing on ohmic contact of AIGaN/GaN HEMTs

Ohmic contacts with Ti/Al/Ti/Au source and drain electrodes on A1GaN/GaN high electron mobility transistors （HEMTs） were fabricated and subjected to rapid thermal annealing （RTA） in flowing N2. The wafer was divided into 5 parts and three of them were annealed for 30 s at 700, 750, and 800 ℃, respectively, the others were annealed at 750 ℃ for 25 and 40 s. Due to the RTA, a change from Schottky contact to Ohmic contact has been obtained between the electrode layer and the A1GaN/GaN heterojunction layer. We have achieved a low specific contact resistance of 7.41 × 10-6Ω cm2 and contact resistance of 0.54 Ω.mm measured by transmission line mode （TLM）, and good surface morphology and edge acuity are also desirable by annealing at 750 ℃ for 30 s. The experiments also indicate that the performance of ohmic contact is first improved, then it reaches a peak, finally degrading with annealing temperature or annealing time rising.     

基于锌扩散的InGaAs/InP平面型红外探测器快速热退火研究

系统研究了快速热退火对锌扩散的In_0.53Ga_0.47As/InP PIN探测器的影响。利用电化学电容电压和二次离子质谱技术分析了退火前后Zn和净受主的浓度分布,结果表明退火过程会影响杂质浓度,但不影响扩散深度。制备了不同退火条件的In_0.53Ga_0.47As/InP PIN探测器。器件测试反映,未退火的探测器在260~300K具有更低的器件电容和更高的激活能。通过暗电流成分拟合对器件暗电流机制进行分析,未退火器件表现出更低的肖克利-里德-霍尔产生复合电流和扩散电流,因而室温下未退火器件具有更高的峰值探测率。为了制备高性能低掺杂吸收层结构的平面型InGaAs探测器,快速热退火是不必要的工艺。