250 W HVHBT Doherty With 57% WCDMA Efficiency Linearized to ${-}$55 dBc for 2c11 6.5 dB PAR

A two-way symmetrical Doherty amplifier exhibiting 250 W saturated power has been developed using high-voltage HBT (HVHBT) GaAs technology biased at 28 V on the collector. Greater than 57% collector efficiency at 50 W (47 dBm) average output power has been demonstrated while achieving -55 dBc linearized ACPR at 5 MHz offset using a two-carrier-side-by-side WCDMA input signal with 6.5 dB PAR measured at 0.01% probability on the CCDF. In addition, a two-stage HVHBT lineup exhibiting 450 W (56.5 dBm) peak power has been demonstrated. The output stage consists of a pair of 250 W two-way symmetrical Doherty amplifiers power combined using a low-loss branchline combiner and driven by a single-ended 100 W class AB high-efficiency amplifier. The lineup demonstrated 44% PAE at 100 W (50 dBm) average output power with 25 dB lineup gain while achieving - 55 dBc linearized ACPR at 5 MHz offset using a two-carrier-side-by-side WCDMA input signal with 6.5 dB PAR measured at 0.01% probability on the CCDF. The lineup exhibits 400 W (56 dBm) PldB at 60% PAE CW, with 45% PAE at 6 dB backoff.     

Highly linear three-way Doherty amplifier with uneven power drive for repeater system

We have demonstrated a high linear three-way Doherty amplifier by applying uneven power drive and optimizing the peaking biases and load impedances. The amplifier has been implemented at 2.14GHz using 190-W peak envelope power laterally diffused metal-oxide-semiconductor field-effect transistors. For comparison, a class AB biased amplifier is tested as it's counterpart. The two-tone signal and forward-link wideband code-division multiple access (WCDMA) signal have been selected as test signals. At 42dBm (12.5-dB backed-off output power), there are large improvements in the third- and fifth-order intermodulation distortions. For the forward-link four-carrier WCDMA signal, the adjacent channel leakage ratio (ACLR) performances at 5-MHz and 10-MHz offsets are -52.5dBc and -53.4dBc, respectively, and satisfy the generally medium high power amplifier linearity target without using any other linearization circuits. In comparison with the class AB amplifier, the three-way Doherty amplifier with uneven power drive has 9.8-dB lower ACLR at 5-MHz offset while maintaining a comparable drain efficiency of 10.2%.     

A microwave Doherty amplifier employing envelope tracking technique for high efficiency and linearity

In this letter, we demonstrate a microwave Doherty amplifier employing an input signal envelope tracking technique. In the amplifier, the gate bias of the peaking amplifier is controlled according to the magnitude of the envelope. A 2.14-GHz Doherty amplifier is implemented using 4-W PEP LDMOSFETs, and an adaptive controlled gate bias circuit is constructed and the control shape is optimized experimentally. The performance of the microwave Doherty amplifier is compared with that of a class AB amplifier using one-tone, two-tone, and forward-link wideband code-division multiple access (WCDMA) signals. For a forward-link WCDMA signal, the measured power added efficiency (PAE) of the microwave Doherty amplifier is 39.4% at -30 dBc adjacent channel leakage ratio (ACLR), while that of the comparable class AB amplifier is 24.2% at the same ACLR level.     

Efficiency enhancement for power amplifiers using dynamic bias switching technique

A dynamic bias switching technique is presented which discretely switches supply voltages according to the signal envelope level. For the detected envelope signals which ate lower than an appropriate threshold, this technique dynamically switches the transistor's drain bias to a significantly lower voltage. For verification, a dynamic bias switching system, applied to a class-AB power amplifier for the 859 MHz band, was implemented. Using a down-link wideband code division multiple access (WCDMA) signal, improved output power of 0.5 dB from 30.5 to 31 dBm, and improved PAE of 8.1% points from 27.4 to 35.5% wete achieved at a given ACLR level of -30 dBc compared to the conventional single-supplied class-AB amplifier.     

A New Wideband Distributed Doherty Amplifier for WCDMA Repeater Applications

A new wideband distributed Doherty amplifier (WDDA) for wideband code division multiple access (WCDMA) repeater applications is reported. The distributed structure provides wideband performance while not needing an N-way splitter and combiner. The two-stage Doherty amplifiers achieve high gain and high efficiency. Also, the linearity of the WDDA is improved by the post-distortion using gate bias optimization of the Doherty amplifiers. For verification, the proposed WDDA is implemented using GaN HEMTs and tested with a one-carrier WCDMA signal at 2.14 GHz. From the measured results at an average output power of 36 dBm (10 dB back-off power), the WDDA shows an adjacent channel leakage ratio (ACLR) of - 45 dBc at plusmn 5 MHz offset with a total gain over 24 dB and a total power-added efficiency over 15% over a 160 MHz bandwidth.     

Modeling and Design of RF Amplifiers for Envelope Tracking WCDMA Base-Station Applications

Wideband code division multiple access (WCDMA) base-station RF amplifiers using a variety of device technologies including GaN field-effect transistors (FETs), Si LDMOS, and GaAs high-voltage heterojunction bipolar transistors (HVHBTs) are modeled, optimized, and compared for use in wideband envelope tracking (ET) system. A quasi-static approach is employed to effectively model the supply-modulated RF amplifiers, and thus facilitate the design optimization process. A new design methodology for ET RF amplifiers is introduced including identification of optimum fundamental and harmonic terminations. The fundamental and harmonic impedances have been successfully optimized for various RF devices and good agreement has been achieved between the simulation and measurement results. Among the modeled and measured ET RF amplifiers, a GaAs HVHBT exhibits the best overall efficiency of 60% with an average output power of 33 W and a gain of 10 dB for a WCDMA signal with 3.84-MHz bandwidth and 7.7-dB peak-to-average power ratio, while meeting all linearity requirements of the WCDMA standard. Desirable device characteristics for optimum ET operation are also discussed.     

一种温度不敏感的高线性功率放大器

设计了一种温度不灵敏的高线性度的射频功率放大器芯片,采用新颖的带温度反馈环路的有源片上自适应偏置电路,该电路降低了温度引起的放大器集电极直流电流分量的变化量,补偿了由温度变化而引起的性能偏差,进而有效提高了放大器的线性度。基于这个温度不灵敏的偏置结构采用InGaP/GaAs HBT工艺设计了一个工作在2110~2170 MHz频段的功率放大器。测试结果表明,该功放在工作频段内的增益大于等于35.3 dB;在中心频率2140 MHz处,1 dB功率压缩点大于33 dBm,功率附加效率在输出功率24.5 dBm时为18%;使用LTE_FDD调制信号,获得邻信道功率比为-47 dBc。在环境温度为-40℃、+25℃和+80℃条件下,功放的增益平坦度较好,增益变化量小于1.5 dB,输出级集电极电流基本不变,有效降低了功放对温度的敏感性。     

An analog/digital pre-distorter using particle swarm optimization for RF power amplifiers

In this paper, a novel pre-distorter is presented using the particle swarm optimization (PSO) for an RF power amplifier linearization has been presented. We used the PSO in order to design of an efficient pre-distorter for the linearization of the output of an RF power amplifier by using the output data of the proposed power amplifier. The PSO is implemented to estimate and optimize the coefficient parameters of the work function in the proposed pre-distorter block diagram. The proposed method using PSO is most efficient because this approach is independent of the output of the power amplifier. The proposed method has been simulated with two-tone input signal and output power spectrum has been compared, where the obtained adjacent channel leakage ration (ACLR) is better than 50 dBc for both channels. Therefore, a quite significant improvement in linearity is achieved.     

High-Efficiency Envelope-Tracking W-CDMA Base-Station Amplifier Using GaN HFETs

A high-efficiency wideband code-division multiple-access (W-CDMA) base-station amplifier is presented using high-performance GaN heterostructure field-effect transistors to achieve high gain and efficiency with good linearity. For high efficiency, class J/E operation was employed, which can attain up to 80% efficiency over a wide range of input powers and power supply voltages. For nonconstant envelope input, the average efficiency is further increased by employing the envelope-tracking architecture using a wide-bandwidth high-efficiency envelope amplifier. The linearity of overall system is enhanced by digital pre-distortion. The measured average power-added efficiency of the amplifier is as high as 50.7% for a W-CDMA modulated signal with peak-to-average power ratio of 7.67 dB at an average output power of 37.2 W and gain of 10.0 dB. We believe that this corresponds to the best efficiency performance among reported base-station power amplifiers for W-CDMA. The measured error vector magnitude is as low as 1.74% with adjacent channel leakage ratio of -51.0 dBc at an offset frequency of 5 MHz     

A 60-W Multicarrier WCDMA Power Amplifier Using an RF Predistorter

In this brief, we present a 60-W power amplifier that is linearized using an RF predistorter for multicarrier wideband code-division multiple-access (WCDMA) applications. The proposed RF predistorter is fully composed of RF or analog circuits, and it has a moderate memory effect compensation capability using a delayed third-order intermodulation (IM3) component path. It also includes the IM5 generation circuits and a compact IM3 generator that is capable of autocanceling for the fundamental component. The proposed RF predistorter was implemented and applied to a 60-W high-power WCDMA amplifier. For a four-carrier downlink WCDMA signal, the RF predistorter improved the adjacent channel leakage power ratio at a 5-MHz offset by 6.19 dB at an average output power of 48 dBm. The total efficiency of the system is as high as 13.6% at the same output power level. At an output power level of 60 W, the linearized power amplifier complies with the linearity specification of the WCDMA system.     

Analysis of a Fully Matched Saturated Doherty Amplifier With Excellent Efficiency

A saturated Doherty amplifier based on class-F amplifiers is analyzed in terms of its load modulation behavior, efficiency, and linearity. Simulations included the amplitude ratio and phase difference between the fundamental and third harmonic voltages, the current/voltage waveforms, load lines, and the third-order intermodulation amplitudes/phases of the carrier and peaking amplifiers. The saturated doherty power amplifier was implemented using two Eudyna EGN010MK GaN HEMTs with a 10-W peak envelope power. For a 2.14-GHz forward-fink wideband code-division multiple-access signal, the doherty amplifier delivers an excellent efficiency of 52.4% with an acceptable linearity of -28.3 dBc at an average output power of 36 dBm. Moreover, the amplifier can provide the high linearity performance of -50 dBc using the digital feedback predistortion technique.     

Optimum design of a predistortion RF power amplifier for multicarrier WCDMA applications

This paper provides a design guide for optimum design of an RF power amplifier with a predistortion linearizer. For a two-tone signal, three performance degradation factors, higher order terms, amplitude, and phase mismatches are analyzed quantitatively. The results are implemented to the design of optimized predistortion power amplifier for a WCDMA signal application. For the experiments, a 2.4-GHz class-AB power amplifier is fabricated using an LDMOSFET with a 30-W peak envelope power. A simple third-order predistorter is used to measure the relative phases of the harmonics, as well as to linearize the amplifier. The performance of the optimized predistortion power amplifier is excellent for an IS-95 code-division-multiple-access signal. Finally, a method for reducing the memory effects of the amplifier is devised to get a good cancellation performance for a wide-band signal, and the performance degradation caused by the memory effects is analyzed. For a forward-link four-carrier WCDMA signal, the predistortion power amplifier delivers an adjacent channel leakage ratio of -46 dBc at a 4-W average output power with a cancellation of 13.4 dB.     

逆F类高效氮化镓Doherty射频功率放大器设计*

逆F 类功放在接近饱和区工作时效率很高,将其与Doherty 功放结构相结合,可以实现一种在大功率回退的情况下仍然具有很高效率的射频功率放大器。本文设计了一款基于GaN HEMT 晶体管的高效率的逆F 类Doherty 功率放大器,工作频带为910MHz-950MHz。单音信号测试结果显示,在930MHz 处,功放回退7.5dB 后漏极效率仍高达64.2%。使用3 载波WCDMA信号作为测试信号,利用数字预失真技术进行线性化后,功放输出信号的上下边带邻信道功率比(ACPR)分别为-35.39dBc 和-35.9dBc。     

一种电调Doherty功率放大器

提出了一种全新的电调Doherty移动基站功率放大器。该Doherty放大器的载波放大器和峰值放大器的驱动功率分配比及输出合成相位实现了电可调,从而保证了Doherty功率放大器的最佳驱动功率分配比,以及最佳的输出合成相位,同时结合内部线性化技术以实现Doherty功率放大器的最优性能。为保证功率放大器性能的稳定,设计了一种用于Doherty功率放大器的恒静态偏置电路,在-25℃～+50℃的高低温实验中使放大器偏置电流的波动小于5%。功放的工作频率为870～890MHz,增益大于58dB。在CDMA2000信号测试下,输出功率为50.06dBm时,其ACLR(邻道泄漏功率比)小于-47.5dBc,整机效率达42.3%(含驱动级)。     

Linearised HBT MMIC power amplifier with partially RF coupled active bias circuit for W-CDMA portable terminals applications

A highly linear MMIC power amplifier for wideband code-division multiple-access (W-CDMA) portable terminals has been devised and implemented with a new integrated on-chip lineariser. The proposed lineariser, consisting of an InGaP/GaAs heterojunction bipolar transistor (HBT) active bias circuit partially coupled to RF input power together with a feedback capacitor, effectively improves gain compression with little insertion power loss and no additional die area. The optimised lineariser improves maximum output power (P1 dB) by 2 dB and adjacent channel leakage power ratio (ACLR) by 4 dB, and the implemented HBT MMIC power amplifier exhibits a P1 dB of 30 dBm, a power gain of 30 dB, a power added efficiency of 42% at the maximum output power under an operation voltage of 3.4 V, and an ACLR of -34 dBc at 27 dBm of output power.     

基于ADS平台不对称Doherty功率放大器的仿真设计

为在高线性的前提下提高WCDMA基站系统中功率放大器的效率,仿真设计了一款工作于2.14 GHz频段不对称功率驱动的Doherty功率放大器。基于ADS平台,采用MRF6S21140H LDMOS晶体管,通过优化载波放大器和峰值放大器的栅极偏置电压改善三阶互调失真(IMD3),同时通过调节输入功率分配比例改善由于峰值放大器对载波放大器牵引不足导致的失配问题,从而改善不对称Doherty功率放大器的输出性能。仿真结果表明,当载波放大器的栅极偏置电压为2.84 V,峰值放大器的栅极偏置电压为0.85 V并且输入功率比例为1:2.3,输出功率为44 dBm时其功率附加效率(PAE)为24.21%,IMD3为-44.46 dBc,和传统AB类平衡功率放大器相比PAE提高了8.58%,IMD3改善了6.98 dBc。     

A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth

This paper presents a CMOS RF power amplifier that employs a digital polar architecture to improve the overall power efficiency when amplifying signals with high linearity requirements. The power amplifier comprises 64 parallel RF amplifiers that are driven by a constant envelope RF phase-modulated signal. The unit amplifiers are digitally activated by a 6-bit envelope code to construct a non-constant envelope RF output, thereby performing a digital-to-RF conversion. In order to suppress the spectral images resulting from the discrete-time to continuous-time conversion of the envelope, the use of oversampling and four-fold linear interpolation is explored. An experimental prototype of the polar amplifier has been integrated in a 0.18- mum CMOS technology, occupies a total die area of 1.8 mm² , operates at a 1.6-GHz carrier frequency with a channel bandwidth of 20 MHz. For an OFDM signal, it achieves a power-added efficiency of 6.7% with an EVM of - 26.8 dB while delivering 13.6 dBm of linear output power and drawing 145 mA from a 1.7-V supply.     

A Transmitter Architecture Based on Delta–Sigma Modulation and Switch-Mode Power Amplification

This brief presents a method of deploying RF switch-mode power amplification for varying envelope signals. Thereby the power amplifier can be operated as a switch with a high power efficiency as the result. The key idea is to transmit either a full RF period or none at all in such a way that the correct modulated RF signal is obtained after filtering. This is accomplished in a novel configuration of a low-pass DeltaSigma modulator using a phase modulated clock combined with a simple AND-gate. The designed modulator is easy to implement, displays very good linearity and offers time domain signals that promote the power efficiency of the power amplifier. The working principle is described through theory and simulations, and validation is done via measurements on a prototype of the modulator. Measurements on the prototype show that the presented modulator modulates a UMTS signal with more than 10-dB margin to the spectrum mask and EVM below 0.85% RMS (req<17.5%). Delta-sigma, power amplifier (PA), RF, switch mode, transmitter architecture, varying envelope.     

A capacitance-compensation technique for improved linearity in CMOS class-AB power amplifiers

A nonlinear capacitance-compensation technique is developed to help improve the linearity of CMOS class-AB power amplifiers. The method involves placing a PMOS device alongside the NMOS device that works as the amplifying unit, such that the overall capacitance seen at the amplifier input is a constant, thus improving linearity. The technique is developed with the help of computer simulations and Volterra analysis. A prototype two-stage amplifier employing the scheme is fabricated using a 0.5-/spl mu/m CMOS process, and the measurements show that an improvement of approximately 8 dB in both two-tone intermodulation distortion (IM3) and adjacent-channel leakage power (ACP1) is obtained for a wide range of output power. The linearized amplifier exhibits an ACP1 of -35 dBc at the designed output power of 24 dBm, with a power-added efficiency of 29% and a gain of 23.9 dB, demonstrating the potential utility of the design approach for 3GPP WCDMA applications.     

A highly linear and efficient differential CMOS power amplifier with harmonic control

A 2.45 GHz fully differential CMOS power amplifier (PA) with high efficiency and linearity is presented. For this work, a 0.18-/spl mu/m standard CMOS process with Cu-metal is employed and all components of the two-stage circuit except an output transformer and a few bond wires are integrated into one chip. To improve the linearity, an optimum gate bias is applied for the cancellation of the nonlinear harmonic generated by g/sub m3/ and a new harmonic termination technique at the common source node is adopted along with normal harmonic termination at the drain. The harmonic termination at the source effectively suppresses the second harmonic generated from the input and output. The amplifier delivers a 20.5dBm of P/sub 1dB/ with 17.5 dB of power gain and 37% of power-added efficiency (PAE). Linearity measurements from a two-tone test show that the power amplifier with the second harmonic termination improves the IMD3 and IMD5 over the amplifier without the harmonic termination by maximally 6 dB and 7 dB, respectively. Furthermore, the linearity improvements appear over a wide range of the power levels and the linearity is maintained under -45 dBc of IMD3 and -57dBc of IMD5 when the output power is backed off by more than 5dB from P/sub 1dB/. From the OFDM signal test, the second harmonic termination improves the error vector magnitude (EVM) by over 40% for an output power level satisfying the 4.6% EVM specification.