Enhanced CAD model for gate leakage current in heterostructurefield effect transistors

A simple and accurate circuit model for Heterostructure Field Effect Transistors (HFETs) is proposed to simulate both the gate and the drain current characteristics accounting for hot-electron effects on gate current and the effect of the gate current on the channel current. An analytical equation that describes the effective electron temperature is developed in a simple form. This equation is suitable for implementation in circuit simulators. The model describes both the drain and gate currents at high gate bias voltages. It has been implemented in our circuit simulator AIM-Spice, and good agreement between simulated and measured results is achieved for enhancement-mode HFETs fabricated in different laboratories. The proposed equivalent circuit and model equations are applicable to other compound semiconductor FETs, i.e., GaAs MESFETs     

Empirical modeling of LF gate noise in GaAs DCFET in impactionization regime

The evolution of the 1/f gate noise in GaAs DCFET has been analyzed in the impact ionization regime. As the drain bias Vd is raised, a steep increase of the 1/f gate current noise is observed in correlation with the triggering of the impact ionization mechanism. A novel and empirical model of the 1/f low frequency gate current noise S _ig measured in the impact ionization regime is proposed. The following relation fits it with an exponential law: S_ig=E exp (-F/Vd) (1/f), which is similar to the well-known dependence of the impact ionization rate α on the drain bias     

A BSIM3-based flat-band voltage perturbation model for RTS and 1/fnoise

Recently, a new random telegraph signal (RTS) noise model for the drain current fluctuations (ΔI_d) associated with single-carrier trapping and detrapping has been developed from a flat-hand voltage perturbation (ΔV_fb) of the BSIM3 current-voltage (I-V) model (Martin et al., 1997). The model's accuracy in predicting the gate bias and geometry dependence of RTS magnitudes has been verified and summarized. In this letter, the perturbation model has been extended to yield a new formulation for the scattering coefficient (α) which predicts the magnitude and bias dependence of 1/f noise without fitting parameters. The absence of fitting parameters allows for a direct determination of the oxide trap density (N_t(E_fn)) from 1/f noise measurements. Results suggest that the BSIM3-based model accurately predicts the bias and geometry dependence of 1/f noise, that N₂O annealing may significantly increase the oxide trap density at strong inversion and that the bias dependence of N_t(E_fn) contains most of the 1/f noise dependence upon V_g     

Random telegraph noise and leakage current in smart power technology DMOS devices

Random telegraph signal (RTS) noise, analyzed in time and frequency domains, and leakage current are studied in smart power technology double-diffused metal oxide semiconductor (DMOS) field effect transistors. The RTS noise is strongly correlated with the presence of an excess leakage current in the device. The observed drain current (gate bias) dependencies of relative (absolute) RTS amplitude and gate voltage dependence of RTS mean pulse widths suggest that the RTS noise sources are located under the gate and in the drain-body region. A model, where the multicell DMOS structure is considered as parallel connection of submicron MOSFETs, is proposed to account for the results.     

An analytical drain current model for dual material engineered cylindrical/surrounded gate MOSFET

In this paper, a drain current model incorporating drain-induced barrier lowering (DIBL) has been developed for Dual Material gate Cylindrical/Surrounding gate MOSFET (DMG CGT/SGT MOSFET) and the expressions for transconductance and drain conductance have been obtained. It is shown that DMG design leads to drain current enhancement and reduced output conductance. The effectiveness of DMG design was scrutinized by comparing with single metal gate (SMG) CGT/SGT MOSFET. Moreover, the effect of technology parameters variations workfunction difference has also been presented in terms of gate bias, drain bias, transconductance and drain conductance. Results reveal that the DMG SGT/CGT devices offer superior characteristics as compared to single material gate CGT/SGT devices. A good agreement between modeled and simulated results has also been obtained thus providing the validity of proposed model.     

Analytical bias dependent noise model for InP HEMT's

A practical device model for both high frequency small signal and noise behavior of InP-HEMT's depending on both gate and drain voltage has been developed. The model is based on the two-piece linear approximation using charge control and saturation velocity models. Combining large signal model and analytical expressions for the noise source parameter P, R, and C, an analytical bias-dependent noise model can be obtained. For implementation into high frequency simulation software, the exact calculated bias dependence was mathematically fitted by elementary functions. It could be shown that lowest noise is observed when the drain current for maximum gain is reduced to a third while the drain voltage is reduced to the start of the saturation region V_ds =0.6 V. Modeling scaling effects of the noise behavior shows that lowest noise is observed for a gate width of 1×40 μm. Multi-finger layouts are preferable for gate widths above 70 μm. Furthermore it is shown, that the optimum width of each finger decreases with the number of fingers     

Current-voltage characteristics of thin-film SOI MOSFET's in strong inversion

A simple analytic model for the steady-state current-voltage characteristics of strongly inverted silicon-on-insulator (SOI) MOSFET's is developed. The model, simplified by a key approximation that the inversion charge density is described well by a linear function of the Surface potential, clearly shows the dependence of the drain current on the device parameters and on the terminal voltages, including the back-gate (substrate) bias. The analysis is supported by measurements of current-voltage characteristics of thin-film (laser-recrystallized) SOI MOSFET's. The dependence of carrier mobility on the terminal voltages, especially the back-gate bias, is analyzed and shown to underlie discrepancies between the theoretical (constant mobility) and experimental results at high gate voltages. The mobility dependence on the back-gate bias enhances the strong influence of the back gate on the drain current, especially when the device is saturated.     

Optimizing the match in weakly inverted MOSFET's by gated lateralbipolar action

The on-chip n-type MOSFET current mirror circuit with different drawn gate widths and lengths has been fabricated, and has been characterized across the wafer with back gate slightly forward biased. The weakly inverted MOSFET device with a small back-gate forward bias represents equivalently the high-gain gated lateral bipolar transistor in low-level injection. Experimental results have exhibited a substantial improvement in the match of the drain current in weak inversion due to action of the gated lateral bipolar transistor, especially for the small size devices. The extensively measured mismatch of the weak inversion drain current has been successfully reproduced by an analytic statistical model with back-gate forward bias and device size both as input parameters. The experimentally extracted variations in process parameters such as the flat-band voltage and the body effect coefficient each have been found to follow the inverse square root of the device area. The mismatch model thus can serve as a quantitative design tool, and has been used to optimize the trade-off between the device area and the match with the forward back-gate bias as a parameter     

A surface potential-based compact model of n-MOSFET gate-tunneling current

Aggressive scaling of the gate-oxide thickness has made gate-tunneling current an essential aspect of MOSFET modeling. This work presents a novel physics-based compact model of gate current in the n-MOSFET. A simplified version of the Esaki-Tsu formula is developed to calculate the tunneling current density, in which the original integral is approximated to retain the essential physics without sacrificing computational efficiency required in a compact model. The proposed model is surface potential-based in both the channel and source/drain overlap regions. The channel component of the gate current is physically partitioned into the source and drain parts using a symmetrically linearized version of the charge-sheet model. The partition is implemented in analytical form and accounts for the drain bias dependence of the channel component. A small number of adjustable parameters is sufficient to reproduce the experimentally observed bias and geometry dependence of the gate current for several advanced processes.     

AlGaN/GaN高电子迁移率晶体管大信号I-V特性模型

对非线性电流源Ids(Vgs,Vds)的准确描述是Al GaN/GaN HEMT大信号模型的最重要部分之一.Materka模型考虑了夹断电压与Vds的关系,其模型参数只有三个,但是Ids与Vgs的平方关系不符合实际,计算结果与测量数据有误差.我们在考虑了栅电压与漏电流的关系及不同栅压区漏电流随漏电压斜率改变的基础上,提出了改进的高电子迁移率晶体管(HEMT)的直流特性模型.采用这个模型,计算了Al GaN/GaN HEMT器件的大信号I-V特性,并与实际测量数据进行了比较.实验结果表明改进的模型更精确,Ids与Vgs的呈2.5次方的指数关系.     

A model for the drain voltage and gate voltage dependence of the current fluctuation spectrum of unsaturated JFET's

From the standpoint of the number fluctuation model of the generation-recombination noise and 1/fnoise, a model for the drain and gate voltage dependences of the current fluctuation spectrum of an unsaturated JFET ot MESFET can be established. The derived formula can explain the various experimental results, especially the square-law dependence of the drain voltage throughout almost all of the unsaturated region, and the increasing characteristic of the current fluctuation spectrum with increasing reverse gate voltage. It can also explain the dependence of drain current fluctuation on the device geometric parameters, and finally, it points out that Hooge's expression for the spectral intensity of the current fluctuation can be valid only in the linear region of the device.     

Photosensitivity Analysis of Low-Temperature Poly-Si Thin-Film Transistor Based on the Unit-Lux-Current

In this paper, the photosensitive effect of n-type low-temperature polycrystalline-silicon thin-film transistors (TFTs) is investigated. A novel layout is adopted to demonstrate that the photo leakage current occurs in the depletion region at the drain junction. Based on the Poole–Frenkel effect lowering of a coulombic barrier and phonon-assisted tunneling, it is discovered that the photosensitivity behavior for poly-Si TFT is dependent on the gate and drain bias. However, this photoinduced leakage current behavior is not included in the present SPICE device model. Therefore, a new parameter, unit-lux-current (ULC), is proposed to depict the photoinduced current. Its dependence on the gate/drain bias and temperature is discussed, and the equation of ULC is further derived, which has good agreement with the experimental data. A qualitative deduction is developed to account for the photo leakage mechanism. ULC variation with respect to defect states in the drain region is also discussed.      

A self-consistent pseudo-two-dimensional model for hot-electron current in MOST' s

A theoretical formulation for the hot-electron currents (substrate and gate currents) in MOST's with nonuniform impurity profile has been built. By applying a gradual channel approximation for the source section and a pseudo-two-dimensional approximation for the drain section, saturation voltage is obtained by considering the voltage and channel current continuity at the boundary of the two sections. Three fitting parameters in the model are determined by comparing the theoretical calculation results with the observed substrate current in samples with various device parameters. The present model was successfully applied to describe the two experimental results: the gate oxide thickness dependence of the gate current injection efficiency and the kink in the maximum channel electric field strength versus gate voltage (= drain voltage) relation. The nonuniform channel impurity profile is approximated by the modified Gaussian distribution, which is found to agree well with the estimation by the substrate bias effect of MOST's. The calculated gate currents for the device can well explain the implantation energy dependence of the measured gate currents.     

Four-terminal field-effect transistors for amplitude modulation

An amplitude modulator using a field-effect tetrode transistor (FETT) is investigated. The operation of the modulation circuit is based on the `linear mode' where the transconductance from one gate to the drain is a linear function of the bias signal at the other gate. Experimental result shows that the modulator has good linearity for RF application.     

Distributed modeling of switching transients in GaAs MESFET's

The transient phenomena resulting from the application of a step bias at the gate electrode of a GaAs MESFET have been simulated using a two-dimensional model. Results emphasizing the effects of the displacement current in high-speed devices are presented. The causes of the delay are discussed for devices of different gate lengths, and the effects of the distributed gate capacitance and the related delay in the drain current characteristics are incorporated in an equivalent circuit model. Analytical expressions derived from large-signal analysis are shown to conform with the results of two-dimensional simulation, allowing for an implementation in simulators such as SPICE     

The effect of high fields on MOS device and circuit performance

A simple analytical model for the MOS device characteristics including the effect of high vertical and horizontal fields on channel carrier velocity is presented. Analytical expressions for the drain current, saturation drain voltage, and transconductance are developed. These expressions are used to examine the effect of scaling the channel length, the gate dielectric thickness, and the bias voltage on device characteristics. Experimental results from various geometry MOS devices are used to verify the trends predicted by the model. Using the physical understanding provided by the model, we examine the effect of device geometry scaling on circuit performance. We suggest that for gate capacitance-limited circuits one should reduce the channel length, and for parasitic capacitance-limited circuits one should reduce the gate dielectric thickness to improve circuit performance.     

基于非线性电阻的GaN HEMT经验基大信号模型

为了实现建立准确的氮化镓高电子迁移率晶体管（GaN high electron mobility transistor,GaN HEMT）大信号模型的目的,提出了一种基于非线性电阻的GaN HEMT经验基大信号模型. 通过对GaN HEMT在高漏极偏置和高电流密度下的电阻特性分析,将受漏源电流控制的非线性电阻模型嵌入经验基大信号模型中. 结合Matlab和ADS提取模型初值,在ADS中建立完整的大信号符号定义模型. 选择栅长为0.25 μm,栅宽分别为2×200 μm、2×250 μm、4×200 μm的GaN HEMT进行直流输出特性和大信号输出特性仿真验证,结果表明本文模型与测试数据具有较高的吻合性. 该大信号模型提高了经验基大信号模型的物理特性,具有较高的精度及良好的缩放性.     

Modelling drain and gate dependence of HEMT 1-50 GHz, small-signalS-parameters, and d.c. drain current

We present refinements to a previously validated HEMT model that improves the model's accuracy as a function of drain bias for simulating d.c. drain current and 1-50 GHz, small-signal S-parameters. By comparing simulation data with experimental data for a 0.4-μm-gate pseudomorphic HEMT, we have been able to establish the accuracy of the refined model, which predicts the device's d.c. current and S-parameters as a function of the applied drain and gate biases to within an accuracy of ~5%. The core of the model and, in particular, its bias dependence, are directly dependent on the HEMT wafer structure and the physical gate length     

Compact modeling of a flash memory cell including substrate-bias-dependent hot-electron gate current

We propose a compact model for a Flash memory cell that is suitable for circuit simulation. The model includes a hot-electron gate current model that considers not only channel hot electron injection but also channel initiated secondary electron injection to express properly substrate bias dependence of gate current. Tunneling gate current for erasing is expressed by the BSIM4 tunneling gate current model. Good agreement between measured and simulated results of both programming and erasing characteristics for 130-nm technology Flash memory cells indicates that our model is useful in designing and optimizing circuit for Flash memories.     

Temperature dependence of hot carrier induced MOSFET degradation at low gate bias

This paper reports a new experimental finding on the temperature dependence of the substrate current and hot carrier induced device degradation at low gate bias. It has been found that the substrate current increases and the drain current degradation is more significant for high operating temperature at low gate bias. It has been observed that the hot carrier induced performance degradation of a latch-type input buffer increases at the elevated temperature.